CN1929146A - Solid-state imaging device and method of manufacturing same - Google Patents
Solid-state imaging device and method of manufacturing same Download PDFInfo
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- CN1929146A CN1929146A CN 200610137523 CN200610137523A CN1929146A CN 1929146 A CN1929146 A CN 1929146A CN 200610137523 CN200610137523 CN 200610137523 CN 200610137523 A CN200610137523 A CN 200610137523A CN 1929146 A CN1929146 A CN 1929146A
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Abstract
A solid-state imaging device includes: a semiconductor substrate; and a signal processing section provided on a backside of the semiconductor substrate. The semiconductor substrate has; a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion section formed in a surface portion of the semiconductor substrate; a second impurity region of the first conductivity type formed below the first impurity region; and a first gate electrode penetrating the semiconductor substrate in a thickness direction of the semiconductor substrate, the first gate electrode transferring the signal charge stored in the first impurity region to the second impurity region. The signal processing section receives the signal charge transferred to the second impurity region.
Description
The cross reference of related application
The application based on and require the priority of the No.2006-197075 of Japanese patent application formerly of the No.2005-257085 of Japanese patent application formerly of on September 5th, 2005 application and application on July 18th, 2006, quote its full content as a reference at this.
Technical field
The present invention relates to a kind of solid camera head and manufacture method thereof.
Background technology
In recent years, in solid camera heads such as cmos image sensor, because the requirement of miniaturization and many pixelations is advancing the miniaturization of Pixel Dimensions.Now, solid camera head is constituted as and is forming the such wiring of vertical signal line except colour filter and lenticule etc. on the photodiode.
But if further advance the miniaturization of Pixel Dimensions and make more multi-layeredization of wiring, then as in the above-mentioned structure, owing to the distance that increases from the sensor surface to the photodiode, so the light of oblique incidence produces interference (shade) to wiring.Its result, light is difficult to arrive photodiode, and light reduces to the incident efficient of photodiode.
In addition, a kind of technology is disclosed, its element separating layer between pixel is embedded in gate electrode, by this gate electrode, to be sent to the N type floating diffusion region territory (for example, with reference to patent documentation 1) that on N type extrinsic region, forms at the signal charge of the N type extrinsic region stored that constitutes photodiode.But in this technology, owing to form the wiring of vertical signal etc. on photodiode, it is difficult therefore will addressing the above problem.
[patent documentation 1] spy opens the 2005-38908 communique
Summary of the invention
According to a kind of mode of the present invention, a kind of solid camera head is provided, it is characterized in that, comprising:
Semiconductor substrate, it comprises:
In above-mentioned semiconductor substrate, form, and the 1st extrinsic region of the 1st conduction type of the signal charge that generates of the opto-electronic conversion of storage by the photoelectric conversion part that forms in the skin section of above-mentioned semiconductor substrate;
In above-mentioned semiconductor substrate and the 2nd extrinsic region of above-mentioned the 1st conduction type that under above-mentioned the 1st extrinsic region, forms; And
Thickness direction at above-mentioned semiconductor substrate connects above-mentioned semiconductor substrate, and the signal charge that will be stored in above-mentioned the 1st extrinsic region is sent to the 1st gate electrode of above-mentioned the 2nd extrinsic region; And
Form in the rear side of above-mentioned semiconductor substrate, and the signal processing part of the signal charge that transmits to above-mentioned the 2nd extrinsic region of input.
According to another kind of mode of the present invention, a kind of solid camera head is provided, it is characterized in that, comprising:
Semiconductor substrate, it comprises:
The 1st extrinsic region of the 1st conduction type of the signal charge that the opto-electronic conversion that forms in above-mentioned semiconductor substrate, store the photoelectric conversion part that forms by the skin section at above-mentioned semiconductor substrate generates;
The 2nd extrinsic region of above-mentioned the 1st conduction type that in above-mentioned semiconductor substrate and at above-mentioned the 1st extrinsic region, forms below more; And
Thickness direction at above-mentioned semiconductor substrate connects above-mentioned semiconductor substrate, and the signal charge that will be stored in above-mentioned the 1st extrinsic region is sent to the 1st gate electrode of above-mentioned the 2nd extrinsic region; And
Contact and arrive spill and leakage (overflow drain) unit of the 1st conduction type at the back side of above-mentioned semiconductor substrate with above-mentioned the 1st extrinsic region; And
At the rear side of above-mentioned semiconductor substrate signal processing part that form, that import the signal charge that transmits to above-mentioned the 2nd extrinsic region.
According to another kind of mode of the present invention, a kind of manufacture method of solid camera head is provided, it is characterized in that, comprising:
Be formed for storing the operation of the 1st extrinsic region of the 1st conduction type of the signal charge that generates by opto-electronic conversion in the skin section of semiconductor substrate;
Form the operation of the groove that connects semiconductor substrate;
By import the impurity of the 1st conduction type at least one side of above-mentioned groove, in above-mentioned semiconductor substrate, form the operation of the 2nd extrinsic region of the 1st conduction type below more at above-mentioned the 1st extrinsic region;
In above-mentioned groove, embed electric conducting material across dielectric film, form the operation of gate electrode; And
Form the operation of above-mentioned signal processing part in the rear side of above-mentioned semiconductor substrate.
Description of drawings
Fig. 1 is the typical sectional arrangement drawing according to the cmos image sensor 1 of the 1st execution mode of the present invention.
Fig. 2 be according to the omission of the 1st execution mode of the present invention the Typical Planar figure of cmos image sensor 1 of state of lenticule and colour filter.
Fig. 3 be according to the omission of the 1st execution mode of the present invention the Typical Planar figure of another kind of cmos image sensor 1 of state of lenticule and colour filter.
Fig. 4 is the typical circuit figure according to the cmos image sensor 1 of the 1st execution mode of the present invention.
Fig. 5 A～C is the flow chart making of typically representing according to the cmos image sensor 1 of the 1st execution mode of the present invention.
Fig. 6 A～C is the flow chart making of typically representing according to the cmos image sensor 1 of the 1st execution mode of the present invention.
Fig. 7 A～C is the flow chart making of typically representing according to the cmos image sensor 1 of the 1st execution mode of the present invention.
Fig. 8 A～C is the flow chart making of typically representing according to the cmos image sensor 1 of the 1st execution mode of the present invention.
Fig. 9 be according to the omission of the 2nd execution mode of the present invention the Typical Planar figure of state of the lenticule of cmos image sensor 101 and colour filter.
Figure 10 is the sectional arrangement drawing along the A-A line of cmos image sensor shown in Figure 9 101.
Figure 11 is the sectional arrangement drawing along the B-B line of cmos image sensor shown in Figure 9 101.
Figure 12 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 13 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 14 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 15 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 16 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 17 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 18 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 19 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 20 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Figure 21 A, B are the flow chart makings of typically representing according to the cmos image sensor 101 of the 2nd execution mode of the present invention.
Embodiment
Below, with reference to the description of drawings execution mode.In addition, in the present embodiment,, the example that uses cmos image sensor is described as solid camera head.
(the 1st execution mode)
Fig. 1 is the typical sectional arrangement drawing according to the cmos image sensor of the 1st execution mode of the present invention, Fig. 2 be according to the omission of the 1st execution mode of the present invention the Typical Planar figure of cmos image sensor of state of lenticule and colour filter.Fig. 3 be according to the omission of the 1st execution mode of the present invention the Typical Planar figure of another kind of cmos image sensor of state of lenticule and colour filter, Fig. 4 is the typical circuit diagram according to the cmos image sensor of the 1st execution mode of the present invention.
Shown in Fig. 1 and 2, cmos image sensor 1 comprises the semiconductor substrate 2 of the about 100 μ m of thickness.For example, semiconductor substrate 2 has: P type Si substrate (the 5th extrinsic region) 3; The P that form on P type Si substrate 3 and impurity concentration is higher than P type Si substrate 3
+Type epitaxial loayer (the 4th extrinsic region) 4; And at P
+That form on the type epitaxial loayer 4 and impurity concentration and P type Si substrate 3 P type epitaxial loayer (the 3rd extrinsic region) 5 about equally.
In addition, owing to have aforesaid sandwich construction, so the thickness of semiconductor substrate 2 depends on the thickness of each layer etc., can suitably change from a few μ m orders of magnitude to the hundreds of μ m order of magnitude and be used.
The impurity concentration of P type Si substrate 3 and P type epitaxial loayer 5 is 1.0 * 10
18/ cm
3About, P
+The impurity concentration of type epitaxial loayer 4 is 1.0 * 10
20/ cm
3About.In addition, P
+The gross thickness of type epitaxial loayer 4 and P type epitaxial loayer 5 is about 5～10 μ m.
At semiconductor substrate 2, form the groove 2a of the thickness direction that connects semiconductor substrate 2.The width of groove 2a is about about 0.8 μ m.
Inwall at groove 2a forms gate insulating film 6, at the medial region formation gate electrode 7 of gate insulating film 6.Gate electrode (the 1st gate electrode) 7 is used for reading out in the signal charge that N type extrinsic region described later (the 1st extrinsic region) 9 is stored by applying voltage, and sends it to charge storage region 13 described later.That is, form transmission transistor 8 in this part, wherein with N type extrinsic region 9 as the source, gate electrode 7 is as grid, charge storage region (the 2nd extrinsic region) 13 is as leaking.In addition, to Width (the paper transverse direction among Fig. 2) adjacent gate electrodes 7 of groove 2a, apply common voltage by the control line 29 of reading described later.
Be formed with the N type extrinsic region 9 as the 1st extrinsic region on the top as the P type epitaxial loayer 5 of the skin section of semiconductor substrate 2, an one side is across gate insulating film 6 and gate electrode 7 adjacency.At this, constitute the photodiode 10 that converts the photoelectric conversion part of signal charge as light to by P type epitaxial loayer 5 and N type extrinsic region 9 with incident, and at the signal charge of N type extrinsic region 9 storages by the opto-electronic conversion generation.
A sidepiece with gate electrode 7 adjacency in the N type extrinsic region 9 forms deeplyer than the other parts of N type extrinsic region 9, and the bottom surface of this sidepiece and P
+Type epitaxial loayer 4 adjacency.Another side of N type extrinsic region 9 and raceway groove termination zone (the 8th extrinsic region) 11 adjacency that are used to realize that the element between the pixel P separates.
Raceway groove stops zone 11 by P
+The type extrinsic region constitutes, and at P type epitaxial loayer 5, P
+The top of type epitaxial loayer 4 and P type Si substrate 3 forms.Raceway groove stops the side in zone 11 and gate insulating film 6 adjacency of pixel adjacent P.That is, raceway groove stops that zone 11 Widths at groove 2a (the paper transverse direction among Fig. 2) are gone up and gate insulating film 6 is arranged side by side.
As shown in Figure 3, raceway groove stops zone 11 and also can form semiconductor substrate 2 in, N type extrinsic region 9 adjacency of feasible and two sides adjacent pixels P.That is, raceway groove stops that zone 11 length directions at groove 2a (the paper above-below direction among Fig. 3) are gone up and gate insulating film 6 is arranged side by side.In this case, the separation of the element between a pixel P part is undertaken by raceway groove termination zone 11 by gate insulating film 6, remainder.
In addition, in Fig. 2 and Fig. 3, the element between the pixel P of the Width of groove 2a separates and stops zone 11 by gate insulating film 6 and raceway groove and carry out, and the element of the longitudinal direction between the pixel P separate by the semiconductor substrate 2 in this part form as P
+The raceway groove of type extrinsic region stops zone (the 7th extrinsic region) 12 to carry out.
Under the N type extrinsic region 9 and in P type Si substrate 3, form as the charge storage region 13 that is transmitted in the 2nd extrinsic region of the signal charge of storage in the N type extrinsic region 9.Charge storage region 13 is made of N type extrinsic region, and an one side is across gate insulating film 6 and gate electrode 7 adjacency, upper surface and P
+ Type epitaxial loayer 4 adjacency.
In the bottom of P type Si substrate 3,, form the floating diffusion region territory (the 6th extrinsic region) 14 (being " FD zone ") that is transmitted in the signal charge of storage in the charge storage region 13 to call this zone in the following text as the part of signal processing part 20 described later.FD zone 14 is made of N type extrinsic region.When the signal charge that will store is sent to FD zone 14, gate electrode (the 2nd gate electrode) 21a of transmission transistor 21 described later is applied voltage in charge storage region 13.
In the face side of semiconductor substrate 2, form colour filter 15; On colour filter 15, form the lenticule 16 that conduct is used for optically focused and imports light into the lens of photodiode 10.
In the rear side (rear side of P type Si substrate 3) of semiconductor substrate 2, be formed for the signal processing part 20 of input transfer to the signal charge of charge storage region 13.As shown in Figure 4, signal processing part 20 has: transmission transistor 21, reset transistor 22, amplifier transistor 23, vertically select transistor 24, level to select transistor 25, vertical scanning circuit 26, horizontal scanning circuit 27, CDS circuit (correlated double sample circuit) 28, read control line 29,30, the control line 31 that resets, drain line 32, vertical signal line 33, horizontal signal lines 34, vertically select control line 35, level to select control line 36, amplifier 37 etc.
The signal charge that reset transistor 22 regularly will be stored in FD zone 14 resets, and the source electrode of reset transistor 22 is electrically connected with FD zone 14, and grid is electrically connected with the control line 31 that resets, and drain electrode is electrically connected with drain line 32.
In addition, each pixel P comprises: photodiode 10, transmission transistor 8,21, reset transistor 22, amplifier transistor 23 and vertically select transistor 24.
26 pairs in vertical scanning circuit is read control line 29 grades and is applied voltage, and control transmission transistor 8 etc.; And 27 pairs of levels of horizontal scanning circuit select control line 36 to apply voltage, and controlling level is selected transistor 25.
CDS circuit 28 is used for removing the fixed pattern noise that the deviation of the threshold voltage of transmission transistor 8 grades that comprise owing to pixel P causes, and between vertical signal line 33.CDS circuit 28 is made of for example 2 capacitors (not shown), sampling transistor (not shown) and clamping transistor (not shown).
The operation of cmos image sensor 1 is carried out as follows.At first, apply voltage, make vertical selection transistor 24 conductings, and select specific pixel column by 26 pairs of vertical control lines 35 of selecting of vertical scanning circuit.
Then, under this state, read control line 29 by 26 pairs in vertical scanning circuit and apply voltage, make transmission transistor 8 conductings, the signal charge that will store in N type extrinsic region 9 is sent to charge storage region 13.
Then, under the state that transmission transistor 8 ends, read control line 30 by 26 pairs in vertical scanning circuit and apply voltage, make transmission transistor 21 conductings, the signal charge that will store in charge storage region 13 is sent to FD zone 14.
In FD zone 14, owing to, therefore export the current signal corresponding to vertical signal line 33 with this potential change from amplifier transistor 23 because of the transfer operation of this signal charge produces potential change.In addition, apply voltage, make reset transistor 22 conductings, the current potential in the FD zone 14 that resets by the control line 31 that resets by 26 pairs in vertical scanning circuit.
The current signal that outputs to vertical signal line 33 outputs to horizontal signal lines 34 via selecting the level of conducting to select transistor 25 by CDS circuit 28 and horizontal scanning circuit 27, is amplified by amplifier 37, and outputs to the outside.
At first, shown in Fig. 5 A, be on the P type Si substrate 3 of hundreds of μ m at thickness, form P
+After this type epitaxial loayer 4, forms P type epitaxial loayer 5, thereby forms semiconductor substrate 2.
After forming semiconductor substrate 2, shown in Fig. 5 B, form resist figure 41 by photoetching process, after this, with resist figure 41 as mask, adopt ion implantation that N type impurity such as phosphorus and arsenic are injected P type epitaxial loayer 5, at the N type extrinsic region 42 of P type epitaxial loayer 5 formation as the part of N type extrinsic region 9.
After forming N type extrinsic region 42, remove resist figure 41, after this, shown in Fig. 5 C,, make the N type diffusion of impurities that constitutes N type extrinsic region 42 by annealing.Like this, the degree of depth of N type extrinsic region 42 is about 1～2 μ m.
After forming N type extrinsic region 42, at the SiO that forms on the P type epitaxial loayer 5 about thick 3 μ m
2Film 43.After this, as shown in Figure 6A, grind the back side of P type Si substrate 3, make that the thickness of semiconductor substrate 2 is about 100 μ m.In addition, the thickness that also can prepare semiconductor substrate 2 in advance is the thin P type Si substrate 3 about 100 μ m, forms P on this P type Si substrate 3
+ Type epitaxial loayer 4 and P type epitaxial loayer 5.In this case, can save the time at the back side of grinding P type Si substrate 3.
After the back side of having ground P type Si substrate 3, at SiO
2Form resist figure (not shown) by photoetching process on the film 43, after this, the resist figure as mask, is utilized reactive ion etching (RIE) etching SiO
2Film 43.Then, remove the resist figure.Then, shown in Fig. 6 B, the SiO of figure will be formed
2 Film 43 utilizes reactive ion etching or wet etching at thickness direction etching semiconductor substrate 2 as mask, forms groove 2a.At this, the control etching stops its top that arrives P type Si substrate 3.
Etching shown in Fig. 6 C, utilizes the angle-tilt ion injection method after the top of P type Si substrate 3, the p type impurities such as inwall injection boron to groove 2a one side form raceway groove and stop zone 11.
After forming raceway groove termination zone 11, shown in Fig. 7 A, with SiO
2Film 43 utilizes reactive ion etching or wet etch etches P type Si substrate 3 as mask, and groove 2a is connected.
Make after the groove 2a perforation, shown in Fig. 7 B, utilize the angle-tilt ion injection method, inwall to the groove 2a relative with the inwall that forms raceway groove termination zone 11 injects N type impurity, in P type epitaxial loayer 5, form N type extrinsic region 9, the side of one side and groove 2a adjacency, and the lower surface of end and P
+ Type epitaxial loayer 4 adjacency; In P type Si substrate 3, form charge storage region 13, the side of one side and groove 2a adjacency, and upper surface and P simultaneously
+Type epitaxial loayer 4 adjacency.
After this, make the p type impurity that constitutes raceway groove and stop zone 11, the N type diffusion of impurities that constitutes N type extrinsic region 9 and charge storage region 13 by annealing.In addition, in Fig. 7 B, show the situation of injecting N type impurity from the surface of semiconductor substrate 2 and both sides, the back side and forming N type extrinsic region 9 and charge storage region 13, but also can only inject N type impurity, form N type extrinsic region 9 and charge storage region 13 from the face side of semiconductor substrate 2 and a side of rear side.
Then, the inwall of thermal oxidation groove 2a shown in Fig. 7 C, forms gate insulating film 6, after this, for example inserts electric conducting materials such as polysilicon in the medial region of gate insulating film 6, forms gate electrode 7.After forming gate electrode 7, grind the surface and the back side of (CMP) grinding semiconductor substrate 2 by mechanochemistry.In addition, remove SiO by this operation
2Film 43.
After the surface and the back side of having ground semiconductor substrate 2, utilize photoetching process to form resist figure (not shown) in the rear side of semiconductor substrate 2, with the resist figure as mask, utilize ion implantation to inject N type impurity to the bottom of P type Si substrate 3, shown in Fig. 8 A, form FD zone 14 in the bottom of P type Si substrate 3.Then, make the N type diffusion of impurities that constitutes FD zone 14 by annealing.
After forming FD zone 14, remove the resist figure, after this, shown in Fig. 8 B, at the rear side formation signal processing part 20 of P type Si substrate 3.In addition, from the efficient aspect, preferably, use and the wiring pad identical materials (for example aluminium) that in signal processing part 20, forms, form gate electrode 21a by the operation identical, but also can use polysilicon, form gate electrode 21a by the operation different with the wiring pad with the wiring pad.
At last, shown in Fig. 8 C, on N type extrinsic region 9, utilize photoetching process to form colour filter 15, and then on colour filter 15, form lenticule 16.By like this, produce cmos image sensor shown in Figure 11.
In the present embodiment, as shown in Figure 1, owing to form signal processing part 20 in the rear side of semiconductor substrate 2, therefore, the light that incides the photodiode 10 that forms in semiconductor substrate 2 can not interfered the generations such as wiring of signal processing part 20.Like this, even also can arrive photodiode 10 for the light of photodiode 10 oblique incidences, its result can improve the incident efficient of elder generation to first electric diode 10.
At this, forming on the rear side of semiconductor substrate 2 under the situation of signal processing part 20, though need transmit signal charge to signal processing part 20 from N type extrinsic region 9, but, in the present embodiment, owing to be formed with charge storage region 13 9 times at N type extrinsic region, and in semiconductor substrate 2, form gate electrode 7, therefore the signal charge that is stored in the N type extrinsic region 9 can be sent to signal processing part 20.
In the present embodiment, owing to form signal processing part 20, therefore can increase the zone of photodiode 10 in the plane of cmos image sensor in the rear side of semiconductor substrate 2.Therefore, can improve the incident efficient of light more to photodiode 10.In addition, because lenticule 16 can be omitted in the zone (minimizing inactive area) that can increase photodiode 10 therefore on colour filter 15.
In the present embodiment, as shown in Figure 3, form at the length direction of groove 2a and to stop zone 11 with gate insulating film 6 raceway groove arranged side by side and carry out to suppress the decline of the mechanical strength of semiconductor substrate 2 under the situation that the element between the pixel P separates.Promptly, though gate insulating film 6 and gate electrode 7 form in the groove 2a that connects semiconductor substrate 2, but, because very narrow between the pixel P on the length direction of groove 2a, therefore, arranging under the situation of groove 2a along the length direction of groove 2a, worrying that the mechanical strength of semiconductor substrate 2 descends.
Relative therewith, form at the length direction of groove 2a and to stop zone 11 with gate insulating film 6 raceway groove arranged side by side and carry out under the situation that the element between the pixel P separates, the shared ratio of the groove 2a relative with semiconductor substrate 2 has reduced.Therefore, can suppress the decline of the mechanical strength of semiconductor substrate 2.
In addition, the present invention is not limited to the record content of above-mentioned execution mode, and its structure and material, each configuration of components etc. under the scope that does not break away from spirit of the present invention, can be carried out suitable change.For example, in the above-described embodiment,,, also can be ccd image sensor though cmos image sensor 1 is illustrated as solid camera head.
In the above-described embodiment, though the 1st extrinsic region is described as N type extrinsic region 9, the 1st extrinsic region also can be the zone different with N type extrinsic region 9.That is, the 1st extrinsic region also can be the N type extrinsic region that directly or indirectly transmits signal charge from N type extrinsic region 9.
In the above-described embodiment, though the 2nd extrinsic region is described as charge storage region 13, but, signal charge be not sent under the situation in FD zone 14 from N type extrinsic region 9 by gate electrode 7 via charge storage region 13, also can be with the 2nd extrinsic region as FD zone 14.
(the 2nd execution mode)
It from Fig. 9 to Figure 11 the exemplary block diagram of the cmos image sensor 101 of the 2nd execution mode of the present invention.Fig. 9 be the 2nd execution mode of the present invention omission the Typical Planar figure of cmos image sensor of state of lenticule and colour filter.Figure 10 and Figure 11 are respectively along the sectional arrangement drawing of the A-A line of cmos image sensor shown in Figure 9 101 with along the sectional arrangement drawing of B-B line.In addition, the typical circuit figure of the cmos image sensor 101 of present embodiment is identical with Fig. 4, in this omission.
In the present embodiment, compare with above-mentioned the 1st execution mode, difference is, the substantial middle portion in zone 11 is provided with spill and leakage unit 31 on the raceway groove that plays the element centrifugation between the adjacent pixels P is whole, and p type impurity layer 32 is set to stop the relative mode in zone 11 and spill and leakage unit 31 with raceway groove, identical about other structure with the execution mode of front.In addition, for the structural element identical, use identical reference marks with the execution mode of front.
As shown in Figure 10 and Figure 11, cmos image sensor 101 comprises the semiconductor substrate 2 of the about 100 μ m of thickness.Semiconductor substrate 2 and the 1st execution mode comprise in the same manner: P type Si substrate (the 5th extrinsic region) 3 for example, the P that forms on P type Si substrate 3 and impurity concentration is higher than P type Si substrate 3
+Type epitaxial loayer (the 4th extrinsic region) 4, and at P
+That form on the type epitaxial loayer 4 and impurity concentration and P type Si substrate 3 P type epitaxial loayer (the 3rd extrinsic region) 5 about equally.In addition, owing to have above-mentioned sandwich construction, the thickness of semiconductor substrate 2 depends on the thickness of each layer etc., can the order of magnitude from the order of magnitude of a few μ m to hundreds of μ m suitably changes and is used.
The impurity concentration of P type Si substrate 3 and P type epitaxial loayer 5 is for example 1.0 * 10
18/ cm
3About, P
+The impurity concentration of type epitaxial loayer 4 is for example 1.0 * 10
20/ cm
3About.In addition, P
+The gross thickness of type epitaxial loayer 4 and P type epitaxial loayer 5 is for for example about 5～10 μ m.
In semiconductor substrate 2, form the groove 2a of the thickness direction that connects semiconductor substrate 2.The width of groove 2a is for for example about about 0.8 μ m.
Inwall at groove 2a forms gate insulating film 6, at the medial region formation gate electrode 7 (the 1st gate electrode) of gate insulating film 6.Gate electrode 7 is identical with the execution mode of front, is used for reading out in the signal charge that N type extrinsic region 9 is stored by applying voltage, and sends it to charge storage region 13.That is, in this part, form transmission transistor 8, wherein with N type extrinsic region 9 as the source, gate electrode 7 is as grid, charge storage region 13 is as leaking.In addition, to the adjacent gate electrode 7 of Width (the paper transverse direction among Figure 10 and Figure 11) of groove 2a, apply common voltage by the control line of in aforementioned embodiments, putting down in writing 29 of reading.
Be formed with the N type extrinsic region 9 as the 1st extrinsic region on P type epitaxial loayer 5 tops as the skin section of semiconductor substrate 2, an one side is across p type impurity zone 32 and gate insulating film 6 and gate electrode 7 adjacency.At this, constitute the photodiode 10 that converts the photoelectric conversion part of signal charge as light to by P type epitaxial loayer 5 and N type extrinsic region 9, the signal charge that storage produces by opto-electronic conversion in N type extrinsic region 9 with incident.
The bottom surface in p type impurity zone 32 forms deeplyer than the bottom surface of N type extrinsic region 9, this bottom surface and P
+The upper surface abut of type epitaxial loayer 4.In addition, as shown in figure 10, side of N type extrinsic region 9 be used to realize that the raceway groove that the element between the pixel P separates stops zone (the 8th extrinsic region) 11 adjacency.
Raceway groove stops zone 11 as P
+The type extrinsic region is at P type epitaxial loayer 5, P
+The top of type epitaxial loayer 4 and P type Si substrate 3 forms.Raceway groove stops the side in zone 11 and gate insulating film 6 adjacency of pixel adjacent P.That is, raceway groove stops that zone 11 Widths at groove 2a (the paper transverse direction among Figure 10) are gone up and gate insulating film 6 is arranged side by side.
Raceway groove termination zone 11 length directions at groove 2a (the paper above-below direction among Fig. 9) are last and gate insulating film 6 is arranged side by side.In this case, the separation of the element between a pixel P part is undertaken by raceway groove termination zone 11 by gate insulating film 6, remainder.
In addition, in Fig. 9 to Figure 11, element between the pixel P of the Width of groove 2a separates and stops zone 11 by gate insulating film 6 and raceway groove and carry out, as shown in Figure 9, the element of the longitudinal direction between the pixel P (depth direction) separate by the semiconductor substrate 2 in this part form as P
+The raceway groove of type extrinsic region stops zone 12 to carry out.
Under N type extrinsic region 9 and in the P type Si substrate 3, be formed with as the charge storage region 13 that is transmitted in the 2nd extrinsic region of the signal charge of storage in the N type extrinsic region 9.Charge storage region 13 is made of N type extrinsic region, and an one side is across gate insulating film 6 and gate electrode 7 adjacency, the upper surface of charge storage region 13 and P
+The bottom surface adjacency of type epitaxial loayer 4.
In the bottom of P type Si substrate 3, put down in writing as the execution mode of front, as the part of signal processing part 20, be formed for being transmitted in the FD zone (the 6th extrinsic region) 14 of the signal charge of charge storage region 13 storages.FD zone 14 is made of N type extrinsic region.In the time will being sent to FD zone 14 at the signal charge of charge storage region 13 storage, put down in writing in the execution mode as the front, gate electrode (the 2nd gate electrode) 21a of transmission transistor 21 is applied voltage.
On the other hand, as shown in figure 11, spill and leakage unit 31 is with respect to the side of the groove 2a that transmission transistor 8 is set in pixel P, be provided with in the side towards its Width (the paper transverse direction among Figure 11), perhaps the gate insulating film along its side forms at longitudinal direction (thickness direction of cmos image sensor 101).This drain electrode unit 31 comprises: contain the 1st spill and leakage layer 31a than the N type impurity of N type impurity concentration lower concentration in the N type extrinsic region 9, contain the 2nd spill and leakage layer 31b than the N type impurity of the 1st spill and leakage layer 31a lower concentration, and with the 3rd spill and leakage layer 31c of the roughly the same N type impurity concentration of the 1st spill and leakage layer 31a.
In addition, these 3 spill and leakage layers are to form according to manufacture method shown below, for the integral body of these layers works as the spill and leakage unit, must make the N type impurity concentration of each spill and leakage layer, particularly the 1st spill and leakage layer 31a lower than the N type impurity concentration in the N type extrinsic region 9.
In above-mentioned the 1st execution mode, in the photodiode 10 that constitutes by P type epitaxial loayer 5 and N type extrinsic region 9, if incident is more than or equal to the light (mainly being the light of visible wavelength band) of its allowance, then produce superfluous electronics by opto-electronic conversion, it is medium that this superfluous electronics flows into pixel adjacent, and detect as noise.
Relative therewith, in the present embodiment, as mentioned above, owing to be provided with spill and leakage unit 31, therefore, in the N type extrinsic region 9 in photodiode 10, the excess electron that produces more than or equal to the light (mainly being the light of visible wavelength band) of allowance by incident is by this spill and leakage unit 31, and discharges to the outside of semiconductor substrate 2 via drain line from the drain portion of reset transistor 22 (not shown).Therefore, can prevent above-mentioned excess electron, and suppress it and become noise source to adjacent pixels inflow etc.
In addition, in the present embodiment, as shown in figure 11, because above-mentioned P+ type impurity layer 32 is set, therefore, in the N type extrinsic region 9 that is connected with transmission transistor 8, suppressed because the gathering of the electric charge that this current potential decline causes.Its result, when resetting transmission transistor 8, above-mentioned excess electron is adverse current in photodiode 10, and suppressing it becomes noise source.
In addition, preferably, the N type impurity concentration of the 1st spill and leakage layer 31a in the spill and leakage unit 31 particularly, can be 5 * 10 than the ratio of low about 1 order of magnitude of N type extrinsic region 9
15Cm
-3～1 * 10
16Cm
-3In addition, preferably, the N type impurity concentration of the 2nd spill and leakage layer 31b particularly, can be 1 * 10 than the ratio of N type extrinsic region 9 high about 1 order of magnitude
17Cm
-3～5 * 10
17Cm
-3In addition, preferably, the N type impurity concentration of N type extrinsic region 9 is 5 * 10
16Cm
-3～1 * 10
17Cm
-3
In the face side of semiconductor substrate 2, form colour filter 15, and on colour filter 15, be formed for optically focused and the lenticule 16 as lens of photoconduction to photodiode 10.
In the rear side (rear side of P type Si substrate 3) of semiconductor substrate 2, be formed for the signal processing part 20 of input transfer to the signal charge of charge storage region 13.As shown in Figure 4, signal processing part 20 has: transmission transistor 21, reset transistor 22, amplifier transistor 23, vertically select transistor 24, level to select transistor 25, vertical scanning circuit 26, horizontal scanning circuit 27, CDS circuit (correlated double sample circuit) 28, read control line 29,30, the control line 31 that resets, drain line 32, vertical signal line 33, horizontal signal lines 34, vertically select control line 35, level to select control line 36 and amplifier 37 etc.
In following record, because transmission transistor 21 is identical with above-mentioned the 1st execution mode, therefore in this description will be omitted.
In addition, in the cmos image sensor 101 of present embodiment, also can drive in the same manner with above-mentioned the 1st execution mode according to circuit shown in Figure 4.
In the present embodiment, owing to form signal processing part 20 in the rear side of semiconductor substrate 2, the light that therefore incides the photodiode 10 that forms in semiconductor substrate 2 can not interfered the generations such as wiring of signal processing part 20 yet.Like this, even also can arrive photodiode 10 with respect to the light of photodiode 10 oblique incidences, its result can improve the incident efficient of light to photodiode 10.
Further, because across P
+Impurity layer 32 N type extrinsic region 9 more below form charge storage region 13, and semiconductor substrate 2 in, form gate electrode 7, so can be sent to signal processing part 20 by the signal charge that this transmission transistor 8 will be stored in N type extrinsic region 9.
In addition,, on the other hand, form signal processing part 20, therefore can increase the zone of the photodiode 10 in the plane of cmos image sensor 101 in its rear side owing to form photodiode 10 in the face side of semiconductor substrate 2.Like this, can improve the incident efficient of light more to photodiode 10.In addition, because lenticule 16 can be omitted in the zone (reducing inactive area) that can increase photodiode 10 therefore on colour filter 15.
Further, as shown in Figure 9, form with gate insulating film 6 raceway groove arranged side by side at the length direction (paper above-below direction) of groove 2a and to stop zone 11, the element that carries out between the pixel P separates.Therefore, the zone that the groove 2a of perforation semiconductor substrate 2 occupies is limited in the volume of regulation as required, can suppress the decline of the mechanical strength of semiconductor substrate 2.
The cmos image sensor 101 of present embodiment can be by the making of the following stated.Figure 12～Figure 21 is the figure that typically represents the manufacture process of the cmos image sensor 101 in this example.In addition, in each figure, the figure that represents with reference marks A is equivalent to above-mentioned Figure 10, and expression is along the state of the sectional arrangement drawing of the A-A line of cmos image sensor 101, the figure that represents with reference marks B is equivalent to above-mentioned Figure 11, and expression is along the state of the sectional arrangement drawing of the B-B line of cmos image sensor 101.
At first, as shown in figure 12, on the P type Si of thick hundreds of μ m substrate 3, form P
+ Type epitaxial loayer 4 then, forms P type epitaxial loayer 5, thereby forms semiconductor substrate 2.
Then, as shown in figure 13, utilize photoetching process to form resist figure 41, then, resist figure 41 as mask, is adopted ion implantation, p type impurities such as boron are injected into P type epitaxial loayer 5, and form P
+Type extrinsic region 51.
Then, as shown in figure 14, after removing resist figure 41, new resist figure 44 as mask, is adopted ion implantation,, form N type extrinsic region 42 then as N type extrinsic region 9 with injection P type epitaxial loayers 5 such as N type impurity such as phosphorus and arsenic.
Then, remove resist figure 44, then, as shown in figure 15, make the N type diffusion of impurities that constitutes N type extrinsic region 42, make simultaneously to constitute P by annealing
+The p type impurity diffusion of type extrinsic region 51 forms N type extrinsic region 9, raceway groove termination zone 11 and P respectively
+ Extrinsic region 32.
Then, as shown in figure 16, stop zone 11 and P at N type extrinsic region 9, raceway groove
+Form the SiO about thick 3 μ m on the extrinsic region 32
2Film 43.After this, grind the back side of P type Si substrate 3, make that the thickness of semiconductor substrate 2 is about 100 μ m.In addition, also can prepare thickness as semiconductor substrate 2 in advance and be the thin P type Si substrate 3 about 100 μ m, on this P type Si substrate 3, form P
+ Type epitaxial loayer 4 and P type epitaxial loayer 5.In this case, can save the time at the back side of grinding P type Si substrate 3.
Then, after the back side of grinding P type Si substrate 3, at SiO
2Utilize photoetching process to form resist figure (not shown) on the film 43, after this, the resist figure as mask, is utilized reactive ion etching (RIE) etching SiO
2Film 43.Then, remove the resist figure.Then, as shown in figure 17, the SiO of figure will be formed
2 Film 43 utilizes reactive ion etching or wet etching etching semiconductor substrate 2 on thickness direction as mask, forms groove 2a.At this, carry out etching up to connecting P type Si substrate 3, form groove 2a as through hole.
Then, as shown in figure 18, utilize the angle-tilt ion injection method, N type impurity is injected the inwall of the side of groove 2a, form charge storage region 13.In addition, inject identical N type impurity, form the 1st spill and leakage layer 31a, the 2nd spill and leakage layer 31b and the 3rd spill and leakage layer 31c to the regulation zone of the opposition side of groove 2a.These spill and leakage layers according to as base stage the layer p type impurity concentration, become N respectively
-Type extrinsic region, N
--Type extrinsic region and N
-The type extrinsic region.
Then, the inwall of thermal oxidation groove 2a as shown in figure 19, forms gate insulating film 6, then, for example inserts electric conducting materials such as polysilicon in the medial region of gate insulating film 6, forms gate electrode 7.After forming gate electrode 7, grind the surface and the back side of (CMP) grinding semiconductor substrate 2 by mechanochemistry.In addition, remove SiO by this operation
2Film 43.
Then, utilize photoetching process, at the rear side formation resist figure (not shown) of semiconductor substrate 2, with the resist figure as mask, utilize ion implantation to inject N type impurity, as shown in figure 20, form FD zone 14 in the bottom of P type Si substrate 3 to the bottom of P type Si substrate 3.Then, make the N type diffusion of impurities that constitutes FD zone 14 by annealing.Further, the rear side at P type Si substrate 3 forms signal processing part 20.
In addition, from the efficient aspect, preferably, gate electrode 21a uses and the wiring pad identical materials (for example aluminium) that forms in signal processing part 20, forms by the operation identical with the wiring pad, still, also can use polysilicon, form by the operation different with the wiring pad.
Then, as shown in figure 21, utilize photoetching process, on N type extrinsic region 9, form colour filter 15, and then on colour filter 15, form lenticule 16.Like this, produce the cmos image sensor 101 shown in Fig. 9～11.
Though abovely describe the present invention in detail according to above-mentioned concrete example, the present invention is not limited to foregoing, in the limit that does not depart from the scope of the present invention, can carry out various distortion and change.
Claims (20)
1. a solid camera head is characterized in that, comprising:
Semiconductor substrate, it has:
The 1st extrinsic region at the 1st conduction type of the signal charge of the opto-electronic conversion generation of the photoelectric conversion part of the skin section formation of above-mentioned semiconductor substrate is passed through in storage;
The 2nd extrinsic region of above-mentioned the 1st conduction type that under above-mentioned the 1st extrinsic region, forms; And
The thickness direction of above-mentioned semiconductor substrate connect above-mentioned semiconductor substrate, and the signal charge that will be stored in above-mentioned the 1st extrinsic region be sent to the 1st gate electrode of above-mentioned the 2nd extrinsic region; And
At the rear side of above-mentioned semiconductor substrate signal processing part that be provided with, that import the signal charge that transmits to the 2nd extrinsic region.
2. solid camera head according to claim 1 is characterized in that, above-mentioned semiconductor substrate also has: the 3rd extrinsic region of the 2nd conduction type that is provided with under above-mentioned the 1st extrinsic region.
3. solid camera head according to claim 2, it is characterized in that above-mentioned semiconductor substrate also has: the 4th extrinsic region that between above-mentioned the 2nd extrinsic region and above-mentioned the 3rd extrinsic region, is provided with, compare the 2nd higher conduction type of impurity concentration with above-mentioned the 3rd extrinsic region.
4. solid camera head according to claim 3 is characterized in that, above-mentioned semiconductor substrate also has: under above-mentioned the 4th extrinsic region, be provided with, with the 5th extrinsic region of the 2nd conduction type of above-mentioned the 2nd extrinsic region adjacency.
5. solid camera head according to claim 4 is characterized in that,
Above-mentioned the 5th extrinsic region arrives the rear side of above-mentioned semiconductor substrate;
Above-mentioned semiconductor substrate also has: the 6th extrinsic region of the 1st conduction type that optionally is provided with in above-mentioned the 5th extrinsic region of its rear side.
6. solid camera head according to claim 5 is characterized in that, above-mentioned signal processing part has: the 2nd gate electrode that transmits signal charge from above-mentioned the 2nd extrinsic region to above-mentioned the 6th extrinsic region.
7. solid camera head according to claim 1, it is characterized in that above-mentioned semiconductor substrate also has: the 7th extrinsic region that on the 1st direction of the major surfaces in parallel of above-mentioned relatively semiconductor substrate, extends and cut apart the 2nd conduction type of above-mentioned the 1st extrinsic region in the mode of every pixel.
8. solid camera head according to claim 7 is characterized in that, above-mentioned semiconductor substrate also has: the 8th extrinsic region of the 2nd conduction type that is provided with between above-mentioned the 1st gate electrode and above-mentioned the 7th extrinsic region.
9. a solid camera head is characterized in that, comprising:
Semiconductor substrate, it comprises:
The 1st extrinsic region at the 1st conduction type of the signal charge of the opto-electronic conversion generation of the photoelectric conversion part of the skin section formation of above-mentioned semiconductor substrate is passed through in storage;
The 2nd extrinsic region of above-mentioned the 1st conduction type that in above-mentioned semiconductor substrate and at above-mentioned the 1st extrinsic region, forms below more;
The thickness direction of above-mentioned semiconductor substrate connect above-mentioned semiconductor substrate, and the signal charge that will be stored in above-mentioned the 1st extrinsic region be sent to the 1st gate electrode of above-mentioned the 2nd extrinsic region; And
Contact and arrive the spill and leakage unit of the 1st conduction type at the back side of above-mentioned semiconductor substrate with above-mentioned the 1st extrinsic region; And
At the rear side of above-mentioned semiconductor substrate signal processing part that form, that import the signal charge that transmits to above-mentioned the 2nd extrinsic region.
10. solid camera head according to claim 9 is characterized in that, above-mentioned spill and leakage unit comprises the spill and leakage layer lower than the impurity concentration of above-mentioned the 1st extrinsic region.
11. solid camera head according to claim 9 is characterized in that, above-mentioned semiconductor substrate also has: the 3rd extrinsic region of the 2nd conduction type that is provided with under above-mentioned the 1st extrinsic region.
12. solid camera head according to claim 11, it is characterized in that above-mentioned semiconductor substrate also has: the 4th extrinsic region that between above-mentioned the 2nd extrinsic region and above-mentioned the 3rd extrinsic region, is provided with, compare the 2nd higher conduction type of impurity concentration with above-mentioned the 3rd extrinsic region.
13. solid camera head according to claim 12 is characterized in that, above-mentioned semiconductor substrate also has: under above-mentioned the 4th extrinsic region, be provided with, with the 5th extrinsic region of the 2nd conduction type of above-mentioned the 2nd extrinsic region adjacency.
14. solid camera head according to claim 13 is characterized in that, above-mentioned the 5th extrinsic region arrives the rear side of above-mentioned semiconductor substrate;
Above-mentioned semiconductor substrate also has: the 6th extrinsic region of the 1st conduction type that optionally is provided with in above-mentioned the 5th extrinsic region of its rear side.
15. solid camera head according to claim 14 is characterized in that, above-mentioned signal processing part has: the 2nd gate electrode that transmits signal charge from above-mentioned the 2nd extrinsic region to above-mentioned the 6th extrinsic region.
16. solid camera head according to claim 9, it is characterized in that above-mentioned semiconductor substrate also has: the 7th extrinsic region that extends and cut apart the 2nd conduction type of above-mentioned the 1st extrinsic region in the 1st direction of the major surfaces in parallel of above-mentioned relatively semiconductor substrate in the mode of every pixel.
17. solid camera head according to claim 16 is characterized in that, above-mentioned semiconductor substrate also has: the 8th extrinsic region of the 2nd conduction type that is provided with between above-mentioned the 1st gate electrode and above-mentioned the 7th extrinsic region.
18. the manufacture method of a solid camera head is characterized in that, comprising:
Be formed for storing the operation of the 1st extrinsic region of the 1st conduction type of the signal charge that produces by opto-electronic conversion in the skin section of semiconductor substrate;
Form the operation of the groove that connects above-mentioned semiconductor substrate;
By at least one side of above-mentioned groove being imported the impurity of the 1st conduction type, in above-mentioned semiconductor substrate, form the operation of the 2nd extrinsic region of the 1st conduction type below more at above-mentioned the 1st extrinsic region;
In above-mentioned groove, insert electric conducting material across dielectric film, form the operation of gate electrode; And
Form the operation of above-mentioned signal processing part in the rear side of above-mentioned semiconductor substrate.
19. the manufacture method of solid camera head according to claim 18, it is characterized in that, also comprise: import the impurity of above-mentioned the 1st conduction type by another side, form operation with the spill and leakage unit of the 1st conduction type at above-mentioned the 1st extrinsic region back side that contact and that arrive above-mentioned semiconductor substrate to the inwall of above-mentioned groove.
20. the manufacture method of solid camera head according to claim 18 is characterized in that, optionally forms above-mentioned the 1st extrinsic region on the top layer of the 3rd extrinsic region of the 2nd conduction type.
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| CN101640214B (en) * | 2008-07-31 | 2011-08-10 | 株式会社东芝 | Solid-state imaging device and method of manufacturing the same |
| CN102629614A (en) * | 2011-02-07 | 2012-08-08 | 三星电子株式会社 | Image sensors |
| CN103178134A (en) * | 2011-12-21 | 2013-06-26 | 英飞凌科技股份有限公司 | Photo cell devices for phase-sensitive detection of light signals |
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| CN102629614A (en) * | 2011-02-07 | 2012-08-08 | 三星电子株式会社 | Image sensors |
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| CN107534048A (en) * | 2015-03-31 | 2018-01-02 | 国立大学法人静冈大学 | Survey long element and solid camera head |
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