TWI685985B - Fast settling output line circuit, fast settling method and imaging system - Google Patents

Abstract

A fast settling output line circuit, a fast settling method and an imaging system. A transfer transistor is coupled between a photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a reset floating diffusion voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator provides adjustable current to the bitline source node through a bias transistor.

Description

Fast and stable output line circuit, fast and stable method and imaging system Unify

The present disclosure generally relates to a complementary metal oxide semiconductor (CMOS) image sensor, and specifically but not exclusively relates to a photodiode pixel unit and the photodiode used in the image sensor Device and method for output line (bit line) of volume pixel unit, the image sensor can quickly stabilize bit line during readout of image signal to reduce fixed pattern noise (FPN) and maintain supply Power supply stability.

Image sensors are already ubiquitous. Image sensors are widely used in digital still cameras, mobile phones, security cameras, and medical, automotive, and other applications. Many of these applications require the use of high dynamic range (HDR) image sensors. The human eye generally has a dynamic range of up to about 100 decibels (dB). For automotive applications, image sensors with a dynamic range of more than 100dB are often required to handle different driving situations, such as when driving through a dark tunnel into bright sunlight.

The HDR image sensor does not always perform the HDR function correctly. common Disadvantages include fixed pattern noise (FPN) that causes image degradation, large random noise, reduced resolution associated with charge blooming, the presence of motion artifacts, fixed sensitivity, and When multiple photodiodes are used, the fill factor is low, where the fill factor is the ratio of the photosensitive area of the pixel to the total area of the pixel.

其中時間常數τ=RC，且V_0.5LSB是單個位元等效電壓(single bit equivalent voltage)值的一半。 When an image sensor is used, photo-generated electrons in each of the multiple pixel units are transferred from photodiodes (PD) to floating diffusion (FD) for Follow up reading. A transfer (TX) transistor coupled between PD and FD is turned on and off under the control of a voltage pulse applied to the TX gate terminal to achieve this charge transfer. Since there is always a coupling capacitance between the TX gate terminal and the FD, the pulse signal applied to the TX gate is always coupled to the FD to a large extent. This is called TX feed-through. The pulse signal fluctuates to an output line (also referred to as a bit line) of the pixel unit through a source follower (SF) transistor and a row select (RS) transistor. The propagation of such large undesired pulses is inevitable, and can even cause annoying FPN for dark signals (signals caused by non-photo-generated, intrinsic electrons inside the pixel) . For any given bit line, since the given bit line is connected to all pixels in a row, the given bit line has a significant capacitive and resistive (RC) load . Therefore, any state change on the bit line will inevitably slow down due to this RC delay. That is to say, once a state change occurs on the bit line, it takes a long time to stabilize to the step level of the renewed step (step level). This is governed by the so-called RC time constant. For any given input step size Vin, its settling time is governed by:

Among them the time constant τ=RC, and V _0.5LSB is half of the value of single bit equivalent voltage (single bit equivalent voltage).

One typical solution to this problem is to use a clamping voltage generator to clamp the bit line voltage to limit its swing. This helps to suppress high-light-banding caused by the voltage near the lower end of the voltage range. This goal is achieved by not allowing the bit line to fall below the clamping voltage limit. As a result, this will reduce FPN under high light conditions. However, this solution causes the power supply to react to each step of the voltage change and cause large current changes, which in turn can cause other undesirable performance problems on the sensor.

Another solution is to disconnect the pixel cell from the output line (bit line) of the pixel cell during charge transfer, again by means of the added clamping voltage generator. The clamp voltage generator does not allow the bit line voltage to drop below a certain voltage level. Therefore, when charge transfer occurs, the voltage change on the bit line can be reduced, and the settling time can be shortened. In addition, the clamp voltage generator keeps the total power supply (AVDD) current close to constant to avoid large changes in power supply. With this solution, after the RS transistor is turned back on again to reconnect the pixel output to the bit line, the bit line is charged by the pull-up current flowing through the SF transistor under the complete dark conditions associated with the highest voltage It will not be absorbed by the pull-down current of the relatively weak current source generator. Since the SF current is not limited by the current source generator, the settling time is also shortened. Always achieve a faster pull-up. This means that faster stabilization under low light conditions is the obvious advantage of this solution. However, the performance under strong light conditions is still a problem, because the higher contrast of light intensity will cause a larger bit line Voltage drop, this will directly lead to a longer settling time.

In addition, as the pixel size becomes smaller and the conversion gain utilized becomes higher, the FD capacitance may become too small so that the TX feedthrough may easily exceed the input voltage range of the analog-digital converter (ADC).

According to an embodiment of the present disclosure, an output line circuit, a fast stabilization method, and an imaging system are provided to quickly stabilize bit lines.

According to an embodiment of the present disclosure, a fast and stable output line circuit includes: a photodiode adapted to accumulate image charge in response to incident light; at least one transfer transistor coupled between the photodiode and floating diffusion To transfer the image charge from the photodiode to the floating diffusion, wherein a transfer gate voltage controls the transfer of the image charge from the transfer receiving terminal of the transfer transistor to the floating diffusion; A reset transistor, coupled to supply a reset floating diffusion voltage to the floating diffusion, wherein a reset gate voltage controls the reset transistor; a source follower transistor, coupled to the source follower gate The terminal receives the floating diffused voltage and provides the amplified signal to the source terminal of the source follower; the bit line enables transistors, coupled between the bit line and the source node of the bit line, where the bit A line enable voltage controls the bit line enable transistor, and wherein the bit line source node is coupled to a black solar voltage generator; and, a current source generator is coupled to the bit line source node Between ground potential, wherein the current source generator provides an adjustable current to the bit line source node through a bias piezoelectric crystal, which is controlled by a bias control voltage.

According to an embodiment of the present disclosure, a method for fast and stable output line circuit Including: reset the floating diffusion to the reset floating diffusion voltage by resetting the reset gate voltage to a high level to turn on the reset transistor; when the column select transistor and bit line enable transistor are turned off When on, pre-charge the bit line to the source reset voltage of the source follower through the bit line parasitic capacitor by setting the idle enable voltage to a high level to turn on the idle enable transistor; The energy voltage is set to a high level to turn on the black solar enable transistor and to precharge the bit line source node to the black solar voltage by supplying the black solar control voltage to the black solar transistor, and by clamping The enable voltage is set to a low level to turn off the clamp enable transistor; the parasitic capacitor to the bit line is interrupted by setting the idle enable voltage to a low level to turn off the idle enable transistor Pre-charging; by setting the column select gate voltage and bit line enable voltage to a high level to close the column select transistor and the bit line enable transistor to the source terminal of the source follower Enable the connection of the bit line with the bit line and reconnect the bit line to the source node of the bit line; by setting the reset gate voltage to a low level to disconnect the Reset the transistor to disconnect the floating diffusion from the pixel voltage; and, read the background signal from the floating diffusion, wherein the source follower transistor receives the background signal at the gate terminal of the source follower and The amplified background signal is provided at the source terminal of the source follower, and wherein the analog-to-digital converter receives the amplified background signal from the bit line to the analog-to-digital converter input terminal.

According to an embodiment of the present disclosure, an imaging system with a fast and stable output line circuit includes: a pixel array formed by pixel units, wherein each pixel unit includes: a photodiode, suitable for accumulating image charges in response to incident light; At least one transfer transistor coupled between the photodiode and floating diffusion to transfer the image charge from the photodiode to the floating diffusion, wherein the transfer gate is electrically charged Control the transfer of the image charge from the transfer receiving terminal of the transfer transistor to the floating diffusion; a reset transistor, coupled to supply a reset floating diffusion voltage to the floating diffusion, wherein the reset gate The voltage controls the reset transistor; and, the source follower transistor is coupled to receive the floating diffused voltage from the source follower gate terminal and provide the amplified signal to the source follower source terminal ; Bit line enable transistor, coupled between the bit line and the bit line source node, wherein the bit line enable voltage controls the bit line enable transistor, and wherein the bit line source A pole node is coupled to the black solar voltage generator; a current source generator is coupled between the bit line source node and ground potential, wherein the current source generator passes the bias piezoelectric crystal to the bit line source A pole node provides an adjustable current, the biased piezoelectric crystal is controlled by a bias control voltage; a control circuitry, coupled to the pixel array to control the operation of the pixel array, wherein the control circuitry directs the pixels The array provides the transfer gate voltage, the reset gate voltage, the column select gate voltage, the bit line enable voltage, the sample and hold voltage, the gate-ground voltage, the bias voltage, and the clamp control Voltage, clamping enable voltage, black sun control voltage, black sun enable voltage, idle control voltage, and idle enable voltage; readout circuitry, coupled to the pixel array through multiple readout rows, from the multiple Pixel readout image data; and, functional logic, coupled to receive image data from the readout circuitry to store the image data from each of the plurality of pixel units, wherein The functional logic provides instructions to the control circuitry.

100‧‧‧Imaging system

102‧‧‧Pixel array

104‧‧‧Control circuit system/control circuit

106‧‧‧ readout circuit system

108‧‧‧Function logic

110‧‧‧read line/read line

200‧‧‧Image sensor system/circuit system

201‧‧‧Pixel unit

202‧‧‧Photodiode (PD)/detection photodiode

203‧‧‧Transfer storage (TS) transistor

204‧‧‧Transfer (TX) transistor

205‧‧‧ Transfer storage gate (TSG) voltage

206‧‧‧Transfer (TX) gate voltage

207‧‧‧Transfer (TX) receiving terminal

208‧‧‧Floating Diffusion (FD)

210‧‧‧Reset (RST) transistor

212‧‧‧Reset (RST) gate voltage

216‧‧‧ source follower (SF) transistor

218‧‧‧Source follower (SF) source terminal/SF output/SF source potential/source terminal

220‧‧‧Column selection (RS) transistor

222‧‧‧Column selection (RS) gate voltage

224‧‧‧bit line/floating bit line

226‧‧‧bit line enable transistor

228‧‧‧Bit line enable voltage/bit line enable voltage bl_en/bit line enable signal bl_en

230‧‧‧bit line source node (BLSN)

231‧‧‧Current source (CS) generator

232‧‧‧Gate-negative ground transistor

234‧‧‧Gate-negative ground control voltage (Vcl)

236‧‧‧Gate-negative ground sample-hold (SH) transistor/gate-negative ground enable transistor

238‧‧‧Sample hold (SH) voltage/SH pulse/sample hold (SH) voltage pulse

240‧‧‧Gate-to-ground voltage/voltage Vcasc/Vcasc

242‧‧‧bias piezoelectric crystal

244‧‧‧bias control voltage (Vbl)

246‧‧‧ Bias sample-and-hold (SH) transistor/bias enabled transistor

248‧‧‧bias voltage/voltage (Vbias)

250‧‧‧Gate-overground (CH) capacitor/capacitor

252‧‧‧BH capacitor

254‧‧‧ Analog ground potential (AGND)

255‧‧‧Clamp voltage (CV) generator

256‧‧‧Clamp Transistor/Clamp Voltage Transistor

258‧‧‧Clamp control voltage

260‧‧‧Adjustable clamping voltage

262‧‧‧Clamp enable transistor

264‧‧‧Clamp enable voltage (clamp_en)

265‧‧‧Black sun voltage generator

266‧‧‧Black Sun Power Supply Transistor

268‧‧‧ Black Sun power supply voltage

270‧‧‧Black Solar Transistor

272‧‧‧Black Sun control voltage

274‧‧‧Adjustable black solar voltage/black solar voltage

276‧‧‧Black Sun Enable Transistor

278‧‧‧Black Sun Enable Voltage (bsun_en)

279‧‧‧ Idle voltage (IV) generator

280‧‧‧Idle power supply transistor

282‧‧‧Idle power supply voltage

284‧‧‧Idle enable transistor

286‧‧‧Idle enable voltage (idle_en)

288‧‧‧bit line parasitic capacitor (Cp)

290‧‧‧Transmission gate

292‧‧‧Analog-to-digital converter input terminal

300‧‧‧Signal readout operation

302‧‧‧point/time

310, 320, 330, 340, 350, 360 ‧‧‧ time zone

400‧‧‧Flowchart

402, 460‧‧‧ process block

410, 420, 430, 440, 450 ‧‧‧ process block/block

C1, C2, C3, C4, C5~Cx‧‧‧ line

R1, R2, R3, R4, R5~Ry‧‧‧Column

A non-limiting and non-exhaustive example of the present invention is explained with reference to the following figures, where the same reference numbers are used in all views unless otherwise specified Refers to the same parts.

FIG. 1 shows an example of an imaging system according to an embodiment of the present disclosure.

FIG. 2 is an exemplary schematic diagram of a block diagram of a pixel unit and a pixel output circuit in an imaging sensor according to an embodiment of the present disclosure. The imaging sensor can quickly stabilize its bit lines.

FIG. 3 is an exemplary waveform associated with an operation performed by a photodiode in an imaging sensor to achieve bit line stability according to an embodiment of the present disclosure.

4 is an illustrative flowchart associated with the event shown in FIG. 3 according to an embodiment of the disclosure.

In all several views of the drawing, corresponding reference characters represent corresponding elements. Those skilled in the art should understand that the elements in the figures are shown for brevity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. In addition, common but well-known elements that are usable or necessary in commercially feasible embodiments are often not shown so as not to hinder the view of these various embodiments of the present invention.

This article describes embodiments of an apparatus and method for quickly stabilizing pixel output lines in an imaging sensor. In the following description, many specific details are stated to provide a thorough understanding of the embodiments. However, those skilled in the relevant art should recognize that the technology described herein may not use one or more of these specific details Can be practiced under other conditions or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Therefore, the phrases "in one instance" or "in one embodiment" appearing throughout this specification do not necessarily refer to the same instance. In addition, in one or more examples, the specific features, structures, or characteristics may be combined in any suitable manner.

Throughout this manual, several technical terms are used. Unless specifically defined herein or clearly indicated in the context in which these terms are used, these terms adopt their usual meanings in the art.

FIG. 1 shows an example of an imaging system 100 according to an embodiment of the present disclosure. The imaging system 100 includes a pixel array 102, control circuitry 104, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) photodiode array, or image sensor pixels (eg, pixels P1, P2, ..., Pn). As shown in the figure, the photodiodes are arranged in columns (eg, columns R1 to Ry) and rows (eg, rows C1 to Cx) to obtain image data of people, places, objects, etc., the image data It can then be used to present two-dimensional images of people, places, objects, etc. However, the photodiodes do not have to be arranged in columns and rows, but other configurations can also be used.

In one example, after each image sensor photodiode/pixel in the pixel array 102 obtains its image charge through photo-generated image charge, the corresponding image data is read out by the readout circuitry 106 , And then the corresponding image data Transfer to function logic 108. The readout circuitry 106 can be coupled to readout image data from the plurality of photodiodes in the pixel array 102. In various examples, the readout circuitry 106 may include amplification circuitry, analog-to-digital conversion (ADC) circuitry, or other circuitry. In one example, the readout circuitry 106 may read out one column of image data at a time along the readout row line 110 (shown in the figure), or various other techniques (not shown) may be used (eg, serial readout or All pixels are read out in parallel at the same time) to read out the image data. The function logic 108 may store image data or even manipulate image data by applying post-image effects (eg, cropping, rotating, red-eye reduction, adjusting brightness, adjusting contrast, or other post-image effects).

In some embodiments, the functional logic 108 may require certain imaging conditions to be met, and thus may instruct the control circuitry 104 to manipulate certain parameters in the pixel array 102 to achieve better quality or special effects.

FIG. 2 is an example of a block diagram of a pixel unit and a pixel output circuit in an imaging sensor according to an embodiment of the present disclosure. The image sensor can quickly stabilize its output line (bit line 224). The illustrated embodiment of the image sensor system 200 may include a detection photodiode (PD) 202 in a typical 4 transistor (4T) pixel unit 201, where the 4T portion may include transfer (TX) power A crystal 204, a reset (RST) transistor 210, a source follower (SF) transistor 216, and a column selection (RS) transistor 220. In one embodiment, the RS transistor 220 is connected between the source terminal of the SF transistor 216 and the bit line 224, and the drain terminal of the SF transistor 216 is directly connected to the pixel voltage (VPIX), as shown in FIG. 2 shows. In another embodiment, the RS transistor 220 is connected between the drain terminal of the SF transistor 216 and VPIX. VPIX can be connected to the power supply voltage AVDD, or can be connected to a regulated voltage supply source, where the regulated voltage supply source It is adjusted based on the power supply from AVDD. The node where the drain of the TX transistor 204, the source of the RST transistor 210, and the gate of the SF transistor 216 intersect is a floating diffusion (FD) 208. The reset (RST) gate voltage 212 and the RS gate voltage 222 controlled by the control circuitry 104 (see FIG. 1) can turn on the RST transistor 210 and the RS transistor 220, respectively.

The transfer (TX) gate voltage 206 enables the TX transistor 204. When a high connection voltage is applied to the TX gate voltage 206, the TX transistor 204 can be turned on. In this case, in one embodiment, the photodiode (PD) 202 is directly connected to the TX transistor 204 TX receiving terminal 207, the photo-generated signal charge accumulated at PD 202 can be transferred to FD 208 through TX transistor 204. In another embodiment, the stored charge transferred from the PD 202 by the transfer storage (TS) transistor 203 existing at the TX receiving terminal 207 of the TX transistor 204 may be transferred to the FD 208 through the TX transistor 204 . When a sufficiently low off voltage is applied to the TX gate voltage 206, the TX transistor 204 can be turned off. The transfer storage gate (TSG) voltage 205 controls the transfer storage (TS) transistor 203.

When the RS transistor 220 is turned on when the RS gate voltage 222 is set to a high level, the amplified image signal from the source terminal of the SF transistor 216 is delivered to the bit line 224. The analog image signal on the bit line 224 is finally provided to the input terminal of the ADC. In one embodiment, when the corresponding transmission gate 290 is enabled, this ADC is one ADC of the plurality of ADCs coupled to each bit line or readout row 110 shown in FIG. 1.

The bit line enable transistor 226 is connected between the bit line 224 and the bit line source node (BLSN) 230. When the bit line enable voltage bl_en 228 is set to a high level, the bit line enable transistor 226 is turned on, and The bit line 224 is connected to its current source (CS) generator 231 through the BLSN 230.

The CS generator 231 is connected between the BLSN 230 and the analog ground (AGND). In an embodiment, the CS generator 231 provides an adjustable current to the BLSN 230 through the biased crystal 242. The bias piezoelectric crystal 242 is controlled by the bias control voltage Vbl 244. The proper operation of the bias piezoelectric crystal 242 in the CS generator 231 requires an appropriate bias control voltage Vbl 244. Vbl 244 is constrained by voltage Vbias 248. In another embodiment, the CS generator 231 (gate-to-ground transistor 232, gate-to-ground enable transistor 236, bias enable transistor 246, CH capacitor 250, and BH capacitor 252 all exist) The BLSN 230 is supplied with adjustable current through the following two transistors connected in series: gate-to-ground transistor 232 and bias piezoelectric crystal 242. The gate-negative ground transistor 232 is controlled by the gate-negative ground control voltage Vcl 234. The bias piezoelectric crystal 242 is controlled by the bias control voltage Vbl 244.

The normal operation of the CS generator 231 requires an appropriate gate-to-negative control voltage Vcl 234, and when the sample and hold (SH) voltage 238 is set to a high level to close the gate-to-negative enable transistor At 236, the gate-negative ground control voltage Vcl 234 is limited by the voltage Vcasc 240. When the SH voltage 238 is at a high level, the cascode hold (CH) capacitor 250 is charged to Vcasc 240. The CH capacitor 250 keeps the value of Vcasc 240 unchanged until the next SH pulse 238 comes, at which time the value of Vcl 234 on the CH capacitor 250 is refreshed to the exact value of Vcasc 240 again. Since the CH capacitor 250 is coupled between the gate-ground control voltage Vcl 234 and the analog ground potential AGND 254, Vcl 234 discharges slowly and the value of Vcl 234 drops slightly before the subsequent SH pulse 238 arrives. Both Vcasc 240 and SH pulse 238 are controlled by control circuit 104.

The proper operation of the CS generator 231 also requires an appropriate bias control voltage 244, and when the SH voltage 238 is set to a high level to close the bias enable transistor 246, the bias control voltage 244 is restricted by the voltage Vbias 248. When the SH voltage 238 is at a high level, the bias hold (BH) capacitor 252 is charged to Vbias 248. The BH capacitor 252 keeps the value of Vbias 248 unchanged until the next SH pulse 238 arrives, at which time the value Vbl 244 on the BH capacitor 252 is refreshed to the exact value of Vbias 248 again. Since the bias BH capacitor 252 is coupled between the bias control voltage Vbl 244 and AGND 254, Vbl 244 discharges slowly and the value of Vbl 244 drops slightly before the subsequent SH pulse 238 arrives. Vbias 248 is controlled by control circuit 104.

Regardless of whether the bit line 224 is connected to or disconnected from the BLSN 230 through the bit line enable (BE) transistor 226, the CS generator 231 is always directly connected to the BLSN 230 through the following two voltage sources: clamp A clamp voltage (CV) generator 255 and a blacksun voltage (BV) generator 265. The CS generator 231 may be driven by one of the two voltage generators in one embodiment, or simultaneously driven by the two voltage generators in another embodiment.

The clamping voltage (CV) generator 255 includes a clamping voltage transistor 256 and a clamping enable transistor 262. The clamping voltage transistor 256 receives the VPIX and provides an adjustable clamping voltage 260 under the control of the clamping control voltage 258. The clamp enable transistor 262 delivers the adjustable clamp voltage 260 to the CS generator 231 on the BLSN 230 under the control of the clamp enable voltage 264.

The black solar voltage (BV) generator 265 includes a black solar power supply transistor 266, a black solar transistor 270, and a black solar enable transistor 276. Black Sun Power The supply transistor 266 provides the black sun power supply voltage 268. Due to the voltage drop between the drain terminal and the source terminal of the black sun power supply transistor 266, the black sun power supply voltage 268 is guaranteed to be lower than VPIX. The black solar transistor 270 receives the black solar power supply voltage 268 and provides an adjustable black solar voltage 274 under the control of the black solar control voltage 272. The black solar enable transistor 276 delivers the adjustable black sun voltage 274 to the current source generator 231 on the BLSN 230 under the control of the black sun enable voltage 278.

Adjustable black solar voltage 274 provides a much higher potential on BLSN 230 than adjustable clamp voltage 260 provides on BLSN 230. If VPIX (the highest potential of the pixel circuit) represents the darkest image boundary (ADC considers it as the upper limit of the conversion range), and any normal background signal is slightly lower than VPIX, then the adjustable black solar voltage 274 is set below The lowest voltage of those background signals. The black solar voltage still represents dark images and is only slightly darker than those background signals. The purpose of the black solar voltage generator 265 is explained in the following paragraph.

The black sun voltage is used to avoid the so-called sun eclipse effect (or black sun effect). That is, when the image sensor directly faces the sunlight, the background at FD 208 is presumed to be "dark" filled with a large number of electrons, which are directly generated on the FD (because the FD itself is a photosensitive substance ) Or from the silicone surrounding the FD unstoppably smudged. Therefore, this background noise signal, which is supposed to be "dark", is saved as an actual bright signal. After the ADC saves the real bright (plus noise) signal based on the correlated double sampling (CDS) method, the subtraction of these two saved nearly equal "bright" signals will result in a near "zero" final Signal, the final signal close to "zero" is equivalent to a black image at a location where the bright sun should be present. It can be seen that if As it is, due to the above subtraction, the bright sun will become a black sun-hence the name "black sun". To overcome the black sun effect, when a known background signal (black or near black) is used during the CDS process, the black sun voltage 274 forces the black level to be used. Therefore, the sun in the image will no longer be black.

The control circuitry 104 controls the black sun control voltage 272 based on the feedback regarding the level where the normal background signal exists. Once the functional logic 108 determines the lowest equivalent voltage (of many normal background signals), the value is fed to the control circuitry 104. And then, the updated black sun control voltage 272 is fed to the BV generator 265 to ensure that the background signal will be sufficiently "black" for the CDS process.

Compared with the adjustable black solar voltage 274, the adjustable clamping voltage 260 sets a minimum limit voltage. The minimum limit voltage represents the brightest image boundary (ADC regards it as the lower end of the conversion range).

The control circuit 104 provides all four control signals: the clamp control voltage 258, the clamp enable voltage 264, the black sun control voltage 272, and the black sun enable voltage 278 to control the CV generator 255 and the BV generator 265.

An idle voltage (IV) generator 279 serves as a current source for the bit line 224. When the bit line 224 is disconnected from its power supply circuit, the IV generator 279 is required to maintain an idle potential relative to the bit line 224. In one embodiment, when both the RS transistor 220 and the bit line enable transistor 226 are simultaneously disabled, the IV generator 279 becomes the only power source to pass through its bit line parasitic capacitor Cp 288 The floating bit line 224 is charged. When the gate of the SF transistor 216 is set to the reset FD voltage (VRFD) by the RST transistor 210, the idle potential is maintained at the closest contact with the potential of the SF source terminal 218 Near value. VRFD is a dedicated voltage for resetting the floating diffusion controlled by the control circuit system 104. VRFD may or may not have the same voltage as VPIX. When the RS transistor 220 is turned on again, the potential at the bit line 224 has been precharged to a similar level of the SF source terminal 218; therefore, the settling time of the bit line 224 and the SF transistor 216 is greatly shortened. This is because when the bit line 224 is reconnected to the SF transistor 216, the voltage difference between the bit line 224 and the SF output 218 is greatly reduced. In one embodiment, the IV generator 279 includes an idle power supply transistor 280 and an idle enable transistor 284 for driving the bit line 224. The idle power supply transistor 280 receives the VPIX and provides an idle control voltage (VIDLE) Controlled idle power supply voltage 282. The idle enable voltage 286 and VIDLE are controlled by the control circuitry 104.

3 is an exemplary signal readout operation 300 of a pixel unit and an output circuit of a pixel unit in an imaging sensor according to an embodiment of the present disclosure, the imaging sensor can make its output line (bit line 224) fast stable. In order to better understand FIG. 3 and the sequence shown in FIG. 3, a timing flow chart is provided in FIG. 4 to explain all the main events occurring in FIG. 3 in conjunction with FIG.

FIG. 4 is an exemplary flowchart 400 according to an embodiment of the present disclosure. Flowchart 400 may show the complete column readout loop and show how the disclosed circuitry 200 can be used to achieve rapid stabilization of the bit line 224 in a typical data readout loop.

The flowchart 400 begins at process block 402 and then proceeds to process block 410. Process block 402 (associated with time point 302 in FIG. 3) marks the start of the readout loop, at which time the readout circuitry 106 reads out a new column of multiple pixel cells. Process block 410 is related to the time zone 310 shown in FIG. 3. The process block 410 coincides with the horizontal blank (H-blank) of each column of the pixel array 102. H-blank in the new readout loop Before clearing each read row 110 in the entire concurrent row (concurrent row). In terms of circuit conditions, during block 410, the RST transistor 210 is turned on by the RST gate voltage 212 to reset the FD 208 to VRFD. At the same time, both the RS transistor 220 and the bit line enable transistor 226 are simultaneously turned off by the RS gate voltage 222 and the bit line enable voltage (bl_en) 228. In the embodiment where the RS transistor 220 is connected between the SF transistor 216 and the bit line 224, these disconnections isolate the bit line 224 from the rest of the drive circuitry except the IV generator 279.

During the process block 410 that coincides with the subsequent H-blank, the three main precharge activities are in effect simultaneously. First of all, for the current source (CS) generator 231, if there are all gate-negative transistors 232, gate-negative enable transistors 236, and bias enable transistors 246 in one embodiment, With the CH capacitor 250 and the BH capacitor 252, the sample-and-hold (SH) voltage pulse 238 enables both the gate-to-negative enable transistor 236 and the bias enable transistor 246. The CH capacitor 250 is charged to Vcasc 240, and the BH capacitor 252 is charged to Vbias 248. In block 410, when the SH pulse is turned on, the gate-to-negative transistor 232 is correctly driven by Vcl 234, and Vcl 234 is directly driven by Vcasc 240; and the bias piezoelectric crystal 242 is correctly driven by Vbl 244 In ground operation, Vbl 244 is driven directly by Vbias 248 in one embodiment or by Vbias 248 through a bias-enabled transistor 246 in another embodiment. Outside the block 410, when the SH pulse is turned off, the CH capacitor 250 and the BH capacitor 252 correctly maintain the normal operation of the CS generator 231 between the SH pulses, because it is used to drive the gate- cathode transistor 232 and the bias Both the bias values Vcl and Vbl of the piezoelectric crystal 242 are correctly held by these two capacitors.

Second, the clamp voltage (CV) generator 255 is disabled by setting the clamp enable voltage clamp_en 264 to a low level. And by enabling the black sun to enable voltage bsun_en 278 is set to a high level to enable the black sun voltage (BV) generator 265. During this current process block 410, the BV generator 265 charges the BLSN 230 through the CS generator 231.

Third, the idle voltage (IV) generator 279 is enabled by setting the idle enable voltage idle_en 286 to a high level. The IV generator 279 charges the isolated bit line 224 to an idle potential through the bit line parasitic capacitor Cp 288, which closely matches the high voltage value appearing on the SF source potential 218, because the SF gate or The FD 208 is set to VRFD by the RST transistor 210 during this same period.

The IV generator 279 pulls up the voltage of the bit line 224 to its expected high reset level by using only the full current capacity through the bit line parasitic capacitor Cp 288. This shortens the reset stabilization time of each column, thus shortening the H-blank time. The direct result is a shorter readout time for each column and a shorter overall frame time. Switching the charging load from the CV generator 255 to the IV generator 279 at time 302 helps to maintain a stable consumption of the supply power at AVDD, because the bit line 224 as the load circuit is generated by the CV generator 255 or IV The generator 279 is continuously charged.

After process block 410, process block 420 may proceed. Process block 420 is related to time zone 320 shown in FIG. 3. During block 420, both the SH voltage 238 and the idle enable voltage idle_en 286 are set from a high level to a low level. The gate-negative enable transistor 236, the bias enable transistor 246, and the idle enable transistor 284 are switched from on to off. The duration of the time zone 320 only needs to be long enough for the first switching operation performed by the SH voltage 238 together with the idle enable voltage idle_en 286 and the first switching operation performed by the RS gate voltage 222 and the bit line enable voltage bl_en 228 Two open The area between the closing actions is buffered to avoid any competition between the first switching action and the second switching action. And to allow enough time, in one embodiment a few nanoseconds are used to stabilize the bit line 224.

After process block 420, process block 430 may proceed. Process block 430 is related to time zone 330 shown in FIG. 3. During block 430, the RST gate voltage 212 is maintained at a high level to keep the RST transistor 210 on. The FD 208 is continuously reset to VRFD. After the RS transistor 220 and the bit line enable transistor 226 are both turned on, the bit line 224 is reconnected to the SF transistor 216 on one side and to the BLSN 230 on the other side, Block 430 allows sufficient time for the bit line 224 to stabilize.

After process block 430, process block 440 may proceed. Process block 440 is related to time zone 340 shown in FIG. 3. During block 440, the RST transistor 210 is turned off. The SF transistor 216 amplifies the background signal on the FD 208, and then the amplified background signal is provided to the bit line 224 through the RS transistor 220 in one embodiment, or from the source of the SF transistor 216 in another embodiment The terminal 218 is directly provided to the bit line 224. During this time period, the black sun enable voltage 278 only enables the BV generator 265 of all three voltage generators. The black sun voltage 274 drives both the BLSN 230 and the bit line 224 at the same time, because the bit line enable voltage bl_en 228 still closes the bit line enable transistor 226. The adjustable black sun voltage from the BV generator 265 can provide a potential generally set on the high level side, which is only slightly lower than the normal background signal. If VPIX represents the darkest image signal, the not too low black solar voltage sets a sufficiently dark image signal (if not the darkest). From the ADC's perspective, if VPIX represents the lowest value of the ADC output, the black sun voltage ensures a very low value at the ADC output, which is not too high above the ADC within its range The lowest value converted.

After process block 440, process block 450 may proceed. Process block 450 is related to time zone 350 shown in FIG. During block 450, in one embodiment, when the transfer transistor 204 is turned on by the TX gate voltage 206, the photo-generated signal charge accumulated on the PD 202 is transferred to the FD 208. In another embodiment, the stored charge transferred from the PD 202 by the transfer storage (TS) transistor 203 at the TX receiving terminal 207 is transferred to the FD 208. Both the RS transistor 220 and the bit line enable transistor 226 are turned off before charge transfer and turned on again after charge transfer. This is to ensure that no overlap occurs between the high level of the TX gate voltage 206 and the high level of the RS gate voltage 222 and the high level of the bit line enable signal bl_en 228. It should also be noted that the idle enable transistor 284 remains off, and in the present disclosure when the transfer transistor 204 toggles between on and off during this current process block 450, the bit line 224 stays In a fully floating state.

The voltage variation of the bit line 224 caused by the two-state thixotropic transfer gate voltage 206 is greatly reduced compared to the same situation when the bit line 224 is not floating. The bit line 224 can maintain its original voltage level almost the same as the value before the pulse was added to the TX gate voltage 206. In one example, by comparison, the voltage step size on bit line 224 may be more than 10 times smaller. Since the bit line 224 is in a floating state during the charge transfer caused by the TX gate voltage 206, FPN is greatly reduced. Although the bit line 224 is disconnected from the BV generator 265 during the charge transfer, the BV generator 265 still charges the BLSN 230 to AGND through the current source generator 231. The total AVDD current shows a small change throughout this block 450. The system power supply therefore remains stable as needed.

After process block 450, process block 460 may proceed. Process block 460 and diagram 3 is related to the time zone 360 shown. During block 460, in general, the image charge transferred from the TX receive terminal 207 to the FD 208 is amplified by the SF transistor 216, and then is provided to the bit line 224 through the RS transistor 220 in one embodiment, or in another In one embodiment, the source terminal 218 of the SF transistor 216 is provided directly to the bit line 224. Specifically, immediately after the end of the pulse on the TX gate voltage 206 in block 450, the RS gate voltage 222 is set to a high level to allow the image signal voltage on the SF source terminal to drive the bit line 224 Reconnect RS transistor 220, and enable bit line enable transistor 226 by setting bit line enable voltage bl_en 228 to a high level to allow BLSN 230 to clamp the voltage on bit line 224 Reconnect.

During block 460, on the BLSN 230 side, the function of the BV generator 265 is taken over by the CV generator 255. This switching is effected by simultaneously setting the black sun enable voltage 278 to a low level and the clamp enable voltage 264 to a high level. Since the adjustable clamping voltage is set to be much lower than the black sun voltage, at the beginning of block 460, the voltage on the BLSN 230 begins to move down from the high black sun voltage. Meanwhile, on the SF source terminal side, if the image signal is dark (which is represented by a high voltage), the effective input step voltage on the bit line 224 is at the switching point of the RS transistor from off to on The location is close to 0. The bit line 224 is quickly stabilized based on a small effective input step voltage. If the image signal is bright, the effective input step voltage on bit line 224 is also minimized to facilitate rapid stabilization of bit line 224, because the initial voltage on both sides of bit line 224 At the same time drift down.

The adjustable clamping voltage of the CV generator 255 can provide a slightly higher potential than the level representing the absolute brightest light. The clamping voltage sets a limit on the lowest boundary, which is equivalent to the signal that looks brightest in the ADC. Although the clamping voltage Not the brightest but it is close enough to the brightest so that the ADC can accept the clamp voltage as an input and convert it to use as the highest value at the output of the ADC without overflowing the ADC. The clamping voltage ensures the lower voltage limit that the ADC can handle. Once the CV generator 255 takes over the function of the BV generator 265, the CV generator 255 is also used to minimize changes in power consumption and continuously maintain the stability of the total AVDD current.

The above description of the illustrated examples of the invention (including the above description set forth in the abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the present invention are set forth herein for illustrative purposes, as those skilled in the relevant art will recognize, various modifications may exist within the scope of the present invention.

These modifications can be made to the present invention based on the above detailed description. The terms used in the above claims should not be construed as limiting the invention to the specific examples disclosed in the specification. Rather, the scope of the present invention should be completely determined by the above claims, which should be understood in accordance with the principles for the interpretation of the claims.

200‧‧‧Image sensor system/circuit system

201‧‧‧Pixel unit

202‧‧‧Photodiode (PD)/detection photodiode

203‧‧‧Transfer storage (TS) transistor

204‧‧‧Transfer (TX) transistor

205‧‧‧ Transfer storage gate (TSG) voltage

206‧‧‧Transfer (TX) gate voltage

207‧‧‧Transfer (TX) receiving terminal

208‧‧‧Floating Diffusion (FD)

210‧‧‧Reset (RST) transistor

212‧‧‧Reset (RST) gate voltage

216‧‧‧ source follower (SF) transistor

218‧‧‧Source follower (SF) source terminal/SF output/SF source potential/source terminal

220‧‧‧Column selection (RS) transistor

222‧‧‧Column selection (RS) gate voltage

224‧‧‧bit line/floating bit line

226‧‧‧bit line enable transistor

228‧‧‧Bit line enable voltage/bit line enable voltage bl_en/bit line enable signal bl_en

230‧‧‧bit line source node (BLSN)

231‧‧‧Current source (CS) generator

232‧‧‧Gate-negative ground transistor

234‧‧‧Gate-negative ground control voltage (Vcl)

236‧‧‧Gate-negative ground sample-hold (SH) transistor/gate-negative ground enable transistor

238‧‧‧Sample hold (SH) voltage/SH pulse/sample hold (SH) voltage pulse

240‧‧‧Gate-to-ground voltage/voltage Vcasc/Vcasc

242‧‧‧bias piezoelectric crystal

244‧‧‧bias control voltage (Vbl)

246‧‧‧ Bias sample-and-hold (SH) transistor/bias enabled transistor

248‧‧‧bias voltage/voltage (Vbias)

250‧‧‧Gate-overground (CH) capacitor/capacitor

252‧‧‧BH capacitor

254‧‧‧ Analog ground potential (AGND)

255‧‧‧Clamp voltage (CV) generator

256‧‧‧Clamp Transistor/Clamp Voltage Transistor

258‧‧‧Clamp control voltage

260‧‧‧Adjustable clamping voltage

262‧‧‧Clamp enable transistor

264‧‧‧Clamp enable voltage (clamp_en)

265‧‧‧Black sun voltage generator

266‧‧‧Black Sun Power Supply Transistor

268‧‧‧ Black Sun power supply voltage

270‧‧‧Black Solar Transistor

272‧‧‧Black Sun control voltage

274‧‧‧Adjustable black solar voltage/black solar voltage

276‧‧‧Black Sun Enable Transistor

278‧‧‧Black Sun Enable Voltage (bsun_en)

279‧‧‧ Idle voltage (IV) generator

280‧‧‧Idle power supply transistor

282‧‧‧Idle power supply voltage

284‧‧‧Idle enable transistor

286‧‧‧Idle enable voltage (idle_en)

288‧‧‧bit line parasitic capacitor (Cp)

290‧‧‧Transmission gate

292‧‧‧Analog-to-digital converter input terminal

Claims (47)

A fast and stable output line circuit, including: a photodiode suitable for accumulating image charges in response to incident light; at least one transfer transistor coupled between the photodiode and floating diffusion to connect the graph Image charge is transferred from the photodiode to the floating diffusion, wherein the transfer gate voltage controls the transfer of the image charge from the transfer receiving terminal of the transfer transistor to the floating diffusion; reset the transistor, Is coupled to supply a reset floating diffusion voltage to the floating diffusion, wherein a reset gate voltage controls the reset transistor; a source follower transistor is coupled to receive the source follower gate terminal Floating the diffused voltage and providing the amplified signal to the source terminal of the source follower; bit line enable transistor, coupled between the bit line and the source node of the bit line, where the bit line enables voltage control The bit line enable transistor, and wherein the bit line source node is coupled to a black solar voltage generator; and the current source generator is coupled between the bit line source node and ground potential, Wherein the current source generator provides an adjustable current to the source node of the bit line through a bias piezoelectric crystal, and the bias piezoelectric crystal is controlled by a bias control voltage. The fast and stable output line circuit as described in item 1 of the patent application scope further includes a transfer storage transistor, which is coupled between the photodiode and the transfer transistor to connect the photoelectric The image charge accumulated in the diode is transferred to the transfer receiving terminal of the transfer transistor, and a transfer storage gate voltage controls the transfer storage transistor. The fast stable output line circuit as described in item 1 of the patent application scope further includes a column selection transistor coupled between the source terminal of the source follower and the bit line, wherein The column selection gate voltage controls the column selection transistor, and wherein the column selection transistor passes the amplified signal from the source follower source terminal to the bit line. The fast stable output line circuit as described in item 1 of the patent application scope further includes a column selection transistor coupled between the source follower drain terminal and the pixel voltage, wherein the column selection gate voltage Controlling the column selection transistor, wherein the column selection transistor passes the pixel voltage to the source follower drain terminal, and wherein the source follower source terminal is connected to the bit line . The fast stable output line circuit as described in item 4 of the patent application range, wherein the pixel voltage is connected to a power supply voltage. The fast stable output line circuit as described in item 4 of the patent application range, wherein the pixel voltage is connected to a regulated voltage supply source, wherein the regulated voltage supply source is regulated based on the power supply voltage. The fast stable output line circuit as described in item 4 of the patent application range, wherein the pixel voltage and the reset floating diffusion voltage have the same value. The fast stable output line circuit as described in item 4 of the patent application range, wherein the pixel voltage and the reset floating diffusion voltage have different values. The fast stable output line circuit as described in item 1 of the patent application range, wherein the black solar voltage generator is configured to receive the pixel voltage and The source node of the line provides an adjustable black solar voltage, and wherein the black solar voltage generator includes: a black solar power supply transistor, receives the pixel voltage and provides a black solar power supply voltage; the black solar transistor, is Coupled to receive the black sun power supply voltage and provide an adjustable black sun voltage controlled by the black sun control voltage; and a black sun enable transistor, coupled to be controlled by the black sun enable voltage to control the adjustable The black solar voltage is transferred to the source node of the bit line. The fast stable output line circuit as described in item 9 of the patent application scope further includes a clamp voltage generator configured to be connected to the bit line source node. The fast stable output line circuit as described in item 10 of the patent application range, wherein the clamp voltage generator is configured to receive the pixel voltage and provide an adjustable clamp voltage to the bit line source node, And wherein the clamp voltage generator includes: a clamp transistor configured to receive the pixel voltage and provide an adjustable clamp voltage controlled by the clamp control voltage; and a clamp enable transistor, which is coupled It is controlled by the clamping enable voltage to transfer the adjustable clamping voltage to the source node of the bit line. The fast stable output line circuit as described in item 11 of the patent application range, wherein the adjustable clamping voltage is lower than the adjustable black sun voltage. The fast stable output line circuit as described in item 1 of the patent application range, wherein the bias voltage provides the bias control voltage. The fast and stable output line circuit as described in item 1 of the patent application range, wherein the current source generator further includes a gate-negative ground coupled between the bit line source node and the bias piezoelectric crystal Transistor, the gate-negative transistor is controlled by the gate-negative control voltage. The fast stable output line circuit as described in item 14 of the patent application range, wherein the gate-ground voltage provides the gate-ground control voltage. The fast stable output line circuit as described in item 14 of the patent application range, wherein the current source generator further includes: a gate-negative sample-and-hold transistor, which is coupled to receive the gate-negative ground voltage and provide the sampled The gate-yin control voltage controlled by the hold voltage; the bias sample-and-hold transistor, coupled to receive the bias voltage and provide the bias control voltage controlled by the sample-and-hold voltage; the gate-yin ground A holding capacitor is coupled between the gate-ground control voltage and the ground potential; and a bias holding capacitor is coupled between the bias control voltage and the ground potential. The fast stable output line circuit as described in item 1 of the patent application scope further includes an idle voltage generator configured to receive a pixel voltage and provide an idle voltage to the bit line, wherein the idle The voltage generator includes: an idle power supply transistor configured to receive the pixel voltage and provide an idle power supply voltage controlled by the idle control voltage; and an idle enable transistor coupled to be controlled by the idle enable voltage The idle power supply voltage is transferred to the bit line. The fast and stable output line circuit as described in item 1 of the patent application scope further includes a transmission gate that transfers the amplified signal from the bit line to the input of the analog-to-digital converter. A method for quickly stabilizing the output line circuit, including: resetting the floating diffusion to the reset floating diffusion voltage by resetting the reset gate voltage to a high level to turn on the reset transistor; selecting the transistor in the current column When the bit line enable transistor is turned off, the bit line is precharged to the source follower source through the bit line parasitic capacitor by setting the idle enable voltage to a high level to turn on the idle enable transistor Pole reset voltage; by setting the black sun enable voltage to a high level to turn on the black sun enable transistor and by pre-charging the bit line source node to by supplying the black sun control voltage to the black sun transistor Black solar voltage, and turn off the clamp enable transistor by setting the clamp enable voltage to a low level; turn off the idle enable transistor by setting the idle enable voltage to a low level To interrupt the precharge of the bit line parasitic capacitor; by setting the column select gate voltage and the bit line enable voltage to a high level to enable the column select transistor and the bit line enable power The crystal is closed to enable the connection of the source terminal of the source follower to the bit line and reconnect the bit line to the source node of the bit line; by resetting the gate voltage Set to a low level to turn off the reset transistor to disconnect the floating diffusion from the pixel voltage; and read the background signal from the floating diffusion, where the source follower transistor is in the source follower gate Receiving the background signal at the terminal and at the source terminal of the source follower The amplified background signal is provided at, and wherein the analog-to-digital converter receives the amplified background signal from the bit line to the analog-to-digital converter input terminal. The method of claim 19, wherein when the column selection gate voltage closes the column selection transistor, the column selection transistor transmits the amplified background signal to the bit line. The method of claim 19, wherein the amplified background signal flows to the bit line. The method described in Item 19 of the patent application scope further includes: setting the sample-and-hold voltage to a high level to turn on the gate-negative sample-and-hold transistor and the bias voltage sample-and-hold transistor to switch the gate-and-negative ground The holding capacitor is precharged to the gate-to-ground voltage and the bias holding capacitor is precharged to the bias voltage; and when the idle enable transistor is turned off, the sampling and holding voltage is set to a low level to turn off The gate-yin ground sample-and-hold transistor and the bias voltage sample-and-hold transistor interrupt the pre-charging of the gate-yin ground holding capacitor and the bias-holding capacitor. The method as described in item 19 of the patent application scope further includes: enabling the column to select the transistor and the bit by setting the column selection gate voltage and the bit line enable to a low level After the element-line enabling transistor is opened, the transfer transistor is turned on and off by the two-state thixotropy of the transfer gate voltage to transfer the accumulated image charge from the transfer receiving terminal of the transfer transistor to the transfer transistor Floating diffusion. The method as described in item 23 of the patent application scope, wherein after the transfer transistor is turned off by setting the transfer gate voltage to a low level, by The column select gate voltage and the bit line enable are set to a high level to close the column select transistor and the bit line enable transistor, and by enabling the black sun Set to a low level to turn off the black sun enabled transistor, and turn on the clamp enabled transistor by setting the clamp enable to a high level. The method according to item 24 of the patent application scope, wherein the source follower transistor amplifies the image charge from the transfer receiving terminal of the transfer transistor at the source terminal of the source follower Into an amplified image signal, and wherein the analog-to-digital converter receives the amplified image signal from the bit line to the analog-to-digital converter input terminal. The method of claim 25, wherein when the column selection gate voltage closes the column selection transistor, the column selection transistor transmits the amplified image signal to the bit Yuan line. The method according to item 25 of the patent application scope, wherein the amplified image signal flows to the bit line. The method according to item 19 of the patent application scope, wherein by enabling a transmission gate, the transmission gate transmits the amplified image signal from the bit line to the analog-to-digital converter input terminal. The method of claim 19, wherein the voltage provided by the black sun-enabled transistor is higher than the voltage provided by the clamp-enabled transistor to the source node of the bit line. The method of claim 19, wherein the source reset voltage of the source follower is the source when the floating diffusion is reset to the reset floating diffusion voltage by the reset transistor The voltage value of the source terminal of the pole follower. An imaging system with a fast and stable output line circuit, including: a pixel array formed by pixel units, wherein each pixel unit includes: a photodiode adapted to accumulate image charges in response to incident light; at least one transfer transistor , Coupled between the photodiode and floating diffusion to transfer the image charge from the photodiode to the floating diffusion, wherein a transfer gate voltage controls the transfer of the image charge from the Transmission of the transfer receiving terminal of the transistor to the floating diffusion; a reset transistor coupled to supply a reset floating diffusion voltage to the floating diffusion, wherein a reset gate voltage controls the reset transistor; and a source A pole follower transistor, coupled to receive the floating diffused voltage from the source follower gate terminal and provide the amplified signal to the source follower source terminal; the bit line enable transistor, coupled in place Between the bit line and the bit line source node, wherein the bit line enable voltage controls the bit line enable transistor, and wherein the bit line source node is coupled to the black solar voltage generator; current source A generator, coupled between the source node of the bit line and the ground potential, wherein the current source generator provides an adjustable current to the source node of the bit line through a bias piezoelectric crystal, the bias voltage The transistor is controlled by a bias control voltage; control circuitry coupled to the pixel array to control the operation of the pixel array, wherein the control circuitry provides the transfer gate to the pixel array Voltage, the reset gate voltage, the column select gate voltage, the bit line enable voltage, the sample and hold voltage, the gate-ground voltage, the bias voltage, the clamp control voltage, the clamp enable voltage , Black sun control voltage, black sun enable voltage, idle control voltage and idle enable voltage; readout circuitry, coupled to the pixel array through multiple readout rows to read out image data from the multiple pixels And functional logic coupled to receive image data from the readout circuitry to store the image data from each of the plurality of pixel units, wherein the functional logic provides the control circuit The system provides instructions. The fast and stable imaging system as described in item 31 of the patent application scope further includes a transfer storage transistor, which is coupled between the photodiode and the transfer transistor to connect the photodiode The image charge accumulated in the pole body is transferred to the transfer receiving terminal of the transfer transistor, and a transfer storage gate voltage controls the transfer storage transistor. The fast and stable imaging system as described in item 31 of the patent application scope further includes a column selection transistor coupled between the source terminal of the source follower and the bit line, wherein the column A selection gate voltage controls the column selection transistor, and wherein the column selection transistor passes the amplified signal from the source follower source terminal to the bit line. The fast and stable imaging system as described in item 31 of the patent application scope further includes a column selection transistor coupled between the source follower drain terminal and the pixel voltage, where the column selection gate voltage controls Column select transistor The body, wherein the column selection transistor passes the pixel voltage to the source follower drain terminal, and wherein the source follower source terminal is connected to the bit line. The fast stable imaging system as described in item 34 of the patent application range, wherein the pixel voltage is connected to a power supply voltage. The fast stable imaging system according to item 34 of the patent application range, wherein the pixel voltage is connected to an adjusted voltage supply source, wherein the adjusted voltage supply source is adjusted based on the power supply voltage. The fast stable imaging system as described in item 34 of the patent application range, wherein the pixel voltage and the reset floating diffusion voltage have the same value. The fast stable imaging system as described in item 34 of the patent application range, wherein the pixel voltage and the reset floating diffusion voltage have different values. The fast and stable imaging system as described in item 31 of the patent application range, wherein the black solar voltage generator is configured to receive a pixel voltage and provide an adjustable black solar voltage to the bit line source node, and wherein The black sun voltage generator includes: a black sun power supply transistor configured to receive the pixel voltage and provide a black sun power supply voltage; a black sun transistor, coupled to receive the black sun power supply voltage and provide a An adjustable black solar voltage controlled by a black solar control voltage; and a black solar enabled transistor coupled to be controlled by the black solar enabled voltage to pass the adjustable black solar voltage to the source node of the bit line . The fast and stable imaging system as described in item 35 of the patent application scope further includes a clamp voltage generator configured to be connected to the source node of the bit line. The fast stable imaging system of claim 40 of the patent application range, wherein the clamp voltage generator is configured to receive the pixel voltage and provide an adjustable clamp voltage to the bit line source node, wherein The adjustable clamping voltage is lower than the adjustable black solar voltage, and wherein the clamping voltage generator includes: a clamping transistor configured to receive the pixel voltage and provide a voltage controlled by the clamping control voltage An adjustable clamping voltage; and a clamping enable transistor, coupled to be controlled by the clamping enable voltage to deliver the adjustable clamping voltage to the source node of the bit line. The fast stable imaging system as described in item 31 of the patent application range, wherein the bias voltage provides the bias control voltage. The fast and stable imaging system as described in item 31 of the patent application range, wherein the current source generator further includes a gate-to-negative power coupling between the bit line source node and the bias piezoelectric crystal For the crystal, the gate-yin earth transistor is controlled by the gate-yin earth control voltage. The fast and stable imaging system as described in item 43 of the patent application range, wherein the gate-ground voltage provides the gate-overground control voltage. The fast and stable imaging system as described in Item 43 of the patent application range, wherein the current source generator further includes: a gate-negative sample-and-hold transistor, coupled to receive the gate-negative voltage Providing the gate-yin ground control voltage controlled by the sample-and-hold voltage; a bias sample-and-hold transistor, coupled to receive the bias voltage and provide the bias control voltage controlled by the sample-and-hold voltage; A gate-negative ground holding capacitor is coupled between the gate-negative ground control voltage and the ground potential; and a bias holding capacitor is coupled between the bias control voltage and the ground potential. The fast and stable imaging system as described in item 31 of the patent application scope further includes an idle voltage generator configured to receive a pixel voltage and provide an idle voltage to the bit line, wherein the idle voltage The generator includes: an idle power supply transistor configured to receive the pixel voltage and provide an idle power supply voltage controlled by the idle control voltage; and an idle enable transistor coupled to be controlled by the idle enable voltage The idle power supply voltage is transferred to the bit line. The fast and stable imaging system as described in item 31 of the patent application scope further includes a transmission gate that transmits the amplified signal from the bit line to the input of the analog-to-digital converter.

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