CN1831783A - Data access device of peripheral element extension interface and its method - Google Patents
Data access device of peripheral element extension interface and its method Download PDFInfo
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- CN1831783A CN1831783A CN 200510033463 CN200510033463A CN1831783A CN 1831783 A CN1831783 A CN 1831783A CN 200510033463 CN200510033463 CN 200510033463 CN 200510033463 A CN200510033463 A CN 200510033463A CN 1831783 A CN1831783 A CN 1831783A
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- peripheral element
- extension interface
- element extension
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Abstract
A data access method of PCI includes inserting a data access unit on PCI of information processing unit to be measured, sending DEVSEL and STOP signals to PCI bus by inserted unit for carrying out Retry Cycle, locking a buffer storage module to each data of PCI bus cycle by microprocessor, storing them in an internal memory module in sequence and utilizing a display module to display out each data stored in internal memory.
Description
[technical field]
The present invention is a kind of relevant for data access arrangement and method thereof, particularly a kind of peripheral element extension interface (Peripheral Componect Interconnect, data access arrangement PCI) and method thereof.
[background technology]
Prosperity along with information industry, signal conditioning package becomes one of indispensable equipment of all trades and professions, and signal conditioning package is in the production phase, must wait via fault test and guarantee its quality, and peripheral element extension interface becomes indispensable test and system's debug project, the test card or the debugging system of peripheral element extension interface are all the real-time blocking display mode at present, only can latch one or two s' information, whether the tester comes pick-up unit normal by these information, but one or two information of real-time blocking, concerning signal conditioning package with complicated and huge electronic circuit, whether the signal conditioning package of judging test is normal, as if inadequate slightly, and when signal conditioning package latch data overlong time to be measured, can cause system to work as machine, and the debug operation is restarted, this is very consuming time and inefficent.
[summary of the invention]
Fundamental purpose of the present invention is to provide a kind of data access arrangement and method thereof of peripheral element extension interface.
The data access arrangement of peripheral element extension interface includes following modules: latch module, a cache module, a little processing and control module, a memory modules and a display module, utilize latch module to produce latch signal to cache module, cache module receives the data that begin to latch the peripheral element extension interface bus cycles behind the latch signal, and during a retry period (Retry Cycle), latch data is stored in the memory modules, show the data that are stored in the peripheral element extension interface bus cycles in the memory modules by display module again.
And the data access method of peripheral element extension interface includes the following step: the data that latch the peripheral element extension interface bus cycles; Inserting a device selects signal (DEVSEL#) to stop (STOP#) to produce a retry period (Retry Cycle) with one; Latch data is stored in the memory modules; After data storage was intact, little processing and control module produced a trigger pip to latch module, to stop retry period (Retry Cycle), with the data latching and the storage operation of carrying out the next record peripheral element extension interface bus cycles.
Compared to prior art, the examining system for the treatment of of the present invention is in start during the cycle, address, the data of each step that pci bus is carried out, orders and information such as enable is recorded as complete data file, effectively to carry out debug and test operation.
[description of drawings]
Fig. 1 is a system block diagrams of the present invention.
Fig. 2 is the data access sequential chart of peripheral element extension interface bus cycles of the present invention.
Fig. 3 is a flow chart of steps of the present invention.
[embodiment]
Please refer to Fig. 1, the data access arrangement 100 of peripheral element extension interface includes: latch module 10, cache module 20, little processing and control module 30, memory modules 40, display module 50, storage data are selected module 60, single step handover module 70 and data transmission module 80.
At first the data access arrangement 100 with peripheral element extension interface is installed on the pci bus 200 to be measured, open the power supply of signal conditioning package, latch module 10 produces a data latch signal to cache module 20, after cache module 20 receives data latch signal, begin to latch the data of peripheral element extension interface bus cycles, at this moment, latch module 10 can produce a look-at-me to little processing and control module 30, after little processing and control module 30 receives look-at-me, produce a predefined address to memory modules 40, memory modules 40 stores cache module 20 latched data according to the address that micro treatment module 30 produces, during data storage, latch module 10 can be inserted a device and select a signal (DEVSEL#) and a stop signal (STOP#), to produce a retry period (Retry Cycle), after data storage is intact, little processing and control module 30 produces a trigger pip to latch module 10, to stop retry period (Retry Cycle), and latch and store the operation of the data of next record peripheral element extension interface bus cycles, data storage up to all peripheral element extension interface bus cycles finishes, and a display module 50 is stored in the data of peripheral element extension interface bus cycles in the memory modules 40 in order to demonstration.
Wherein storage data select module 60 in order to the latch data gradation is stored in the memory modules 40, and the tester can pass through a single step handover module 70, the data that show the peripheral element extension interface bus cycles by pen, or via a data transmission module 80 (examples, serial transmission interface RS-232), the data of peripheral element extension interface bus cycles of access are sent to the signal conditioning package that another stores the data of correct peripheral element extension interface bus cycles, to carry out the data compare operation, make the more convenient to operate and efficient purpose of debug to reach.
Please refer to Fig. 2, at first frame signal (FRAME#) maintains a low level signal, represent the beginning of new peripheral element extension interface bus cycles, utilize a latch module to produce the signal and the data latching (D_Latch) 120 to cache module (Address ﹠amp of an address latch (A_Latch) 110; DataLatch Buffer) 20, during latch data is stored in memory modules 40, latch module 10 is inserted a retry period 130 ~ 140 to the peripheral element extension interface bus cycles, when latched data is stored in after memory modules 40 finishes, stop retry period 130 ~ 140, carry out following one-period (Cycle) with continuation, allow the data of next record peripheral element extension interface bus cycles enter cache module 20, and insert a retry period 130 ~ 140, when latched data is stored in after memory modules 40 finishes, stop retry period 130 ~ 140, the rest may be inferred, finish up to each data storage, show the data that are stored in the peripheral element extension interface bus cycles in the memory modules 40 by display module 50 again, allow the testing staff carry out data relatively, thus, can learn error bit at once, to carry out debug (Debug) operation, wherein retry period 130 ~ 140 utilization is inserted a device and is selected signals (DEVSEL#) to peripheral element extension interface in the bus cycles, before peripheral element extension interface bus-bar end cycle, do not receive when being ready for signal (TRDY#), again this peripheral element extension interface bus cycles, to continue the storage latch data, and after data storage is intact, after receiving device to be measured response and being ready for signal (TRDY#), insert stop signal (STOP#) to peripheral element extension interface in the bus cycles, stopping retry period 130 ~ 140, and carry out data latching and the storage operation of next record peripheral element extension interface bus cycles.
Please refer to Fig. 3, after at first being installed on the data access arrangement 100 of peripheral element extension interface on the peripheral element extension interface, open the power supply of signal conditioning package, at this moment, latch module send a latch signal to cache module with the data that latch the peripheral element extension interface bus cycles (latch data can be address Address[31..0]; Data Data[31..0]; Order Command; Enable signal BE#[3..0]) (step 300), latch data is stored in the memory modules, and insert a device and select signal (DEVSEL#) and a stop signal (STOP#) to this peripheral element extension interface in the bus cycles, to carry out retry period operation (step 305), the address that produces according to little processing and control module is stored in the memory modules (step 310) with latch data and after data storage is intact, stop retry period operation (step 315), to carry out latching and storage operation of next record data, so circulation finishes up to all data storage.
Next, lifting a concrete instance explains, at first the data access arrangement of peripheral element extension interface is inserted the motherboard of the signal conditioning package of to be measured or fault, wherein data access arrangement is to utilize the static random access memory of a microprocessor controller 89C52 and 64kBytes (Static Random Access Memory; SRAM), dot matrix LCD MODULE (Dot Matrix LCD Display Module), address and data latching buffer (Address ﹠amp; Data Latch Buffer), decoding and steering logic device (Decode ﹠amp; Control Logic), storage data selector (Store Data Selector), single step change-over switch modules such as (SwitchButton) is formed.
Open the power supply of signal conditioning package, just have the signal of first peripheral element extension interface bus cycles to produce in peripheral element extension interface bus (PCI Bus) this moment, and signal enters decoding and steering logic device (Decode ﹠amp; Control Logic), decoding and steering logic (Decode ﹠amp then; Control Logic) produces the latch signal of address latch (A_Latch) and data latching (D_Latch) to address and data latching buffer (Address ﹠amp; Data Latch Buffer), and insert device select signal (DEVSEL#) and stop signal (STOP#) to the peripheral element extension interface bus cycles carrying out a retry period (Retry Cycle) operation, this moment, microprocessor controller 89C52 just can produce address Address (0000h ~ 00009h) and the address Address (1000h ~ 1000Ah) with address and data latching buffer (Address ﹠amp of original definition; Data LatchBuffer) be latched into the first stroke data (the address Address[31..0 of peripheral element extension interface bus cycles]; Data[31..0]; Order Command; Enable signal BE#[3..0]), deposit static random access memory (the Static Random Access Memory of 64kBytes in batches; SRAM) in, because once only store 1byte, so need storage data selector (Store Data Selector) to divide ten data storage to finish, send out trigger pip Trigger_52 to decoding and steering logic device (Decode ﹠amp in having stored the back by microprocessor controller 89C52 then with peripheral element extension interface bus cycles; ControlLogic).
Then, decoding and steering logic device (Decode ﹠amp; Control Logic) receive one of device response to be measured and be ready for signal (TRDY#), to stop the retry period operation, so that allow the peripheral element extension interface bus carry out the transmission of next record data, decoding and steering logic device (Decode ﹠amp then; Control Logic) produces the latch signal of address latch (A_Latch) and data latching (D_Latch) again to address and data latching buffer (Address ﹠amp; Data Latch Buffer), with the data latching of second peripheral element extension interface bus at address and data latching buffer (Address ﹠amp; Data Latch Buffer) in, and inserts device and select signal (DEVSEL#) and stop signal (STOP#) in the bus cycles, to make the peripheral element extension interface bus cycles carry out the retry period operation again to peripheral element extension interface.
Next produce a look-at-me INT1 to microprocessor controller 89C52, this moment, microprocessor controller 89C52 just produced address Address (0000Ah ~ 00013h) and the address Address (10000h ~ 1000Ah), and with address and data latching buffer (Address ﹠amp of original definition; Data LatchBuffer) be latched into second data (the address Address[31..0 of peripheral element extension interface bus cycles]; Data Data[31..0]; Order Command; Enable signal BE#[3..0]) add up into static random access memory (the Static Random Access Memory of 64kBytes in batches; SRAM) in, the data of each peripheral element extension interface on the bus cycles are deposited among the SRAM so repeatedly then (deposited the Address (00000h ~ 0FFFFh) take 1.2 seconds approximately) of 64kBytes data, produce the signal of step (Step) to microprocessor controller 89C52 by the testing staff by single step change-over switch (Switch Button) again, so that the data among the SRAM are pursued being shown on the dot matrix LCD MODULE (Dot Matrix LCD DisplayModule) of pen, to allow the testing staff carry out data relatively, or with the data among the SRAM via the transmission (TXD) of microprocessor controller 89C52 and receive (RXD) pin position and see through data transmission module (example, serial transmission interface RS-232) is sent on another station information treating apparatus, and another station information treating apparatus can be in advance gets up the data storage of normal peripheral element extension interface bus cycles of homotype, and then the data that peripheral element extension interface bus cycles of this information processing apparatus system to be measured send are made comparisons, so can learn the place of difference or error bit at once, allow the testing staff can find out the trouble spot of information processing apparatus system to be measured soon, get rid of operation to carry out fault.
Data access arrangement and method thereof by this peripheral element extension interface, can write down the data of every peripheral element extension interface bus cycles, solve the data that prior art only can latch one or two peripheral element extension interface bus cycles with the interception display mode, so that tester or maintenance personal to be provided the data of more complete peripheral element extension interface bus cycles, reach more efficient test and maintenance purpose.
Claims (14)
1. the data access arrangement of a peripheral element extension interface, this device comprises:
One latch module, in order to produce a latch signal, to latch the data of peripheral element extension interface bus cycles (PCI Bus Cycle), and insert a retry period (Retry Cycle) to these peripheral element extension interface bus cycles, in order to repeat this peripheral element extension interface bus cycles to latch the data of this peripheral element extension interface bus cycles, and after the data that latched this peripheral element extension interface bus cycles, produce a look-at-me;
One cache module provides the data of these peripheral element extension interface bus cycles that a buffer area latchs with temporary transient storage;
One little processing and control module, receive this look-at-me after, produce a predefined address;
One memory modules is stored the data of these peripheral element extension interface bus cycles that this cache module latchs according to this predefined address; And
One display module is stored in the data of these peripheral element extension interface bus cycles of latching in this memory modules in order to demonstration;
Wherein, this little processing and control module produces a trigger pip to this latch module, in order to stop this retry period after the data storage of these peripheral element extension interface bus cycles of latching is intact.
2. the data access arrangement of peripheral element extension interface according to claim 1, it is characterized in that: this latch data comprises the address (Address) of this peripheral element extension interface bus cycles.
3. the data access arrangement of peripheral element extension interface according to claim 1, it is characterized in that: this latch data comprises the data (Data) of this peripheral element extension interface bus cycles.
4. the data access arrangement of peripheral element extension interface according to claim 1, it is characterized in that: this latch data comprises the order (Command) of this peripheral element extension interface bus cycles.
5. the data access arrangement of peripheral element extension interface according to claim 1, it is characterized in that: this latch data comprises the enable signal of this peripheral element extension interface bus cycles.
6. the data access arrangement of peripheral element extension interface according to claim 1, it is characterized in that: more comprise a single step handover module, join with this little processing and control module, in order to produce a step signal to show the data of these peripheral element extension interface bus cycles by pen.
7. the data access arrangement of peripheral element extension interface according to claim 1, it is characterized in that: this memory modules comprises a static random access memory.
8. the data access arrangement of peripheral element extension interface according to claim 1, it is characterized in that: this display module comprises some array liquid crystal displays.
9. the data access method of a peripheral element extension interface, this method comprises the following step:
Latch the data of peripheral element extension interface bus cycles;
Inserting a device selects signal (DEVSEL#) in the bus cycles, when these peripheral element extension interface bus cycles finish, to carry out again retry period (Retry Cycle) operation of these peripheral element extension interface bus cycles to this peripheral element extension interface;
To latch the data storage of this peripheral element extension interface bus cycles to a memory modules; And
After the data of having stored this peripheral element extension interface bus cycles, signal (TRDY#) is ready in preset device response one, in the bus cycles, stops this retry period operation to this peripheral element extension interface to insert a stop signal (STOP#).
10. the data access method of peripheral element extension interface according to claim 9 is characterized in that: more comprise by pen and show that the data of these peripheral element extension interface bus cycles are in the step of a display module.
11. the data access method of peripheral element extension interface according to claim 9 is characterized in that: this latch data comprises the address (Address) of this peripheral element extension interface bus cycles.
12. the data access method of peripheral element extension interface according to claim 9 is characterized in that: this latch data comprises the data (Data) of this peripheral element extension interface bus cycles.
13. the data access method of peripheral element extension interface according to claim 9 is characterized in that: this latch data comprises the order (Command) of this peripheral element extension interface bus cycles.
14. the data access method of peripheral element extension interface according to claim 9 is characterized in that: this latch data comprises the enable signal of this peripheral element extension interface bus cycles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100334639A CN100397357C (en) | 2005-03-11 | 2005-03-11 | Data access device of peripheral element extension interface and its method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100334639A CN100397357C (en) | 2005-03-11 | 2005-03-11 | Data access device of peripheral element extension interface and its method |
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| Publication Number | Publication Date |
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| CN1831783A true CN1831783A (en) | 2006-09-13 |
| CN100397357C CN100397357C (en) | 2008-06-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005100334639A Expired - Fee Related CN100397357C (en) | 2005-03-11 | 2005-03-11 | Data access device of peripheral element extension interface and its method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100465916C (en) * | 2007-04-23 | 2009-03-04 | 杭州华三通信技术有限公司 | Failure diagnosis method, device and system for PCI system |
| CN100568205C (en) * | 2007-12-28 | 2009-12-09 | 威盛电子股份有限公司 | Data trade blocking method and device |
| CN101222430B (en) * | 2008-01-24 | 2011-01-19 | 中兴通讯股份有限公司 | High-speed multi-protocol data transmission system and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW508490B (en) * | 1999-08-27 | 2002-11-01 | Via Tech Inc | PCI debugging device and method and chipset and system using the same |
| CN1161694C (en) * | 2000-12-06 | 2004-08-11 | 神达电脑股份有限公司 | One-step interrupt debugging card unit for PCI bus period and its operation process |
| CN1221902C (en) * | 2001-06-21 | 2005-10-05 | 神达电脑股份有限公司 | Method and device for debuggin with single-step interrupt in peripheral element interconnection bus cycle |
-
2005
- 2005-03-11 CN CNB2005100334639A patent/CN100397357C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100465916C (en) * | 2007-04-23 | 2009-03-04 | 杭州华三通信技术有限公司 | Failure diagnosis method, device and system for PCI system |
| CN100568205C (en) * | 2007-12-28 | 2009-12-09 | 威盛电子股份有限公司 | Data trade blocking method and device |
| CN101222430B (en) * | 2008-01-24 | 2011-01-19 | 中兴通讯股份有限公司 | High-speed multi-protocol data transmission system and method |
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| Publication number | Publication date |
|---|---|
| CN100397357C (en) | 2008-06-25 |
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Granted publication date: 20080625 Termination date: 20140311 |