CN1822390A - 半导体器件边缘终端结构及方法 - Google Patents
半导体器件边缘终端结构及方法 Download PDFInfo
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- CN1822390A CN1822390A CN200510022821.6A CN200510022821A CN1822390A CN 1822390 A CN1822390 A CN 1822390A CN 200510022821 A CN200510022821 A CN 200510022821A CN 1822390 A CN1822390 A CN 1822390A
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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Abstract
在一个实施方案中,在具有第一导电类型的一半导体层内形成一个边缘终端结构。该终端结构包括一个隔离槽和一个和半导体层相接触的导电层。该半导体层是在具有第二导电类型的一片半导体基片上形成的。在一个进一步的实施方案中,该隔离槽包括多个形状,这些形状包含部分半导体层。
Description
技术领域
本发明一般地涉及半导体器件,更具体地讲,涉及功率开关器件及其制造方法。
背景技术
金属-氧化物半导体场效应晶体管(MOSFETS)是功率开关器件的一种常用类型。一个MOSFET器件包括一个源区,一个漏区,一个在源和漏区之间延伸的沟道区,以及在沟道区邻近提供的一个栅结构,该栅结构包括一个导电的栅电极层,它被安置在该沟道区邻近但又被一层薄的电介质层和沟道区隔开。
当一个MOSFET器件处于导通状态时,一个电压被加至栅结构以在源和漏区之间形成一个导电沟道区,从而允许电流流过该器件。在断状态下,加到栅结构上的任何电压是足够小,以致不能形成一导电沟道,从而不能产生电流流动。在断状态时,该器件必须承受在源和漏区之间的一个高的电压。
当前的高电压功率开关市场被两个主要参数驱动:击穿电压(BVdss)和通态电阻(Rdson)。对于一个具体的应用,需要一个最小的击穿电压,而在实践中,设计人员通常能够满足一个击穿电压的规格。然而,这经常要以通态电阻的增大为代价。这种性能上的二者兼顾是对于高压功率开关器件的制造商和使用者的一个主要的设计上的挑战。
最近,超结器件(superjunction deVices)已经得到广泛使用以改进在击穿电压和通态电阻之间不易兼顾的情况。在一个带规的n-沟道超结器件中,用多个高掺杂扩散n型和p型区来代替一个抵掺杂n型外延区。在通状态下,电流流过高掺杂n型区,它使Rdson变小。而在断状态下,该高掺杂n型和p型区耗尽或互相补偿以提供一个高的BVdss。虽然超结器件显得很有希望,但在制造上仍存在重大的挑战。
目前高电压功率开关产品的另一个问题是,它们通常需要一个大的输入(例如,栅或控制电极)电荷以从一个态转化为另一态。这个要求,除了其它效果以外,还对外部控制电路加上一个额外的负担。
因而,就需要这样的高电压功率开关器件结构及其制造方法,这能提供低的Rdson,高的BVdss,以及小的输入电荷。
附图说明
图1给出按照本发明的开关器件的一张放大的部分截面图;
图2到图7给出图1的开关器件在不同的制造阶段上的放大的部分截面图;
图8是显示图1开关器件击穿电压特性的曲线图;
图9是显示图1开关器件通态电阻特性的曲线图;
图10给出一种单元结构的一张放大的部分顶视图,此结构适用于按照本发明的开关器件。
图11给出按照本发明的一个开关器件及边缘终端结构的一张放大的部分截面图。
图12给出按照本发明的另一种槽隔离结构的一张放大的部分顶视图。
图13给出图12的槽隔离结构,在制造的早期阶段,沿着参照线13-13的一张放大的部分截面图。
图14给出图13的结构在进一步加工以后的一张放大的部分截面图;以及
图15给出按照本发明的另一个槽隔离结构的一张放大的部分截面图。
具体实施方式
为了容易理解,图中的元件不一定画成按比例,而在各个图中,只要合适,就用相同的元件号。虽然如下讨论描述了一个n-沟道的器件,但本发明也适合于p-沟道器件,这种器件可以用把所述各层和各个区域的导电类型都反过来而形成。
另外,本发明的器件可以体现为蜂窝状设计(其中体区是多个蜂窝状区),或单体设计(其中体区是包含一单个的区域,该区以一个伸长的形状,典型地以一种蜿蜒的图案形成)。然而,在整个叙述中,为容易理解起见,本发明的器件将被描述为一种蜂窝状的设计。应当理解,我们要求本发明既包括网状设计,也包括单个基的设计。
图1给出按照本发明的一个绝缘栅场效应晶体管(IGFET),MOSFET,超结器件,或开关器件,或蜂窝状设计单元10的一张放大的部分截面图。作为举例,器件10是作为许多这种器件的一种,这种器件作为功率集成电路的一部分与逻辑电路和/或其它元件一起集成进一半导体芯片。器件10也可以是许多这种器件的一种,这种器件集成在一起以形成一个分立的晶体管器件。
器件10包括半导体材料11,它包含,例如,n型硅基片12,其电阻率在约0.001到约0.005欧姆-厘米范围内,以及它可以掺以砷。在所示的实施方案中,基片12提供一个漏接触。在基片12内或在基片12上形成一半导体层14,而按照本发明,它被轻掺以n-型或p-型杂质,或包含可以忽略的杂质量(也即,它是本征的)。在一个示例性的实施方案中,层14是用常规的外延生长技术形成的。在一个适用于750从器件的示例性实施方案中,层14是p-型,其掺杂浓度在约1.0×1013原子/cm3到约5.0×1013原子/cm3。而厚度约为40μm。层14的厚度依赖于器件10的所要求的BVdss等级而增加或减小。当然,其它材料,包括硅-锗,硅-锗-碳,掺硅碳,或其它等也可以用于半导体材料体11或作为其一部分。
器件10也包括一层n-型区或覆盖层17,它在半导体材料11上表面或主表面内或其邻近形成。N型区17对于器件10提供了一低电阻电流通道,这将在下面更详尽地加以叙述。在一个示例性实施方案中,n-型区17具有约6.0×1016原子/cm3的最大浓度,以及约0.4微米的深度。也可以在主表面18内或邻近主表面18再形成一个P-型区或覆盖层19,它位于n-型区17下面或邻近。P型区19提供对在n型区17和半导体层14之间的pn结更好的控制,并在完全耗尽的条件下提供对n-型区17的电荷补偿。在一个示例性的实施方案中,p-型区19有约5.0×1015原子/cm3的表面浓度,以及约0.8微米的深度。
按照本发明器件10还包括填充槽,半导体材料填充槽,外延填充区或槽,电荷补偿槽区,深槽电荷补偿区,电荷补偿填充槽或电荷补偿区22。电荷补偿填充槽22包括多个层或多个半导体材料层,包括相反导电类型的层,其间最好被一个或n个本征或缓冲半导体层所隔开。该本征层,除了起其它作用外,起着防止相反导电类型层(也即,该两个电荷层)的内部混杂的作用,而这种内部混杂将对在导通状态下器件10的导电效率起负面影响。
在一个示例性的实施方案中,填充槽22包括用外延生长技术形成的半导体材料的多个层或叠层。例如,填充槽22包括一个n型层23,它在槽壁或邻近半导体材料体11的表面上,或在其邻近形成。而一本征半导体或缓冲层24在n-型层23上,或在其邻近形成,一个p-型层26在本征半导体层24上,或在其邻近形成,以及一本征半导体或缓冲层27在p-型层26上,或在其邻近形成。本征层24,除了起其它作用外,起着防止层23和26相互混杂的作用,而这,如前所述,改进了器件10的导电效率。本征层27,除了起其它作用外,起填充槽剩余空间的作用。对于一个n-沟道器件,以及按照本发明,n-型层23提供了在器件10处于通状态时,从沟道到漏的一个主要的垂直低电阻电流通道。当器件10处于断状态时,按照本发明,n-型层23和p-型层26互相补偿,以提供一个提高的BVdss特性。当然还可以用附加n-型和p-型层,以及它们最好被附加的本征或缓冲层隔开。
作为举例,n-型层23和p-型层26分别有约2.0×1016到约4.0×1016原子/cm3的掺杂浓度,分别有约0.1μm到约0.3μm的厚度。在一个示例性的实施方案中,本征半导体或缓冲层24和27,是非掺杂或很轻p型掺杂的,其掺杂浓度小于约2.0×1014原子/cm3,并分别有约0.5μm到约1.0μm的厚度。层27的厚度被调整到,例如,用以填充槽的剩余部分。
在半导体层14内,在填充槽22之间并在其邻近处形成一个体或掺杂区31,并从主表面18向下延伸。在一个示例性实施方案中,体区31具有p-型导电性,并如下所述具有这样的掺杂浓度,它适合于形成一个作为器件10的导电沟道45的反型层。体区31从主表面18向下延伸至约1.0到约5.0μm的深度。在体区31内形成一个n-型源区33,它从主表面18向下延伸至约0.2到约0.5μm的深度。在体区31内也形成一个p-型体接触或接触区36,它提供在主表面18上对于体区31的一个低接触电阻。另外接触区36降低了在源区33之下的体区31的薄层电阻,这就抑制了寄生双极效应。
在一部分主表面18上面或其邻近形层一第一电介质层41。在一个示例性实施方案中,电介质层41包含一层热氧化层,其厚度约为0.1μm到约0.2μm。在电介质层41上形成一第二电介质层42。在一个示例性实施方案中,第二电介质层包含氮化硅,并有约0.1μm的厚度。
在邻近体区31的另一部分主表面18上或其邻近形成栅电介质层43。在一个示例性实施方案中,栅电介质层43包含二氧化硅,其厚度约0.05μm到约0.1μm。在另一个实施方案中,栅电介质层43包含氮化硅,五氧化钽,二氧化钛,钛酸钼锶,或其组合,包括与二氧化硅的组合或其它等。
按照本发明的一个实施方案,在电介质层41和42上形成一层掺杂多晶半导体层,导电层,或接地平面层46,它通过在电介质层41和42上形成的开口与p-型层26相接触。在一个示例性实施方案中,导电层46包含一多晶硅层,有约0.1μm的厚度,以及对于一个n-沟道器件具有p-型导电性,当热处理时,p型杂质从导电层46扩散进填充槽22以形成p-型掺杂区52,这就加强了对于p-型层26的欧姆接触。在另一个实施方案中,导电层46包含非晶硅,一种金属,一种硅化物或其组合,包括与多晶硅的组合。如果一种金属被用于导电层46,则先把p-型杂质通过开口47植入或淀积以形成p-型掺杂区52,从而增强对于p-型层26的欧姆接触。导电层46最好直接或间接地连接或耦合至一个导电接触或如图1所示的源接触层63。
按照本发明,导电层46除了其它作用外,起着一个接地平面的作用,从而为少数载流子更快和更有效地被从器件扫出提供一个通道,从而降低了把开关器件10从一个状态转向另一状态所需要的输入电荷,以及提高了开关速度。另外,如同将在后面更详尽解释的那样,按照本发明,导电层46还被用作边缘终端结构的一部分。
在导电层46上面形成一第三电介质层48,而在第三电介质层上面形成一第四电介质层51。在一个示例性实施方案中,电介质层48包含氮化硅(例如,约0.05μm的厚度),以及电介质层51包含一淀积二氧化硅(例如约0.7μm的厚度)。在电介质层51上面形成一导电层53,它包含,例如,n-型多晶硅(例如,0.3μm的厚度)。
在栅电介质层43上形成导电间隔器栅区域,垂直间隔器栅区域,或间隔器限定的栅区域57,它们被电介质间隔器59与导电层46隔开。导电间隔器栅区域57和栅电介质形成一个控制电极或栅结构58。导电间隔器栅区域57包含,例如,n-型多晶硅,并约有0.8μm厚。在一个示例性实施方案中,电介质间隔器59包含氮化硅,并约有0.1μm厚。间隔器栅区域57被耦合至导电层53,以提供一个导电栅结构,它控制沟道45的形成以及在器件10中的电流的传导。在如图所示的实施方案中,一个导电连接区77把间隔器栅区57耦合至导电层53。导电连接区77包含,例如,n-型多晶硅。一个间隔器栅区是指以淀积在一个表面上的栅材料形成的一个控制电极来控制在另一个垂直表面上形成的沟道。在器件10的情况下,沟道45是在表面18处形成的,这个表面被认为是一个水平表面。用来形成间隔器栅区57的控制电极薄膜是沿着垂直表面68淀积的,此表面是和表面18相垂直的。
按照本发明的导电间隔器栅区57,比起常规器件提供一个最小的栅到漏的重迭,从而显著地减小栅电荷。另外,在器件10中,对于栅的电学路径是由导电层53提供的,而它抬起在主表面18之上,从而进一步减小了栅电荷。另外,导电层46,除了起着其它作用以外,起着插在栅和漏区之间的一个接地平面的作用,从而进一步减小栅到漏的电容。本发明的这些特征提供提高了的开关速率以及减小了输入电荷要求。
在器件10的各部分上面形成一第五电介质层61,它包含,例如,厚度约为0.5μm的氮化硅。在器件10的各部分上形成一层间电介质(ILD)层62,它包含,例如,厚度约0.8μm的淀积二氧化硅。在各层电介质层内为源接触层63形成一个开口,以提供对器件10的一个接触。如图所示,主表面18的一部分被腐蚀以使源接触层63既与源区33又和体区36接触。在一个示例性实施方案中,源接触层63包含一种铝硅合金或其它等。一个漏接触层66在半导体材料11的相对面上形成,它包含,例如,一种可焊接金属结构,诸如钛-镍-银,铬-镍-金,或其它等。
器件10的工作按如下进行。假定源端63被加上零伏的电势Vs。而间隔器栅区57接收到一个控制电压VG=5.0伏,该电压大于器件10的导通阈值,而漏端66被加上一个漏电势VD=5.0伏。VG和Vs的数值引起体区31在间隔器栅区57下部反型以形成沟道45,它把源区33电连接到层17。一个器件电流Is从源端63流出,经过源区33,沟道45,层17,n-型层23,流至漏端66。因而电流Is通过n-型层23垂直流动,以产生一个小的导通电阻。在一个实施方案中,Is=1.0安培。为了把器件10转向断开状态,它把一个小于器件导通阈值的控制电压VG加到间隔器栅57(例如,VG<5.0V)。这就使沟道消失,Is不再流过器件10,而导电层46把少数载流子从器件中扫出。在断状态下,n型层23和p-型层26作为来自主阻挡结扩散的耗尽区互相补偿,从而提高了BVdss。在一个实施方案中,主阻挡结是由体区31和半导体层14形成的,其中层14是n-型。在另一个实施方案中,主阻挡结是由半导体层14和基片12形成的,其中层14是p型。
现在转向图2-7,其中描述了按照本发明的器件10的形成过程。图2给出在制造的早期阶段,器件10的一张放大的部分截面图。在一个早期步骤中,在主表面18上形成一层电介质层40,以及通过电介质层40一个选用的p-型区19被离子植入进半导体层14。在一个示例性实施方案中,硼被植入,其剂量约为5.0×1011原子/cm2,而植入能量为600keV,以形成p-型层19。接着,通过电介质层40,n型层17被离子植入半导体层14。在一个示例性实施方案中,磷被植入,其剂量约为2.0×1012原子/cm2,植入能量为600keV,以形成n-型层17。
接着在主表面18上形成掩蔽层71,并构图以形成开口72。然后用常规的方法来腐蚀电介质层40,以把部分半导体材料体11通过开口72暴露出来。作为例子,开口72的宽度74有约3.0μm到约5.0μm的量级。接着通过层17,19和14,腐蚀出槽122。在一个示例性实施方案中,槽122至少延伸进基片12的一部分。槽122的深度由半导体层14的厚度来决定,而这厚度又是BVdss的一个函数。在一个示例性的实施方案中,用一种基于氟或氯化学试剂来进行深度反应离子腐蚀(DRIE),以形成槽122。对DRIE腐蚀可以用几种工艺,包括低温,高密度等离子体,或Bosch DRIE腐蚀工艺。在一个示例性实施方案中,槽122有基本垂直的侧壁。在另一个实施方案中,槽122有一个椎形的轮廓,其中在槽下表面槽的宽度比宽度74要小。在形成槽122以后,用常规的腐蚀方法把掩蔽层71除去。虽然在图中把槽122画成两个,但应当注意到,槽122也可以是单个的连续槽或者是相互连接的槽的阵列(例如,诸如图10中所示并将在后面描述的那样的槽)。槽122也可以是多个具有闭合端头的独立的槽,它们被半导体材料体11的各个部分所分开。
图3给出了器件10在制造的下一个阶段上的一张放大的部分截面图。在这个阶段上,作为形成填充槽122的第一阶段,各个半导体材料层在槽122内被形成,生长,或淀积。在一个示例性实施方案中,用了半导体外延生长技术来填充槽122。
在第一步中,在槽122的侧壁上形成一薄层热氧化物,以去除由DRIE步骤所引起的表面损伤。接着用常规的各向同性腐蚀方法把该薄层热氧化物除去。之后,把半导体材料体11放进一个外延生长反应器并把预清洗作为该外延生长过程的第一步。当硅是对于填充层(例如,层23,24,26,和27)所选的半导体材料时,诸如SiHCl3,SiH2Cl2,SiH4或Si2H6这种硅源气体是适应于形成这些层的。在所示的实施方案中,生长的是覆盖层(也即该层不仅生长在槽122表面上,还生长在整个主表面18上)。在另一个实施方案中,用选择性外延生长技术来形成层23,24,26和27,以使这些层没有在电介质层40上形成。
N-型层23首先沿着槽122的表面上生长,而以砷作为一种合适的掺杂源。在一个示例性实施方案中,n型层23有约2.0×1016到约4.0×1016原子/cm3的掺杂浓度,以及约0.1μm到约0.3μm的厚度。
接着,在n型层23上生长本征或缓冲层24,该层或者是不掺杂的(除了在硅源材料中通过存在的微量杂质和/或在以前的生长步骤之后在反应室中保留的残余掺杂气体),或者是非常轻的p-型掺杂,其掺杂浓度小于约2.0×1014原子/cm3。层24有约0.5μm到约1.0μm的厚度。接着在层24上生长p-型层26,它适应用硼掺杂源。在一个示例性实施方案中,p-型层26有约2.0×1016到约4.0×1016原子/cm3的掺杂浓度和约0.1μm到约0.3μm的厚度。接着在p-型层26上生长本征或缓冲层27,它或者是不掺杂的(除了在硅源材料中通常存在的微量杂质和/或以前生长步骤后在反应室中保留的残余掺杂气体),或者是非常轻的p-型掺杂,其掺杂浓度小于约2.0×1014原子/cm3。层27有约0.5μm到约1.0μm的厚度。可以理解,层23,24,26和27的厚度按照槽122的宽度来调整。在一个示例性的实施方案中,这些层的厚度使所得到的各外延层把槽122填满。当用覆盖式外延生长方法时,层27,26,24和23之后用化学机械抛光技术,内腐蚀(etch-back)技术,其组合,等等来平面化。在平面化过程中,外延层27,26,24,23被向下平面化至,或回到主表面18,以形成填充槽122。在一个示例性实施方案中,该平面化过程也把电介质层40除去。还可以用一个附加的腐蚀步骤来进一步除去任何从层40残留的电介质材料。如果选择性外延生长或选择性内腐蚀技术被持用,那么电介质层40可以保留,它将取代层41,如下所述。
图4给出在进一步处理后,器件10的一张放大了的部分截面图。首先,在主表面18上形成一第一电介质层41,它包含,例如,一层约0.1μm到约0.2μm厚的二氧化硅。在约750℃下的热氧化生长是合适的。在一个可选用的步骤中,用溅射腐蚀步骤来平滑第一电介质层41的上部或暴露的表面。接着在第一电介质层41上形成第二电介质层42,它包含,例如,约0.1μm的氮化硅。接着采用光刻和腐蚀步骤以形成通过第二电介质层42和第一电介质层41的开口47。从而把在填充槽22上部的主表面18的一部分暴露出来,如图4所示。在一个示例性的实施方案中,开口47的宽度49有约0.5μm到约1.0μm。
接着在第二电介质层42上形成导电层46,它通过开口47,与填充槽22接触或耦合。在一个示例性实施方案中,导电层46包含约0.1μm的多晶硅,它也可以是掺杂淀积,也可以是非掺杂淀积。如果导电层46一开始是非掺杂淀积,那么导电层46之后要用,例如,离子植入技术来掺杂。在这个示例性的实施方案中,导电层46被掺以硼,以提供一个对于p-型层26的接触。一个具有植入能量约60keV,约5.0×1015到约1.0×1016原子/cm2的硼离子植入剂量对于掺杂导电层26是充够的。在之后的加热处理步骤中,杂质从导电层46扩散进填充槽22中去以形成p-型区52。
接着在导电层46上形成第三电介质层48,而在第三电介质层48上形成第四电介质层51。第三电介质48包含,例如,氮化硅(例如约0.05μm厚度),而电介质层51包含一淀积氧化物(例如,约0.7μm厚)。接着在第四电介质层51上形成导电层53,它包含,例如,n型多晶硅(例如,约0.3μm厚度)。在导电层53上面形成一层保护层54,它包含,例如,约0.15μm的氮化硅。
用光刻和腐蚀的步骤来腐蚀穿层54,53,51,48,46和42的部分区域以提供开口70。这同时也形成了台阶堆层结构56,它包含层42,46,48,51,53和54的各个部分的区域。在一个示例性的实施方案中,开口70的宽度73在约5.0μm到约8.0μm之间。
图5给出在经过形成电介质间隔器59这又一个处理步骤以后,器件10的放大了的部分截面图。在一个示例性实施方案中,在台阶堆层结构56和第一电介质层41上面淀积一层氮化硅薄膜。作为举例,用化学蒸汽淀积工艺淀积一层约0.1μm厚的氮化硅薄层。接着,用常规的各向异性内腐蚀步骤来除去在台阶堆层结构56上和第一电介层41上的部分氮化硅层,同时保留了在台阶堆层结构56的侧壁上或垂直表面68上的那部分氮化硅层,以形成电介质间隔器59。
接着用氧化硅湿腐蚀方法来除去在开口70内的那部分电介质层41。作为举例,用烯的氢氟酸(例如,50∶1)来腐蚀电介质层41。在一个示例性的实施方案中,该腐蚀时间是被推长了(例如,8到15分)以从电介质间隔器59的下部底切或除去电介质层41的材料,以形成凹入部分74。以这样方式的凹入的电介质层41保证在体区31中形成的沟道45(如图1所示)延伸进层17,以使沟道电流更有效地流动。在一个示例性实施方案中,在电介质间隔器59之下,区74凹入距离约0.1μm。接着在开口70内的主表面上生长一层(厚度约0.08μm)热氧化硅,以形成栅电介质层43。
图6给出在进一步处理以后器件10的一个放大的部分截面图。一共形半导体材料层被淀积在器件10上,其厚度约为0.1μm到约0.15μm。接着通过开口70和共形半导体材料层把硼杂质引入主表面18,以对体区31提供p-型杂质。在一个示例性实施方案中,共形半导体材料层包含非掺杂多晶硅,而硼是通过非掺杂多晶硅植入层17的。一个约1.0×1013原子/cm2的离子植入剂量和约160keV的植入能量对于650伏器件是合适的。在植入步骤以后,用一个清洗或腐蚀过程来清洁共形半导体材料层的表面。
接着在第一共形层上淀积一第二共形半导体材料层,并腐蚀这两层以提供间隔栅57。在一个示例性实施方案中,第二共形半导体材料层包含约0.8μm的n-型多晶硅,它可以在淀积过程中掺杂或以后用离子植入或其它掺杂技术来掺杂。在间隔器栅57形成后,再在间隔器栅57的表面和栅氧化物43的暴露区上加上一层0.015μm的栅电介质(例如二氧化硅)。
在一个示例性实施方案中,该腐蚀步骤将电介质层54和电介质间隔器59的上部暴露出来。接着腐蚀电介质层54和电介质间隔器59的上部,保护层54被除去,在间隔器栅57和导电层53之间电介质间隔器59的上部破除去。
在下一步骤中,诸如多晶硅这样的导电材料被淀积以提供连接性导电区77。连接性导电区77把间隔器栅57耦合至或电连接至导电层53。然后进行n-型掺杂步骤以对连接性导电区77掺杂,并对源区33提供掺杂剂。在一个示例性实施方案中,一种剂量为3.0×1015原子/cm2,植入能量为80keV的砷植入被用于该掺杂步骤。
图7给出在后面的制造步骤以后,器件10的一张放大的部分截面图。第五层电介质层61被淀积,它包含,例如,约0.05μm的氮化硅。接着在第五层电介质层61上淀积ILD层62。在一个示例性实施方案中,ILD层62包含一厚度约为0.8μm淀积二氧化硅层。一种可选的ILD锥形腐蚀被用于ILD层62的锥形区62a。这有助于对以后形成的层的阶梯覆盖。
接着,一种常规的光刻和腐蚀步骤被用来形成接触开口81,它使一部分主表面18暴露出来。接着通过开口81用一个p-型离子植入步骤来形成接触区36。作为举例,用了3.0×1014原子/cm2的硼离子植入剂量和80keV的植入能量。接着一层共形间隔器层被淀积和腐蚀以形成间隔器82。在一个示例性实施方案中,一层0.3μm的氮化硅层被淀积和腐蚀以形成间隔器82。在这时用一个快速退火步骤以激活和扩散各种离子植入。例如,器件10被暴露于约1030摄氏度的温度约45秒钟。
接着用一个腐蚀步骤来除去一部分主表面18以形成凹入区域84。这就允许源接触层63既能接触源区33又能接触接触区36,从而把这两个区短路在一起。接着把间隔器82除去。在以后的处理中,源接触层63被淀积及形成图形,接着基片12可选地被减薄,以及淀积漏接触层66以提供如图1所示的结构。虽然在图2-7中没有显出,在所述的制造阶段中,用了光刻和腐蚀步骤,例如,在图4-6中,把部分导电层46暴露出来以提供开口,而在开口处源接触区63耦合至导电层46,如图1所示。可以理解,在淀积源接触层63以前,可以形成其它导电层,诸如硅化物层。
图8是描述按照本发明,并按照这里给出的工艺参数的器件10的击穿电压(BVdss)特性的一张曲线图。如图8所示,器件10显示约750V的从漏到源的标称击穿电压,另外如图8所示,器件还显示在击穿以下的低的漏电。
图9是描述按照本发明,并按照这里给出的工艺参数的器件10的通态电阻(Rdson)特性。器件10比起具有相同BVdss的常规的超结器件显示优越的Rdson特性,而后者典型的Rdson值是约36毫欧姆cm2。
图10给出按照本发明,对器件10适宜的一种蜂窝结构300的一张放大的部分截面图。图中给出按照本发明的一个实施方案的蜂窝结构,它有一种填充槽322,它包围着许多个半导体层14的多边形区,而有源器件或单元在此形成。显然多边形区域可以有圆角,以及其它形状,包括圆的、正方的、长方的或其它等也是适合的。蜂窝结构300的一个特征是它提供了一个高的堆积密度,从而改进了Rdson和电流携带能力。按照本发明,填充槽322包括n-型层23,本征层24和27,以及p-型层26。
图11是器件10另一部分的一张放大截面图,它给出按照本发明的一种可选用的边缘终端结构100。终端结构100的一个特征是它合并了器件10的基本部件,从而节省了处理成本。终端结构100包括一个导电接触层或导电层146,导电接触层或导电层146在主表面18上并邻近于主表面处形成。在一个示例性实施方案中,导电接触层146和导电层46包含相同的材料并在同一时间形成。例如,导电接触层146包含p-型多晶硅。在一次热处理后,p-型杂质将从导电接触层146扩散而形成p-型掺杂层152,该层是对n-型层17反掺杂的结果,它耦合至可选用的p-型层19。图11还显示导电接触层146通过开口91耦合至源接触层63。
在器件10的外围形成一个隔离槽103,这包含,例如,一个腐蚀出的槽106,其中填充以一种电介质材料108。可选地,先形成一层热氧化层110以垫衬隔离槽103的侧壁和/或下表面。
在另一个实施方案中并如图11所示,隔离槽113还包括半导体材料层,它与填充槽22同时形成。作为举例,该半导体材料层包括n-型层23,本征或缓冲层24,p-型层26,和本征或缓冲层27,如结合图1所示已经描述的那样,如果没有包括这些半导体材料层,那么在制造过程中,槽106是和填充槽22分别形成的。
在一个示例性实施方案中,电介质材料108包含用SOG(旋涂玻璃,spin-on glass)BPSG,PSG,和/或TEOS淀积技术形成的二氧化硅。在形成氧化物以后,用内腐蚀或化学机械平面化技术,其组合,或其它技术,把电介质区的上表面平面化。在一个示例性实施方案中,槽106具约30μm到约100μm的宽度,并用类似于结合图2所叙述的形成槽122所用的方法。槽106的侧壁可以是基本垂直的,或者是有锥度的以使在槽106的底处的宽度小于槽106顶处的宽度。作为举例,电介质材料108和/或电介质层110延伸到半导体层14之下的一个深度或距离,如图11中所示。
在层23,24,26,27被包括在隔离槽103中的另选的实施方案中,在基片12内在槽106的下方被插入一个n-型区109,以减小与单元片(die)分离相联系的任何漏电流问题。
按照本发明,当半导体层14具有p-型导电性,对于BVdss的主要的方法是由半导体层14和n-型基片12所形成的pn结114。这个特征简化了边缘终端结构100,并节省了空间。例如,常规器件要求外延层厚度的1到3倍的距离用于终端结构。而在本发明中,该距离减小到外延层厚度的约1/2倍。
在该实施方案中,结114比起常规器件中的结要更加平,因为结从基片12向上耗尽,而不是向下和从体区31跨越耗尽。另外,因为导电接触层146通过掺杂区152和19被耦合至半导体层14,因而结114横向延伸至器件10的边缘。以这样的方式,一个具有优化BVdss的优化平面结得以实现。隔离槽103,除了起其它作用外,起了使结114钝化的作用。
图12给出按照本发明一个备选的隔离槽203的一张放大的顶视图,区域131表示器件10的这样的一个区,它用于结合着图11所叙述的终端结构,而区域132表示器件10的这样的一个区,它用作如在图1中所描述的有源结构。隔离槽203包括多个柱或形状117的阵列,它们在隔离槽被腐蚀时形成。在一个示例性实施方案中,形状117的相邻的行如图12所示那样互相偏移以使形状117相互基本上是等距离。在一个示例性的实施方案中柱117互相间隔约5μm到约15μm。
作为举例,形状117是半导体材料11的各个部分的柱或区域。在一个示例性实施方案中,形状117包含基片12,半导体层14,p-型层19,n-型层17和电介质层41,并具有约0.8μm到约1.0μm的宽度或直径。这在图13中被更清楚地显示出来,该图是图12沿着参照线13-13所取的一部分隔离槽203的一张放大的截面图。图13给出在电介质材料208形成之前的隔离槽203。常规的光刻和腐蚀技术被用来形成槽206和形状117。例如,用基于氟或氯的化学试剂的DRIE。
在槽206和形状117被形成以后,电介质层210被形成,如图14所示。作为举例,电介质层210包含一种热生长二氧化硅。接着淀积电介质层208并使之平面化。在一个示例性实施方案中,电介质层208包含一旋涂玻璃。按照本发明,形状117减小了当电介质层208被淀积时的中凹效应,它提供一个更加平的表面,更好的钝化,以及一更加可靠的器件。形状117可以是圆的,正方的,长方的,多边形的,梯形的,椭圆的,三角形的,其组合或其它等,该形状还可以包括圆角。
图15给出相邻的或多个隔离槽203a和203b的一张放大部分截面图,它被画成被一划痕网格或区461分开的两个器件的相应部分。在这个实施方案中,在一片半导体晶片上的相邻器件10包括划痕网格461,它包含半导体材料11,而不是电介质材料208和210在相邻单元片之间是连续的。这就允许一种单元片分割装置,诸如一个切割锯,沿着中心线463来把单元片分开,从而能牢固地进行单元片分割。
总之,已经描述了具有深槽电荷补偿的一种新的开关器件,包括一种制造方法。另外,已经描述了一种接地平面结构,它适合于本发明的器件,也适合于其它半导体器件。另外,已经叙述了适合于本发明的器件以及其它半导体器件的边缘终端结构。
虽然本发明已经参照本发明的具体的实施方案予以叙述和说明,但本发明并不限于这些说明性的实施方案。本领域的技术人员可以认识到,在不偏离本发明的精神下,可以作修改和变动。因而希望本发明把所有这种变动和修改都包括进所附权利要求的范围。
Claims (10)
1.一种半导体器件,包括:
具有一个边缘区的、具有第一导电类型的半导体基片;
在该半导体基片上形成的、具有第二导电类型的半导体层;
在邻近该边缘区的半导体层中形成的具有第二导电类型的第一掺杂区;
耦合至第一掺杂区的第一导电层;以及
在邻近第一掺杂区的半导体层中形成的隔离槽。
2.权利要求1的器件,其中隔离槽包括各个形状构成的一个阵列,所述各个形状构成的阵列包含半导体层的各区域。
3.权利要求1的器件,还包括在半导体层中形成的一电荷补偿区。
4.权利要求3的器件,其中电荷补偿区包括:
在半导体层中形成的一个槽;
在槽中形成的具有第一导电类型的一第一半导体层;
在第一半导体层上形成的一第一缓冲层;以及
在第一缓冲层上形成的具有第二导电类型的一第二半导体层。
5.一种半导体器件,包括:
具有一个边缘区的、具有第一导电类型的半导体基片;
在半导体基片上形成的、具有第二导电类型的半导体层;
在邻近该边缘区的半导体层中形成的具有第二导电类型的第一掺杂区;
耦合至第一掺杂区的第一导电层;
在邻近第一掺杂区的半导体层中形成的一个隔离区;
在半导体层中形成的一电荷补偿区;
在邻近电荷补偿区的半导体层中形成的具有第二导电类型的一第二掺杂区;
在第二掺杂区中形成的具有第一导电类型的一第三掺杂区;以及
在邻近第二和第三掺杂区形成的一控制电极。
6.权利要求5的器件,其中电荷补偿区包括
在半导体层中形成的一个槽;
在该槽中形成的具有第一导电类型的一第一半导体层;
在第一半导体层上形成的一第一本征层;以及
在第一本征层上形成的具有第二导电类型的一第二半导体层。
7.权利要求5的器件,还包括耦合至电荷补偿区的一第二导电层。
8.权利要求7的器件,还包括耦合至第三掺杂区的一个接触层,其中该接触层还耦合至第一和第二导电层。
9.形成一半导体器件的方法,包括如下步骤:
提供一有一个边缘区的、具有第一导电类型的半导体基片和在一主表面上形成的、具有第二导电类型的一半导体层;
在邻近该边缘区的半导体层中形成一具有第二导电类型的第一掺杂区;
形成耦合至第一掺杂区的第一导电层;以及
在邻近第一掺杂区形成的半导体层中形成一个隔离槽。
10.权利要求9的方法,还包括在半导体层中形成一电荷补偿区的步骤。
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TWI362747B (en) | 2012-04-21 |
TW200636992A (en) | 2006-10-16 |
US20060180857A1 (en) | 2006-08-17 |
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