CN1783045A - System and method for dynamically distributing device address on integrated circuit bus - Google Patents
System and method for dynamically distributing device address on integrated circuit bus Download PDFInfo
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- CN1783045A CN1783045A CN 200410077283 CN200410077283A CN1783045A CN 1783045 A CN1783045 A CN 1783045A CN 200410077283 CN200410077283 CN 200410077283 CN 200410077283 A CN200410077283 A CN 200410077283A CN 1783045 A CN1783045 A CN 1783045A
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Abstract
The system for dynamically allocating device address on integrated circuit bus includes one bus controlling and processing unit and several devices connected to the integrated circuit bus with one processing unit each. The bus controlling and processing unit is for generating several different new addresses, sending commands to the integrated circuit bus and allocating new address to device with preset address. Each of the processing units in the devices completes the following successive jobs: setting the address of device the unit is in as preset address, receiving from the integrated circuit bus one new address allocating command and determining the device address as the new address based on the command. The present invention also provides method of dynamically allocating device address. The present invention can expand the capacity of the integrated circuit bus and make the integrated circuit bus capable of connecting more device.
Description
[technical field]
The present invention relates to a kind of IC bus address allocation system and method, particularly a kind of I
2The address dynamic allocation system and the method for C bus apparatus.
[background technology]
The I of Philip
2C (Inter Integrated Circuit, I
2C) bus is because have the simplicity of plug and play two-wire interface, and its low implementation cost, the industrywide standard universal serial bus of become control in numerous electronic application, safeguarding and dispose.
Be connected I
2I on the C bus
2C equipment need be by I separately
2C address (I
2C SlaveAddress) could visit.Traditional I
2The address setting of C equipment is by each I
2Hardware on the circuit board of C equipment preestablishes.I
2The C bus defines an I
2C equipment is only to set an I
2C address, and I
2The setting range of C address is 00-FF.For example, most of I
2(Electrically ErasableProgrammable Read Only Memory EEROM) only has three rubber pins (Strapping Pin) to the erasable programmable read-only memory of the electronics that the C bus can be visited, and has limited the I of these EEROM like this
2C address setting scope is A0-AF (only to be even address), therefore is merely able to have 8 EEROM equipment to be connected to an I at most
2The C bus.
Therefore, be necessary to provide a kind of employing dynamical fashion to set I
2The method of C device address, thus I can be expanded
2The capacity of C bus.
[summary of the invention]
Fundamental purpose of the present invention is to provide a kind of dynamic assignment IC bus (I for example
2The system of the device address the C bus), the capacity that it can expand IC bus makes can connect more equipment on the IC bus.
Another purpose of the present invention is to provide a kind of dynamic assignment IC bus (I for example
2The method of the device address the C bus), the capacity that it can expand IC bus makes can connect more equipment on the IC bus.
For realizing fundamental purpose of the present invention, technical scheme provided by the invention is as follows:
The system of the device address on a kind of dynamic assignment IC bus comprises a bus master processing unit and a plurality of equipment that is connected on the described IC bus, and each equipment comprises a processing unit.Wherein said bus master processing unit is used for: produce a plurality of new addresses that have nothing in common with each other; Sending order on above-mentioned IC bus, is the equipment of a presumptive address to the current address with the new address assignment that produces.The processing unit that wherein is connected one first equipment on the said integrated circuit bus is carried out following operation one by one: the address setting of corresponding device is described presumptive address separately; Receiving a new address assignment from the said integrated circuit bus is the order of the equipment of above-mentioned presumptive address to the current address, and is this new address according to received order with the address setting of this equipment.
Wherein said IC bus is I
2The C bus.
The processing unit that wherein is connected each equipment on the said integrated circuit bus is also carried out following operation: but set separately corresponding device is address set condition or be set at can not set condition.
For realizing another object of the present invention, technical scheme provided by the invention is as follows:
The method of the device address on a kind of dynamic assignment IC bus, its improvement be, it is that the address can not set condition that this method comprises the steps: to set all devices that is connected on the described IC bus; One bus master processing unit constantly sends the address assignment order to above-mentioned IC bus: the address setting that with the address is the equipment of a presumptive address is a new address; But one first equipment that setting is connected on the described IC bus is the address set condition; The address of setting described first equipment is a presumptive address; Receive and carry out an address assignment order from the said integrated circuit bus: the address of setting described first equipment is one first address, and wherein this first address is different from described presumptive address; But one second equipment that setting is connected on the described IC bus is the address set condition; The address of setting described second equipment is described presumptive address; Receive and carry out an address assignment order from the said integrated circuit bus: the address of setting described second equipment is one second address, and wherein this second address is different from described presumptive address, and this second address is different from described first address.
Wherein said IC bus is I
2The C bus.
This method can also comprise: but set a miscellaneous equipment that is connected on the described IC bus is the address set condition; The address of setting this miscellaneous equipment is described presumptive address; Receive and carry out an address assignment order from the said integrated circuit bus: the address setting that with the address is the equipment of above-mentioned presumptive address is a new address.
Utilize dynamic assignment IC bus provided by the invention (I for example
2The system and method for the device address the C bus) can adopt dynamical fashion to distribute more address, thereby can expand the capacity of IC bus, makes can connect more equipment on the IC bus.
[description of drawings]
Fig. 1 is I of the present invention
2The hardware structure figure of C bus address dynamic allocation system.
Fig. 2 is I
2The processing unit of C equipment is carried out method flow diagram of the present invention.
Fig. 3 is I
2C bus master processing unit is carried out method flow diagram of the present invention.
[embodiment]
As shown in Figure 1, be I of the present invention
2The hardware structure figure of C bus address dynamic allocation system.Dynamic assignment I of the present invention
2C (Inter Integrated Circuit, I
2C) system 100 of the device address on the bus comprises an I
2C bus driver device 110 (I
2C Bus Driver) and a plurality of I
2C equipment (I
2C Slave Device) (130,140,150) are connected an I one by one with series system
2On the C bus 120.
Described I
2C bus driver device 110 comprises a bus master processing unit 111, and this bus master processing unit 111 is used for: produce a plurality of new addresses that have nothing in common with each other; To above-mentioned I
2Sending on the C bus and ordering the new address assignment that will produce is the I of a presumptive address S to the current address
2C equipment.
Each I
2C equipment comprises a processing unit (131,141,151), and described processing unit (131,141,151) will be carried out following operation one by one: the address setting of corresponding device is described presumptive address separately; From above-mentioned I
2Receiving on the C bus 120 a new address assignment is the order of the equipment of above-mentioned presumptive address to the current address, and is this new address according to received order with the address setting of this equipment.In embodiments of the present invention, at first will be by being connected described I
2I on the C bus 120
2The processing unit 131 of C equipment 130 is carried out above-mentioned operation, the 2nd I after processing unit 131 complete above-mentioned All Jobs
2C equipment 140 could be carried out, the 3rd I after processing unit 141 complete above-mentioned All Jobs
2C equipment 150 could be carried out.
A plurality of I of the present invention
2Also connect between the C equipment, therefore at last I by an electrical cable 160 (can be common wiring, also can be other transmission line that can transmit electric signal) that can transmit electric signal
2The output terminal of C equipment with the back one I
2The current potential of the input end of C equipment is identical, for example, and I
2The output terminal a and the I of C equipment 130
2The input end b current potential of C equipment 140 is identical, I
2The output terminal b and the I of C equipment 140
2The input end c current potential of C equipment 150 is identical.In embodiments of the present invention, described bus master processing unit 111 will be given an order one by one for being connected I
2I on the C bus 120
2C equipment (130,140,150) distributes new address inequality.
Before being assigned with the address, all I
2The processing unit of C equipment (131,141,151) control power source voltage Vcc is at output terminal output electronegative potential separately, and whether constantly detect input end then is noble potential.If I
2It is noble potential that the processing unit of C equipment does not detect input end, this I
2C equipment is in the address can not set condition; In case detect input end is noble potential, then I
2But C equipment is in the address set condition, at this moment I
2The processing unit of C equipment is a presumptive address S with address setting earlier, waits for from I
2It is the order of a new address that C bus 120 receives address setting, and according to ordering this I
2The address setting of C equipment is a new address.Set after the new address, processing unit control Vcc exports noble potential with output terminal.
For being connected I
2I after the C drive unit 110
2C equipment 130, Vcc are controlled its input end a and are kept noble potential, so I
2C equipment 130 will be prior to other I
2C equipment (140,150) is assigned with the address.Processing unit 131 is at first controlled power source voltage Vcc with its output terminal a output electronegative potential, detects input end a and is after the noble potential, with I
2C equipment 130 address settings are described presumptive address S.
Described bus master processing unit 111 is to I
2Send the address assignment order on the C bus: with present address is the I of S
2The address setting of C equipment is one first new address X1, and wherein X1 and S are inequality.
Because I
2C equipment 130 present addresses are S, so its processing unit 131 can be from I
2The C bus interface receives orders, and with I
2C equipment 130 address settings are X1, afterwards with its output terminal a output noble potential.
Because I
2The input end b and the I of C equipment 140
2The output terminal a of C equipment 130 has same potential, and therefore, this moment, input end b was a noble potential.I
2The processing unit 141 of C equipment 140 detects after input end b is noble potential, with I
2The address setting of C equipment 140 is described presumptive address S.Because I
2C equipment 140 present addresses are S, so its processing unit 141 can be from I
2The C bus interface is received the address assignment order, and with I
2The address setting of C equipment 140 is one second new address X2.X1 wherein, X2 and S have nothing in common with each other.Repeating above step can be with I
2The address setting of C equipment 150 is one and X1, the new address that X2 and S have nothing in common with each other.
The embodiment of the invention has only three I
2C equipment (130,140,150) is connected I
2On the C bus 120, so bus master processing unit 111 is only to these three I
2The address that C equipment dynamic assignment has nothing in common with each other.In other embodiments, be connected I
2I on the C bus 120
2The quantity of C equipment can increase.
Below in conjunction with Fig. 2 and Fig. 3, introduce 111 pairs of bus master processing units in detail and be connected I
2I on the C bus
2C equipment (130,140,150) dynamic assignment the have nothing in common with each other method and the detailed process of address.
As shown in Figure 2, be I
2The processing unit of C equipment is carried out method flow diagram of the present invention.At first, be connected I
2All I on the C bus 120
2The processing unit (131,141,151) of C equipment (130,140,150) is controlled its Vcc separately at output terminal (output terminal a, output terminal b, output terminal c) output electronegative potential (step S210).Each I
2The processing unit of C equipment is finished after the aforesaid operations separately, postpones a period of time, for example 10 milliseconds (step S220).Can determine all I after waiting for 10 milliseconds
2The operation of C equipment completing steps S210.Then, all processing units (131,141,151) will detect constantly separately whether input end is noble potential (step S230).In case it is noble potential that wherein a certain processing unit detects its input end, then this processing unit is a presumptive address S (step S240) with address setting.
In embodiments of the present invention, for being connected I
2I after the C drive unit 110
2C equipment 130, Vcc are controlled its input end a and are kept noble potential, so I
2C equipment 130 will be prior to other I
2C equipment (140,150) is assigned with the address.
Therefore, I
2It is noble potential that the processing unit 131 of C equipment 130 at first detects its input end a, with I
2The address setting of C equipment 130 is described presumptive address S (step S240).Whether other processing unit (141,151) is high voltage (step S230) constantly detecting its input end (input end b, input end c) still.
Through after the above-mentioned series of steps, I
2The current address of C equipment 130 is S, and its processing unit 131 is waited for from I
2Receive the address assignment order that bus master processing unit 111 sends on the C bus 120: the address setting that with the address is the equipment of S is X.
For bus master processing unit 111 to I
2Sending the process of address dynamic assignment order on the C bus 120, as shown in Figure 3, is I
2C bus master processing unit is carried out method flow diagram of the present invention.Bus master processing unit 111 distributes before the address, at first postpones to wait for one sufficiently long period, and the time of this delay should be longer than an I before
210 milliseconds of the times that is postponed after the C equipment 130 completing steps S210, for example 20 milliseconds (step S310).All parameters that need use when dynamically allocate address of initialization are for example set and are connected I
2I on the C bus 120
2C equipment sum N, an I is given in planned assignment
2The address A of C equipment, and set an accumulation factor B=0 (step S320), this accumulation factor B represents that bus master processing unit 111 has sent the quantity of address assignment order, just has been assigned to the I of address
2The quantity of C equipment.In the embodiment of the invention, set N=3, A=10h.Because presumptive address S of the present invention can be an arbitrary value, sets above-mentioned presumptive address S=60h in an embodiment.
Finish after the parameter initialization setting, bus master processing unit 111 judges that whether B is less than N (step S330).Because just finished initializing set N=3 and B=0 this moment, therefore directly enter next step: make X=A+B, then this moment X=10h (step S340).Subsequently, bus master processing unit 111 is to I
2Send order on the C bus 120: with the address is that the device address of S is set at X (step S350).Because this moment, the address was that the equipment of S is to be connected I
2I after the C drive unit 110
2C equipment 130, its this moment the address be S=60h.
Afterwards, I
2The processing unit 131 of C equipment 130 is from I
2C bus 120 receives order (step S250), with I
2The address setting of C equipment 130 is X=10h (step S260), controls its Vcc at last with its output terminal a output noble potential (step S270).So far, finish I
2The address dynamic assignment of C equipment 130, its addresses distributed are 10h.To finish subsequently I
2The address assignment of C equipment 140.
Because I
2C equipment 130 in step S270 with its output terminal a output noble potential, therefore, this moment I
2The input port b of C equipment 140 also is a noble potential.I
2The processing unit 141 of C equipment 140 detect input port b be noble potential (step S230) afterwards, with I
2The address setting of C equipment 140 is presumptive address S, promptly is 60h (step S240).
Because bus master processing unit 111 is I sending order
2After the C equipment 130 distribution address X=10h (step S350), accumulation factor B=B+1 (step S360).After the completing steps 360, B=1.In order to guarantee I
2C equipment 140 has grace time to finish the step of synchronous coordination, and bus master processing unit 111 postpones to wait for 20 milliseconds (step S370) afterwards, judges whether that B is less than N (step S330).Owing to this moment B=1 and N=3, then B forwards next step to less than N, makes X=A+B (step S340).Because this moment, A=10h and B=1 then passed through after the step S340 X=11h.
Bus master processing unit 111 is for the second time to I
2C bus 120 sends the address assignment orders: with the address is that the device address of S is set at X (step S350).Because this moment I
2The address of C equipment 140 is S=60h, so I
2The processing unit of C equipment 140 can be from I
2C bus 120 receives this order (step S250), with I
2The address setting of C equipment 140 is X (step S260), controls Vcc at last with its output terminal b output noble potential (step S270).Because this moment X=11h, so so far, finished I
2The address dynamic assignment of C equipment 140, I
2140 addresses distributed of C equipment are 11h.According to above-mentioned method and flow process operation, can finish I
2The address assignment of C equipment 150, I
2150 addresses distributed of C equipment are 12h.
Bus master processing unit 111 is finished after three dynamically allocate address operations, these three I
2The address that C equipment is assigned to is respectively 10h, 11h, 12h.
In other embodiments of the invention, can suitably change each parameter wherein, but must meet following condition: guarantee that described presumptive address S finally is not assigned to a certain I
2C equipment.Can be for one of ordinary skill in the art without creative work, the selected parameter that meets above-mentioned condition is implemented the present invention.
I
2The C bus is a kind of IC bus, so the equipment that thought of the present invention can apply to other IC bus carries out dynamic address allocation.
Claims (12)
1. the system of the device address on the dynamic assignment IC bus is characterized in that this system comprises a bus master processing unit and a plurality of equipment that is connected on the described IC bus, and each equipment comprises a processing unit, wherein:
Described bus master processing unit is used for: produce a plurality of new addresses that have nothing in common with each other; Sending order on above-mentioned IC bus, is the equipment of a presumptive address to the current address with the new address assignment that produces;
The described processing unit that is connected a plurality of equipment on the IC bus is carried out following operation one by one: the address setting of corresponding device is described presumptive address separately; Receiving a new address assignment from the said integrated circuit bus is the order of the equipment of above-mentioned presumptive address to the current address, and is this new address according to received order with the address setting of this equipment.
2. the system of the device address on the dynamic assignment IC bus as claimed in claim 1 is characterized in that, wherein said IC bus is I
2C (InterIntegrated Circuit) bus.
3. the system of the device address on the dynamic assignment IC bus as claimed in claim 1, it is characterized in that the processing unit that wherein is connected each equipment on the said integrated circuit bus is also carried out following operation: corresponding device is the address set condition but set separately.
4. the system of the device address on the dynamic assignment IC bus as claimed in claim 1, it is characterized in that the processing unit that wherein is connected each equipment on the said integrated circuit bus is also carried out following operation: setting separately, corresponding device is that the address can not set condition.
5. the system of the device address on the dynamic assignment IC bus as claimed in claim 1 is characterized in that, wherein said a plurality of equipment are connected on the described IC bus.
6. as the system of the device address on claim 1 or the 5 described dynamic assignment IC bus, it is characterized in that, wherein " processing unit that is connected a plurality of equipment on the said integrated circuit bus is carried out following operation one by one " is meant: after the complete described following operation of the processing unit of the last equipment on being connected the said integrated circuit bus, thereafter the processing unit of an equipment could be carried out described following operation, up to the complete described following operation of all devices.
7. the method for the device address on the dynamic assignment IC bus is characterized in that this method comprises:
It is that the address can not set condition that setting is connected all devices on the described IC bus;
One bus master processing unit constantly sends the address assignment order to above-mentioned IC bus: the address setting that with the address is the equipment of a presumptive address is a new address;
But one first equipment that setting is connected on the described IC bus is the address set condition;
The address of setting described first equipment is a presumptive address;
Receive and carry out an address assignment order from the said integrated circuit bus: the address of setting described first equipment is one first address, and wherein this first address is different from described presumptive address;
But one second equipment that setting is connected on the described IC bus is the address set condition;
The address of setting described second equipment is described presumptive address;
Receive and carry out an address assignment order from the said integrated circuit bus: the address of setting described second equipment is one second address, and wherein this second address is different from described presumptive address, and this second address is different from described first address.
8. the method for the device address on the dynamic assignment IC bus as claimed in claim 7 is characterized in that, wherein said IC bus is I
2C (InterIntegrated Circuit) bus.
9. as the method for the device address on claim 7 or the 8 described dynamic assignment IC bus, it is characterized in that each equipment that wherein is connected on the described IC bus comprises a processing unit, is used to set the address of its equipment.
10. as the method for the device address on claim 7 or the 8 described dynamic assignment IC bus, it is characterized in that each equipment that wherein is connected on the described IC bus comprises a processing unit, is the address set condition but be used to set its equipment.
11. method as the device address on claim 7 or the 8 described dynamic assignment IC bus, it is characterized in that, each equipment that wherein is connected on the described IC bus comprises a processing unit, and being used to set its equipment is that the address can not set condition.
12. the method as the device address on claim 7 or the 8 described dynamic assignment IC bus is characterized in that this method also comprises:
But the miscellaneous equipment that setting is connected on the described IC bus is the address set condition;
The address of setting this miscellaneous equipment is described presumptive address;
Receive and carry out an address assignment order from the said integrated circuit bus: the address setting that with the address is the equipment of above-mentioned presumptive address is a new address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100772836A CN100383771C (en) | 2004-12-04 | 2004-12-04 | System and method for dynamically distributing device address on integrated circuit bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100772836A CN100383771C (en) | 2004-12-04 | 2004-12-04 | System and method for dynamically distributing device address on integrated circuit bus |
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| Publication Number | Publication Date |
|---|---|
| CN1783045A true CN1783045A (en) | 2006-06-07 |
| CN100383771C CN100383771C (en) | 2008-04-23 |
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ID=36773251
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100772836A Expired - Fee Related CN100383771C (en) | 2004-12-04 | 2004-12-04 | System and method for dynamically distributing device address on integrated circuit bus |
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| CN (1) | CN100383771C (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101685433B (en) * | 2008-09-23 | 2011-10-05 | 祥采科技股份有限公司 | Serial bus unit assigned address by primary device |
| CN102498444A (en) * | 2009-07-27 | 2012-06-13 | 齐尔-阿贝格股份公司 | Device and method for addressing a slave unit |
| CN101610192B (en) * | 2008-06-18 | 2012-06-27 | 华为技术有限公司 | Communication slave, bus cascading method and system |
| CN102609381A (en) * | 2012-02-03 | 2012-07-25 | 华为技术有限公司 | Single board, communication system and method for distributing independent addresses for devices |
| CN103676901A (en) * | 2013-12-23 | 2014-03-26 | 北京易艾斯德科技有限公司 | Control system for automatically identifying data communication address |
| CN104899164A (en) * | 2014-03-04 | 2015-09-09 | 瑞萨集成电路设计(北京)有限公司 | Address addressing method for integrated circuit bus and integrated circuit bus equipment and system |
| CN104899177A (en) * | 2015-06-30 | 2015-09-09 | 深圳市兰丁科技有限公司 | I2C (inter-integrated circuit) equipment control method and system |
| CN106445857A (en) * | 2015-08-12 | 2017-02-22 | 西门子公司 | Master-slave system, configuration method of bus address in master-slave system, and slaves |
| CN106547713A (en) * | 2015-09-18 | 2017-03-29 | 华为技术有限公司 | A kind of method and apparatus of distribution address |
| CN110083570A (en) * | 2019-04-16 | 2019-08-02 | 深圳市致宸信息科技有限公司 | A kind of multi-chip series connection automatic address coded system and method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1005436B (en) * | 1984-05-22 | 1989-10-11 | 北方电信有限公司 | Bus arrangement for a digital television system |
| JPH09179810A (en) * | 1995-12-25 | 1997-07-11 | Matsushita Electric Works Ltd | Unit selecting device |
| US6629172B1 (en) * | 1998-12-14 | 2003-09-30 | Micron Technology, Inc. | Multi-chip addressing for the I2C bus |
| US6745270B1 (en) * | 2001-01-31 | 2004-06-01 | International Business Machines Corporation | Dynamically allocating I2C addresses using self bus switching device |
| US6996644B2 (en) * | 2001-06-06 | 2006-02-07 | Conexant Systems, Inc. | Apparatus and methods for initializing integrated circuit addresses |
| CN1267828C (en) * | 2003-04-01 | 2006-08-02 | 智邦科技股份有限公司 | Electron system using bus between integrated circuits as interface and its data transmission method |
-
2004
- 2004-12-04 CN CNB2004100772836A patent/CN100383771C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101610192B (en) * | 2008-06-18 | 2012-06-27 | 华为技术有限公司 | Communication slave, bus cascading method and system |
| CN101685433B (en) * | 2008-09-23 | 2011-10-05 | 祥采科技股份有限公司 | Serial bus unit assigned address by primary device |
| TWI507835B (en) * | 2009-07-27 | 2015-11-11 | Ziehl Abegg Ag | Slave unit, master unit, and slave unit addressing method |
| CN102498444A (en) * | 2009-07-27 | 2012-06-13 | 齐尔-阿贝格股份公司 | Device and method for addressing a slave unit |
| CN102498444B (en) * | 2009-07-27 | 2014-05-28 | 齐尔-阿贝格股份公司 | Device and method for addressing a slave unit |
| CN102609381A (en) * | 2012-02-03 | 2012-07-25 | 华为技术有限公司 | Single board, communication system and method for distributing independent addresses for devices |
| CN103676901A (en) * | 2013-12-23 | 2014-03-26 | 北京易艾斯德科技有限公司 | Control system for automatically identifying data communication address |
| CN104899164A (en) * | 2014-03-04 | 2015-09-09 | 瑞萨集成电路设计(北京)有限公司 | Address addressing method for integrated circuit bus and integrated circuit bus equipment and system |
| CN104899164B (en) * | 2014-03-04 | 2023-05-30 | 瑞萨集成电路设计(北京)有限公司 | Address addressing method for integrated circuit bus, integrated circuit bus device and system |
| CN104899177A (en) * | 2015-06-30 | 2015-09-09 | 深圳市兰丁科技有限公司 | I2C (inter-integrated circuit) equipment control method and system |
| CN104899177B (en) * | 2015-06-30 | 2018-03-16 | 深圳市兰丁科技有限公司 | A kind of I2C apparatus control methods and system |
| CN106445857A (en) * | 2015-08-12 | 2017-02-22 | 西门子公司 | Master-slave system, configuration method of bus address in master-slave system, and slaves |
| CN106547713A (en) * | 2015-09-18 | 2017-03-29 | 华为技术有限公司 | A kind of method and apparatus of distribution address |
| CN106547713B (en) * | 2015-09-18 | 2020-06-16 | 华为技术有限公司 | Address allocation method and device |
| CN110083570A (en) * | 2019-04-16 | 2019-08-02 | 深圳市致宸信息科技有限公司 | A kind of multi-chip series connection automatic address coded system and method |
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|---|---|
| CN100383771C (en) | 2008-04-23 |
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