CN101610192B - Communication slave, bus cascading method and system - Google Patents
Communication slave, bus cascading method and system Download PDFInfo
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Abstract
The embodiment of the invention discloses a communication slave, a bus cascading method and a bus cascading system. When the cascading hierarchy has two levels, the bus cascading system comprises a communication host, a first communication slave connected with the communication host, and a second communication slave connected with the first communication slave. The method comprises that: the first communication slave receives a level signal of the communication host, which is opposite to the level defaulted by the first communication slave self; and the first communication slave changes self defaulted level state according to the received level signal, and changes self defaulted logical address. By adopting the embodiment of the invention to carry out logical address register on the communication host, the communication host does not need to increase a communication port to connect the communication slave, and the communication slave can determine self logical address so as to realize logical address register and identification.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a communication slave, a bus cascading method and a bus cascading system.
Background
Currently, in a bus system for communication exchange, a serial bus physical layer standard RS485, a Peripheral Component Interconnect (PCI), an ethernet, and the like are commonly used. The bus devices share a communication line, so that the cost is low, the reliability is high, and the devices on the bus need to use the bus in a time-sharing manner. The most commonly used bus is controlled by a communication host, the bus is connected with a plurality of communication slaves, and the communication host is reserved with enough physical interfaces so as to support the access of N communication slaves at most, but the communication host is huge in size and increased in manufacturing cost.
Fig. 1 is a conventional bus connection method, in which a "communication extension unit" is additionally added to a bus, and the "communication extension unit" can be connected to M communication slave machines and is responsible for managing communication between "N +1, N +2, ·.
Because the communication slave cannot directly communicate with the communication host, cannot know the own logical address, and needs to determine the own logical address in an automatic or artificial IP address specifying mode, the communication slave needs to rely on a communication extension unit to process a complex routing protocol message and control protocol conversion between devices.
In the process of implementing the present invention, the inventor finds that the technology of implementing port expansion by using a "communication expansion unit" has the following disadvantages:
the communication extension unit has complex hardware and low reliability, and can realize the logical address registration of the communication slave machine only by adopting a complex bus management algorithm.
Disclosure of Invention
The embodiment of the invention provides a communication slave machine, a bus cascade method and a system, wherein a communication port is not required to be added to a communication master machine to connect the communication slave machine, the communication slave machines are mutually cascaded through uplink and downlink physical interfaces, and the logical address registration and identification can be realized.
The embodiment of the invention provides a bus cascading method, when the hierarchy of the cascading is two levels, the bus cascading method comprises a communication host, a first communication slave connected with the communication host and a second communication slave connected with the first communication slave, and the method comprises the following steps:
the first communication slave machine receives a level signal of the communication master machine, wherein the level signal is opposite to the level of the first communication slave machine default;
and the first communication slave machine changes the self-default level state according to the received level signal, changes the self-default logic address and registers the logic address on the communication host machine.
The embodiment of the invention also provides a bus cascading method, which comprises the following steps:
receiving a level signal of a communication host, and changing the self-default level;
determining a logic address of the communication host according to the broadcast signal of the communication host, and registering the logic address on the communication host according to the logic address;
receiving a level signal output by the communication slave machine, and changing the default level of the communication slave machine;
and determining a logic address of the communication host according to the broadcast signal of the communication host, and registering the logic address on the communication host according to the logic address.
Embodiments of the present invention also provide a communications slave comprising a central processing unit and input logic, wherein,
the input logic is used for being connected with a communication host or being connected with the output logic of another communication slave and receiving the level signal of the communication host or the level signal of the output logic of the another communication slave;
and the central processing unit is used for determining the logic address of the communication slave according to the level signal of the input logic and registering the logic address of the communication slave according to the logic address.
The embodiment of the invention also comprises a communication slave which comprises input logic, a central processing unit and a bus transceiver, wherein,
the input logic is used for being connected with a communication host or being connected with the output logic of another communication slave and receiving the level signal of the communication host or the level signal of the output logic of the another communication slave;
the bus transceiver is used for receiving broadcast signals from the communication host;
and the central processing unit is used for determining the logic address of the communication slave machine according to the broadcast signal and registering the logic address of the communication slave machine according to the logic address.
Still further, an embodiment of the present invention provides a bus cascade system, including a communication master, a first communication slave and a second communication slave, where the level and logical address of the first communication slave and the second communication slave are the same by default, and the level of the first communication slave and the second communication slave are opposite to the level of the communication master, and the output logic of the first communication slave is logically connected to the input logic of the second communication slave, where:
the communication master machine is connected with the input logic of the first communication slave machine;
the first communication slave is used for receiving a level signal of the communication host, wherein the level signal is opposite to a default level, and under the control of the level signal, the first communication slave changes the default level of the first communication slave, changes the default logical address of the first communication slave, and registers the logical address on the communication host.
The embodiment of the invention also provides a bus cascade system, which comprises at least three communication slave machines and a communication host machine, wherein:
the communication master machine is in input logic connection with one of the at least three communication slave machines and sends broadcast signals to the at least three communication slave machines;
the input logic of one communication slave machine of the other two communication slave machines is connected with the output logic of one communication slave machine connected with the communication master machine, and the input logic of the other communication slave machine of the other two communication slave machines is connected with the output logic of one communication slave machine of the other two communication slave machines;
the communication host sends broadcast signals to the at least three communication slave machines, the at least three communication slave machines determine own logic addresses according to level signals received by own input logics and the broadcast signals, and perform logic address registration on the communication host according to the own logic addresses.
The embodiment of the invention has the following beneficial effects:
the level and the logic address of the communication slave are same in default, and when a level signal is received, the level of the communication slave is changed to determine the logic address of the communication slave; or the level of the host computer is changed, and the logical address registration is carried out on the host computer according to the broadcast signal of the communication host computer, thereby avoiding the problem of adopting complex bus management algorithm and protocol conversion to realize the logical address registration, and further providing the interconnection communication with high reliability and low cost.
Drawings
FIG. 1 is a schematic diagram of a connection method of a bus device using a communication expansion unit to implement port expansion in the prior art;
fig. 2 is a schematic structural diagram of a first embodiment of a bus concatenation system according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a second embodiment of a bus concatenation system according to the embodiment of the present invention;
fig. 4 is a schematic structural diagram of a bus cascade system according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of a fourth embodiment of a bus concatenation system according to the embodiment of the present invention;
fig. 6 is a schematic structural diagram of a fifth embodiment of a bus concatenation system according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a first embodiment of a communication slave according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a second embodiment of a communication slave according to an embodiment of the present invention;
FIG. 9 is a flowchart illustrating a first embodiment of a bus concatenation method according to an embodiment of the present invention;
FIG. 10 is a flowchart illustrating a second embodiment of a bus concatenation method according to an embodiment of the present invention;
FIG. 11 is a flowchart illustrating a bus concatenation method according to a third embodiment of the present invention;
FIG. 12 is a flowchart illustrating a bus concatenation method according to a fourth embodiment of the present invention;
fig. 13 is a flowchart illustrating a fifth embodiment of a bus concatenation method according to an embodiment of the present invention.
Detailed Description
Referring to fig. 2, a schematic structural diagram of a first embodiment of a bus concatenation system according to an embodiment of the present invention is provided.
The bus cascade system includes a communication master 100 and a communication slave.
As shown in fig. 2, the bus cascade system provided in the embodiment of the present invention includes:
the communication master machine 100 is used for connecting communication slave machines, and as shown in fig. 2, the communication slave machine 1, the communication slave machine 2.
Specifically, the communication master 100 includes an interface 001, an interface 002, an interface 00N, the communication slave 1 includes an interface 10, the interface 10 includes an input logic 12 and an output logic 13, the input logic 12 of the communication slave 1 is connected with the interface 001 of the communication master 100 through a bus, wherein the communication slave 2, the communication slave 3, and the communication slave N are the same as the interfaces of the communication slave 1, and will not be repeated here. The communication slave machine N +1 and the communication slave machine N +2. The value range of m is that m is more than or equal to 1, and the value range of N is that N is more than or equal to 1.
And the input logic (N +1)2 of the communication slave machine N +1 is connected with the output logic 13 of the communication slave machine 1, so that the communication slave machine N +1 and the communication slave machine 1 are connected through a bus.
Further, the communication host 100 provides N physical interfaces (N ≧ 1), such as the physical interfaces 001, 002.. N shown in fig. 2; the communication slave 1 may also have one physical interface 10, which is used to connect with one physical interface 001 of the communication master 100 to implement the connection of the input logic 12 of the communication slave 1 with the communication master 100 through a bus, and the communication slave (N +1) may also have one physical interface (N +1)0, which is used to connect with the physical interface 10 of the communication slave 1 to implement the connection of the input logic (N +1)2 of the communication slave (N +1) with the communication slave 1 through a bus; when the physical interfaces of all the communication slaves are implemented in detail, the physical interfaces can be further divided into an uplink physical interface 101 and a downlink physical interface 102.
Furthermore, when only two communication slave machines are connected with each other on one physical interface of the communication master machine, the input logic of one communication slave machine is connected with the communication master machine through a bus, and the output logic of the communication slave machine is connected with the input logic of the second communication slave machine through the bus; the logical addresses of the two communication slaves are the same in default, for example, both are logical 0 or logical 1, and when the input logic of the first communication slave connected to the communication master receives the level signal from the communication master, the logical address of the first communication slave is opposite to the default logical address, for example, the logical address 1 is changed to the logical address 0, or the logical address 0 is changed to the logical address 1, while the logical address of the second communication slave remains unchanged.
When three or more communication slave machines are connected with each other on one physical interface of the communication master machine and one communication slave machine is connected with the communication master machine through a bus, the logic addresses of the communication slave machines are the same by default. When the input logic of the communication slave receives the level signal, the level of the communication slave changes under the control of the level signal of the communication master or the communication slave connected with the input logic of the communication master, and when the level of the communication slave changes, the communication master sends a broadcast signal to the communication master to indicate the communication slave to perform logic address registration. The communication slave selects a logic address which is not registered as a logic address of the communication slave according to the broadcast signal, and performs logic address registration on the communication host by using the logic address; or, the broadcast signal carries a logical address allocated by the communication master to the communication slave, and the communication slave is instructed to register the logical address according to the logical address, where it should be noted that the logical address allocated by the communication master to each communication slave is different, but the logical address of one communication slave may be allowed to be the same as the default logical address.
By adopting the bus cascade system provided by the embodiment of the invention, the connection relation between the communication slave machines is a simple physical connection relation, the reliability is high, and the logic control and the logic address registration are easy to realize.
Referring to fig. 3, a schematic structural diagram of a second embodiment of a bus concatenation system according to the embodiment of the present invention is provided.
As shown in fig. 3, the bus cascade system provided in the embodiment of the present invention has a cascade hierarchy of 2 levels, that is, the bus cascade system includes a communication master 100, a communication slave 1, and a communication slave 2, wherein the input logic 22 of the communication slave 2 is connected to the output logic 13 of the communication slave 1, and the communication slave 1 is connected to the communication master 100 through a bus. Here, the communication slave 1 is a front stage of the communication slave 2, the communication slave 2 is a rear stage of the communication slave 1, and as can be seen from fig. 3, the communication slave has 2 stages, and such a cascade system is referred to as a bus cascade having a cascade hierarchy of 2 stages. The level and the logic address of the communication slave 1 and the communication slave 2 are the same by default, and the level of the communication slave 1 and the level of the communication slave 2 are opposite to the level state of the communication master 100.
The communication slave 1 is configured to receive a level signal of the communication master 100, the level signal being opposite to a default level, and under the control of the level signal, the communication slave 1 changes its default level and changes its default logical address, and performs logical address registration on the communication master 100
The communication slave 1 includes a central processing unit 11 and an input logic 12.
The input logic 12 of the communication slave 1 is connected with the communication master 100 through a bus, and the grounding end 1000 of the communication master 100 is grounded;
the central processing unit 11 is configured to determine a logical address of the communication slave 1 according to the level signal of the input logic 12, and register the logical address of the communication slave 1 according to the logical address.
Further, the communication slave 1 also comprises an output logic 13, and the output logic 13 is connected with an input logic 22 of the communication slave 2.
Further, the communication slave 1 further comprises a logic driver 14, wherein the logic driver 14 is connected to the input logic 12 and the output logic 13, and is configured to be controlled by a level signal to drive the input logic 12 and the output logic 13 to output corresponding level signals. In a specific implementation, the logic driver 14 may be a single logic driver connected to the input logic 12 and the output logic 13, or two logic drivers connected to the input logic 12 and the output logic 13, respectively.
The input logic 12 may be Rdyin input logic. The output logic 13 may be Rdyout output logic.
The central processor 11 includes an address determining module 110 and an address registering module 111.
The address determining module 110 is configured to determine a logic address of the communication slave 1 according to the level signal input by the input logic 12;
the address registration module 111 is configured to perform logical address registration on the communication slave 1 according to the logical address.
The structure and function of the communication slave 2 are the same as those of the communication slave 1, and are not described in detail herein.
In this case, when the communication slave 1 is connected to the communication slave 2 and the communication master 100 via the bus, the same physical interface 10 may be used, and in practical applications, the physical interface 10 may be divided into an uplink physical interface 101 and a downlink physical interface 102, and the communication slave 1 is connected to the physical interface 001 of the communication master 100 via the uplink physical interface 101 and is connected to the physical interface 20 of the communication slave 2 via the downlink physical interface 102.
Specifically, when the communication slave 1 connected to the communication master 100 receives a low level signal from the communication master 100 (because the ground terminal 1000 of the communication master 100 is grounded, the communication master 100 outputs a low level signal to the communication slave 1), the logic driver 14 of the communication slave 1 drives the input logic 12 to input a low level signal, the address determination module 110 of the cpu 11 of the communication slave 1 determines that the logic address of the communication slave 1 is opposite to the default logic address according to the low level signal input by the input logic 12, for example, the logic address is changed from the logic address 1 to the logic address 0, the logical address registration module 111 registers the logical address of the communication slave 1 according to the logical address 0. Then, the output logic 13 of the communication slave 1 outputs a high level signal to the communication slave 2, and the input logic 22 of the communication slave 2 receives the high level signal, and the logic address 1 is maintained unchanged if the level of the high level signal is not changed.
The logical address registration of the communication slaves of the level 2 cascade connected to other physical interfaces of the communication master 100 is the same, and is not described herein again.
The embodiment of the invention takes the RS485 asynchronous serial communication bus as an example to explain the embodiment of the invention, and the embodiment of the invention can also be applied to the technical fields such as PCI, Ethernet and the like.
The level signal output from the output logic 13 (i.e., RdyOut1) of the slave 1 in the communication in the 2-stage bus cascade system may be determined as follows.
Firstly, a micro-value resistor Rx is not welded on an output logic 13(RdyOut1), no signal is output by the output logic 13(RdyOut1) of the communication slave 1, and the communication slave 2 is pulled up by depending on an input, so that the communication slave 2 reads a high-level signal from an input logic 22(RdyIn 2);
secondly, a micro-resistance Rx is welded on the output logic 13(RdyOut1) or is directly short-circuited by a lead, the output logic 13(RdyOut1) of the communication slave 1 outputs a high-level signal, and the logic driver 24 on the input logic 22(RdyIn2) of the communication slave 2 is controlled by the high-level signal output by the RdyOut1 of the communication slave 1 to drive the input logic 22(RdyIn2) to input the high-level signal;
thirdly, a micro-value resistor Rx is welded on the output logic 13(RdyOut1) or is directly short-circuited by a lead, the communication slave 1 outputs a high-resistance signal by adopting a tri-state gate at the output logic 13(RdyOut1), and the communication slave 2 pulls up by means of an input, so that the input logic 22(RdyIn2) reads a high-level signal.
It should be noted that, there may be other ways to implement the reading of the level signal from the second-level communication slave to the level signal opposite to the level signal from the first-level communication slave besides the above three ways, which is only an example and is not intended to limit the application scope of the embodiment of the present invention.
By adopting the bus cascade system provided by the embodiment of the invention, the communication slave 1 is connected to the communication master 100, the communication slave 2 is connected to the communication slave 1, 2-level cascade is realized, the logical addresses of the communication slave 1 and the communication slave 2 are the same by default, the communication slave 1 changes the logical address thereof and registers the logical address on the communication master under the control of the level signal from the communication master 100, and the communication slave 2 keeps the default logical address unchanged, so that the logical control and address identification during the 2-level communication slave cascade are simplified.
Referring to fig. 4, a schematic structural diagram of a bus cascade system according to a third embodiment of the present invention is shown. The bus cascade system comprises at least three communication slaves and a communication master 100, wherein:
the communication master 100 is logically connected to an input of one of the at least three communication slaves and transmits a broadcast signal to the at least three communication slaves.
The input logic of one communication slave machine of the other two communication slave machines is connected with the output logic of one communication slave machine connected with the communication master machine, and the input logic of the other communication slave machine of the other two communication slave machines is connected with the output logic of one communication slave machine of the other two communication slave machines;
the communication master 100 sends broadcast signals to the at least three communication slaves, and the at least three communication slaves determine their own logical addresses according to the level signals received by their own input logics and the broadcast signals, and perform logical address registration on the communication master according to the own logical addresses.
In the present embodiment, each communication slave machine is represented by a communication slave machine 1 and a communication slave machine 2.. the communication slave machine m, specifically, as shown in the figure, the output logic 13 of the communication slave machine 1 and the input logic 22 of the communication slave machine 2 are connected to each other and are connected to the bus of the communication master machine 100 by the input logic 12 of the communication slave machine 1, and the input logic 22 of the communication slave machine 2 is connected to the output logic 13 of the communication slave machine 1.. the input logic m2 of the communication slave machine m is connected to the output logic (m-1)3 of the communication slave machine (m-1), thereby realizing bus cascade connection. Wherein, the grounding terminal 1000 of the communication host 100 is grounded
The structure and function of the communication slave in the bus cascade system are explained by taking the communication slave 1 as an example;
the communication slave 1 includes: input logic 12, a central processor 11, and a bus transceiver 15, wherein,
the input logic 12 is connected to the communication host 100 through a bus and receives a level signal from the communication host 100;
the bus transceiver 15 for receiving the broadcast signal from the communication host 100;
the central processing unit 11 is configured to determine a logical address of the communication slave 1 according to the level signal received by the input logic 12 and the broadcast signal, and register the logical address of the communication slave 1 according to the logical address.
Further, the communication slave 1 comprises an output logic 13, the output logic 13 being connected to the input logic 22 of the communication slave 2 via a bus.
Further, the communication slave 1 comprises a logic driver 14 for connecting with the input logic 12 and the output logic 13, wherein the logic driver 14 is controlled by a level signal to drive the input logic 12 and the output logic 13 to output corresponding level signals. In a specific implementation, the logic driver 14 may be a single logic driver connected to the input logic 12 and the output logic 13, or two logic drivers connected to the input logic 12 and the output logic 13, respectively.
The central processor 11 includes an address determining module 110 and an address registering module 111.
The address determining module 110 is configured to determine a logical address of the communication slave 1 according to the broadcast signal;
the address registration module 111 is configured to perform logical address registration on the communication slave 1 according to the logical address.
Here, when the communication slave 1 is bus-connected to the communication slave 2 and the communication master 100, the same physical interface 10 may be used, and in practical applications, the physical interface 10 may be further divided into an uplink physical interface 101 and a downlink physical interface 102, the communication slave 1 is connected to the physical interface 001 of the communication master 100 through the uplink physical interface 101 and is connected to the physical interface 20 of the communication slave 2 through the downlink physical interface 102, and the communication slave m may also include the physical interface m0, which is not described herein again.
Specifically, in operation, the logical addresses of the communication slave 1 to the communication slave m are the same as each other by default, for example, all are logical address 0, the level of the communication master 100 is opposite to the levels of the communication slave 1, the communication slave 2 and the communication slave m, when the input logic 12 of the communication slave 1 receives a level signal from the communication master 100, the default level of the communication slave 1 itself is changed under the control of the level signal of the communication master 100, and when the level of the communication slave 1 is changed, the communication master 100 transmits a broadcast signal to the communication slave 1 to instruct the communication slave 1 to perform logical address registration.
The broadcast signal carries registered address information, and the communication slave 1 selects an unregistered logical address as a logical address of the communication slave according to the broadcast signal, and performs logical address registration on the communication master 100 by using the logical address;
or the communication master 100 allocates a logical address to the communication slave 1 by sending a broadcast signal thereto, where the allocated logical address is different from the default logical address; for example, if the communication master 100 allocates the logical address 256 to it by broadcasting a signal, the communication slave 1 performs logical address registration on the communication master 100 with the logical address 256; when the input logic 22 of the communication slave 2 receives the level signal output from the output logic 13 of the communication slave 1, the default level of the input logic itself is changed under the control of the level signal of the communication slave 1, and when the level of the communication slave 2 is changed, the communication master 100 assigns a logical address, for example, a logical address 255 (the logical address is different from the logical address of the communication slave 1, but may be the same as the default logical address) by sending a broadcast signal thereto.
Still, the embodiment of the present invention takes RS485 asynchronous serial communication bus as an example to describe the embodiment of the present invention, and the embodiment of the present invention can also be applied to the technical fields such as PCI and ethernet.
By adopting the bus cascade system provided by the embodiment of the invention, the input logic 12 of the communication slave 1 is connected to the communication master 100 through a bus, the input logic and the output logic of the other levels of communication slaves realize cascade through the bus, the communication slave changes the self-default level under the control of the level signal received by the input logic 12 of the communication slave, the communication master 100 allocates a logic address to the communication slave through a broadcast signal, the communication slave determines the self logic address according to the broadcast signal and registers the logic address on the master through the logic address, so that the logic control and the address identification are simplified when the multi-level communication slave cascade is realized.
Certainly, in a special case, the bus concatenation system provided in this embodiment may also adopt a protection mechanism, and the logical address registration and the communication are completed without being sequentially triggered according to the concatenation sequence. For example, communication between the communication master and the communication slave is normally performed according to a cascade sequence from the communication slave 1 to the communication slave m, when the communication slave s (0 < s < m, s being an integer) fails to operate, the communication slave (s +1,. said., m) cascaded after the communication slave s cannot be registered for a set period of time, and when the communication master detects that no communication slave is registered for more than the set period of time, the communication master sends a control broadcast signal to notify all communication slaves RdyOut which have not been registered successfully to output a low level signal, and RdyOut of the communication slave s maintains a high level because the communication slave s fails. After reading the level signal of each RdyIn, the communication slave (s +1) can find the fault of the communication slave s, and the communication slave (s +1) can start the registration process through the bus communication slave to bypass the communication slave s and continue the logic address registration and the communication process.
Referring to fig. 5, a schematic structural diagram of a bus concatenation system according to a fourth embodiment of the present invention is shown.
In order to increase the reliability of the bus cascade system for signal transmission, a plurality of communication slaves may form a ring connection with two physical interfaces 001 and 002 of one communication master 100, as shown in fig. 5, an uplink physical interface 101 of the communication slave 1 is connected with one physical interface 001 of the communication master 100, an input logic of the communication slave 1 is connected to the communication master 100 through a bus, an uplink physical interface 201 of the communication slave 2 is connected with a downlink physical interface 102 of the communication slave 1, an input logic of the communication slave 2 is connected to an output logic of the communication slave 1 through a bus, and so on, the multi-level communication slaves are cascaded in sequence until being connected to an uplink physical interface m01 of the communication slave m, and a downlink physical interface m02 of the communication slave m is connected with the other physical interface 002 of the communication master 100. It should be noted that, in the same manner as the logical address registration manner in the third embodiment of the bus cascade system according to the embodiment of the present invention, the input logic (RdyIn) of each level of the communication slave changes its default level under the control of the level signal, and the communication master sends the broadcast signal to the communication slave with the changed level, and the communication slave determines its own logical address according to the broadcast signal and registers the logical address on the communication master.
In the bus concatenation system provided in the embodiment of the present invention, when a link of a communication slave connected to one physical interface of a communication master is interrupted, a plurality of communication slaves connected in a ring type may communicate with each other by connecting another physical interface of the communication master.
Referring to fig. 6, a schematic structural diagram of a fifth embodiment of a bus concatenation system according to the embodiment of the present invention is provided.
In order to increase the reliability of the bus cascade system for transmitting signals, the multi-level communication slave can form a ring connection with a single physical interface of two communication hosts.
As shown in fig. 6, the communication master 100 provides a plurality of physical interfaces including a physical interface 001, the uplink physical interface 101 of the communication slave 1 is connected to one physical interface 001 of the communication master 100, the input logic of the communication slave 1 is connected to the communication master 100 through a bus, the uplink physical interface 201 of the communication slave 2 is connected to the downlink physical interface 102 of the communication slave 1, and the input logic of the communication slave 2 is connected to the output logic of the communication slave 1 through a bus, so that the multi-level communication slaves are sequentially connected in cascade until being connected to the uplink physical interface m01 of the communication slave m, and the downlink physical interface m02 of the communication slave m is connected to one physical interface 00N of the communication master 200. Here, N represents any physical interface on the communication master 200, and it should be noted that, in a manner of performing logical address registration by the multi-stage communication slave, like the logical address registration manner in the third embodiment of the bus cascade system provided in the embodiment of the present invention, the input logic (RdyIn) of each stage of communication slave changes its default level under the control of the level signal, and the communication master sends a broadcast signal to the communication slave with the changed level, and the communication slave determines its own logical address according to the broadcast signal and performs logical address registration on the communication master.
In the bus concatenation system provided in the embodiment of the present invention, under a normal condition, the communication master 100 is in a working state, and the communication master 200 is in a standby state, when the communication master 100 fails, the standby communication master 200 is started to work, and the ring-connected multi-stage communication slave can realize communication by connecting one physical interface of the standby communication master 200.
Fig. 7 is a schematic structural diagram of a communication slave according to a first embodiment of the present invention.
The communication slave provided by the embodiment of the invention is applied to a bus cascade system with cascade level 2. The structure and function of the communication slave will be described below by taking the communication slave 1 as a communication slave connected to a communication master as an example, the communication slave 1 includes a central processing unit 11 and an input logic 12, wherein,
the input logic 12 is connected with a communication host through a bus;
the central processing unit 11 is configured to determine a logical address of the communication slave 1 according to the level signal received by the input logic 12, and register the logical address of the communication slave 1 according to the logical address.
Further, the communication slave 1 also comprises an output logic 13, the output logic 13 being connected via a bus to the input logic 22 of the communication slave 2 to which it is connected via the physical interface 10.
Further, the communication slave 1 further comprises a logic driver 14, wherein the logic driver 14 is connected to the input logic 12 and the output logic 13, and is configured to be controlled by a level signal to drive the input logic 12 and the output logic 13 to output corresponding level signals. In a specific implementation, the logic driver 14 may be a single logic driver connected to the input logic 12 and the output logic 13, or two logic drivers connected to the input logic 12 and the output logic 13, respectively.
The input logic 12 may be Rdyin input logic. The output logic 13 may be Rdyout output logic.
The central processor 11 includes an address determining module 110 and a logical address registering module 111.
The address determining module 110 is configured to determine a logic address of the communication slave 1 according to the level signal input by the input logic 12;
the logical address registration module 111 is configured to perform logical address registration on the communication slave 1 according to the logical address.
Here, when the communication slave 1 is connected to another communication slave and the communication master through a bus, the same physical interface 10 may be used, and in practical applications, the physical interface 10 may be divided into an uplink physical interface 101 and a downlink physical interface 102, and the communication slave 1 is connected to the physical interface of the communication master through the uplink physical interface 101 and is connected to the physical interface of another communication slave through the downlink physical interface 102.
In a specific operation, the logic addresses of the communication slave 1 and the other communication slave are the same by default, for example, both are logic 0 or logic 1 (in this embodiment, the original level states of the communication slave 1 and the other communication slave are both high level, and the default logic address is 1, for explanation), when the communication slave 1 connected to the communication master receives a low level signal from the communication master (because the ground terminal of the communication master is grounded, the communication master outputs a low level signal to the communication slave 1), the logic driver 14 of the communication slave 1 drives the input logic 12 to input a low level signal, the address determining module 110 of the cpu 11 of the communication slave 1 determines that the logic address of the communication slave 1 is opposite to the default logic address according to the low level signal input by the input logic 12, for example, the logic address is changed from logic address 1 to logic address 0, the logical address registration module 111 registers the logical address of the communication slave 1 according to the logical address 0. Then, the output logic 13 of the communication slave 1 outputs a high level signal to the communication slave 2, and the input logic 22 of the communication slave 2 receives the high level signal, and the logic address 1 is maintained unchanged if the level state is not changed.
By adopting the communication slave provided by the embodiment of the invention, under the control of the level signal from the communication master, the logic address of the communication slave is changed and the logic address registration is carried out on the communication master, and the default logic address is kept unchanged by the other communication slave, so that the logic control and the address identification are simplified when the level 2 communication slaves are cascaded.
Fig. 8 is a schematic structural diagram of a communication slave according to a second embodiment of the present invention.
The communication slave provided by the embodiment of the invention is applied to a bus cascade system with cascade hierarchy more than 2, and comprises the following components:
taking a communication slave 1 connected with a communication master as an example to explain the structure and the function of the communication slave in a bus cascade system with cascade hierarchy more than 2;
the communication slave 1 includes: input logic 12, a central processor 11, and a bus transceiver 15, wherein,
the input logic 12 is used for connecting with a communication host through a bus and receiving a level signal from the communication host;
the bus transceiver 15, is used for receiving the broadcast signal from the communication host;
the central processing unit 11 is configured to determine a logical address of the communication slave 1 according to the level signal received by the input logic 12 and the broadcast signal, and register the logical address of the communication slave 1 according to the logical address.
Further, the communication slave 1 comprises an output logic 13, the output logic 13 being connected with an input logic 22 of the communication slave 2.
Further, the communication slave 1 comprises two logic drivers 14, which are connected to the input logic 12 and the output logic 13, respectively. In a specific implementation, the logic driver 14 may be a single logic driver connected to the input logic 12 and the output logic 13, or two logic drivers connected to the input logic 12 and the output logic 13, respectively.
The central processor 11 includes an address determining module 110 and an address registering module 111.
The address determining module 110 is configured to determine a logical address of the communication slave 1 according to the level signal received by the input logic 12 and the broadcast signal;
the address registration module 111 is configured to perform logical address registration on the communication slave 1 according to the logical address.
In this case, when the communication slave 1 is bus-connected to another communication slave and a communication master, the same physical interface 10 may be used, and in practical applications, the physical interface 10 may be divided into an uplink physical interface 101 and a downlink physical interface 102, and the communication slave 1 is connected to the physical interface 001 of the communication master through the uplink physical interface 101 and is connected to the physical interface of another communication slave through the downlink physical interface 102.
During specific operation, the logical addresses of all communication slaves in the bus cascade system with the cascade hierarchy greater than 2 are the same by default, for example, all the logical addresses are logical address 0, when the input logic 12 of the communication slave 1 receives a level signal from the communication master, the default level of the communication slave changes under the control of the level signal of the communication master, and when the level of the communication slave 1 changes, the communication master sends a broadcast signal to the communication slave to indicate the communication slave to perform logical address registration.
The broadcast signal carries registered address information, the communication slave 1 selects a logic address which is not registered as a logic address of the communication slave according to the broadcast signal, and performs logic address registration on the communication host by using the logic address;
or the communication host machine distributes a logic address for the communication slave machine 1 by sending a broadcast signal to the communication slave machine, wherein the distributed logic address is different from the default logic address; for example, the communication master assigns a logical address 256 to it by a broadcast signal, and the communication slave 1 performs logical address registration on the communication master with the logical address 256.
The communication slave machine provided by the embodiment of the invention has the advantages that the default level of the communication slave machine is changed under the control of the level signal, the communication master machine distributes the logic address to the communication slave machine through the broadcast signal, the communication slave machine determines the logic address of the communication slave machine according to the broadcast signal and registers the logic address on the master machine according to the logic address, and therefore the logic control and the address identification are simplified when the multi-level communication slave machines are connected in a cascade mode.
Referring to fig. 9, a flowchart of a first embodiment of a bus concatenation method according to an embodiment of the present invention is shown.
With reference to fig. 3, an implementation flow of the bus concatenation method provided in the embodiment of the present invention in a bus concatenation system with a concatenation hierarchy level of 2 is described, where the bus concatenation system includes a communication master 100, a communication slave 1, and a communication slave 2, and an input logic 22 of the communication slave 2 is connected to an output logic 13 of the communication slave 1 through a bus, and is connected to the communication master 100 through a bus by an input logic 12 of the communication slave 1. Here, the cascade connection mode in which the communication slave 1 is a front stage of the communication slave 2 and the communication slave 2 is a rear stage of the communication slave 1 is referred to as a bus cascade having a cascade hierarchy of 2 stages. The logical address and the level state of the communication slave 1 and the communication slave 2 are the same by default, for example, both are logical address 0 or logical address 1.
The method specifically comprises the following steps:
102, the communication slave 1 registers a logical address on the communication master 100 according to the logical address 0;
104, the communication slave machine 2 receives the level signal, and the default level of the communication slave machine is not changed;
in step 105, the communication slave 2 maintains its default logical address 1.
By adopting the bus cascading method provided by the embodiment of the invention, the communication slave 1 is connected to the communication master 100, the communication slave 2 is connected to the communication slave 1, 2-level cascading is realized, the logical addresses of the communication slave 1 and the communication slave 2 are the same by default, the communication slave 1 changes the logical address thereof and registers the logical address on the communication master under the control of the level signal from the communication master 100, and the communication slave 2 keeps the default logical address unchanged, so that the logical control and the address identification are simplified when the 2-level communication slave is cascaded.
Referring to fig. 10, a flowchart of a second embodiment of a bus concatenation method according to the embodiment of the present invention is shown.
With reference to fig. 3, an implementation flow of the bus concatenation method provided in the embodiment of the present invention in a bus concatenation system with a concatenation hierarchy level of 2 is described, where the bus concatenation system includes a communication master 100, a communication slave 1, and a communication slave 2, and an input logic 22 of the communication slave 2 is connected to an output logic 13 of the communication slave 1 through a bus, and is connected to the communication master 100 through a bus by an input logic 12 of the communication slave 1. Here, the cascade connection mode in which the communication slave 1 is a front stage of the communication slave 2 and the communication slave 2 is a rear stage of the communication slave 1 is referred to as a bus cascade having a cascade hierarchy of 2 stages. The logical address and the level state of the communication slave 1 and the communication slave 2 are the same by default, for example, both are the logical address 0 or the logical address 1 (in this embodiment, the original level states of the communication slave 1 and the communication slave 2 are both high level, and the default logical address is 1).
The method specifically comprises the following steps:
step 203, the communication slave 1 outputs a high-level signal to the communication slave 2;
step 204, the communication slave machine 2 receives the high level signal, and the default level of the communication slave machine is not changed;
in step 205, the communication slave 2 maintains the logical address 1 unchanged.
By adopting the bus cascading method provided by the embodiment of the invention, the communication slave 1 is connected to the communication master 100, the communication slave 2 is connected to the communication slave 1, 2-level cascading is realized, the logical addresses of the communication slave 1 and the communication slave 2 are the same by default, the communication slave 1 changes the logical address thereof and registers the logical address on the communication master under the control of the low level signal from the communication master 100, and the communication slave 2 keeps the default logical address unchanged, so that the logical control and address identification are simplified when the 2-level communication slave is cascaded.
Referring to fig. 11, a flowchart of a bus concatenation method according to a third embodiment of the present invention is shown.
Referring to fig. 4, an implementation flow of the bus concatenation method provided by the embodiment of the present invention in a bus concatenation system with a concatenation hierarchy greater than 2 is described, as shown in the figure, the output logic 13 of the communication slave 1 is connected to the input logic 22 of the communication slave 2 through a bus, and the input logic 12 of the communication slave 1 is connected to the bus of the communication master 100 through a bus, and the input logic 22 of the communication slave 2 is connected to the output logic 13 of the communication slave 1 through a bus, the input logic m2 of the communication slave m is connected to the output logic (m-1)3 of the communication slave (m-1) through a bus, so as to implement bus concatenation. The logical address and the level state of the communication slave are the same by default, for example, the default logical address is both logical address 0 or logical address 1.
The bus concatenation method provided by the embodiment of the invention specifically comprises the following steps:
in the same way, the communication slave machine changes the self-default level under the control of the level signal opposite to the self-default level, reads the broadcast signal from the communication master machine and determines the self logic address; and according to the said logical address confirmed, carry on the logical address registration on the communication host computer; after the registration is finished, the communication slave machine outputs a level signal to indicate the next level communication slave machine to register the logic address until the last level communication slave machine finishes the logic address registration.
Referring to fig. 12, a flowchart of a fourth embodiment of a bus concatenation method according to the embodiment of the present invention is shown.
Referring to fig. 4, an implementation flow of the bus concatenation method provided by the embodiment of the present invention in a bus concatenation system with a concatenation hierarchy greater than 2 is described, as shown in the figure, the output logic 13 of the communication slave 1 is connected to the input logic 22 of the communication slave 2 through a bus, and the input logic 12 of the communication slave 1 is connected to the bus of the communication master 100 through a bus, and the input logic 22 of the communication slave 2 is connected to the output logic 13 of the communication slave 1 through a bus, the input logic m2 of the communication slave m is connected to the output logic (m-1)3 of the communication slave (m-1) through a bus, so as to implement bus concatenation. The logic address and the level state of the communication slave are the same by default, for example, the default logic address is logic address 0 or logic address 1, and the default level is high.
The bus concatenation method provided by the embodiment of the invention specifically comprises the following steps:
in this way, the communication slave machine changes the default high level of the communication slave machine under the control of the low level signal, reads the broadcast signal from the communication master machine and determines the logic address of the communication slave machine; and according to the said logical address confirmed, carry on the logical address registration on the communication host computer; after the registration is finished, the communication slave machine outputs a low level signal to indicate the next level communication slave machine to register the logic address until the last level communication slave machine finishes the logic address registration.
Referring to fig. 13, a flowchart of a fifth embodiment of a bus concatenation method according to the embodiment of the present invention is shown.
Referring to fig. 4, an implementation flow of the bus concatenation method provided by the embodiment of the present invention in a bus concatenation system with a concatenation hierarchy greater than 2 is described, as shown in the figure, the output logic 13 of the communication slave 1 is connected to the input logic 22 of the communication slave 2 through a bus, and is connected to the communication master 100 through a bus by the input logic 12 of the communication slave 1, and the input logic 22 of the communication slave 2 is connected to the output logic 13 of the communication slave 1 through a bus, the input logic m2 of the communication slave m is connected to the output logic (m-1)3 of the communication slave (m-1) through a bus, so as to implement bus concatenation. The logic address and the level of the communication slave are the same by default, for example, the default logic address is logic address 0 or logic address 1, and the default level is high level.
The bus concatenation method provided by the embodiment of the invention specifically comprises the following steps:
in this way, the communication slave machine changes the default high level state of the communication slave machine under the control of the low level signal, reads the broadcast signal from the communication master machine and determines the logic address of the communication slave machine; and according to the said logical address confirmed, carry on the logical address registration on the communication host computer; after the registration is finished, the communication slave machine outputs a low level signal to indicate the next level communication slave machine to register the logic address until the last level communication slave machine finishes the logic address registration.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention may be implemented by software plus a necessary hardware platform, and may also be implemented by hardware entirely. With this understanding in mind, all or part of the technical solutions of the present invention that contribute to the background can be embodied in the form of a software product, which can be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments or some parts of the embodiments of the present invention.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (13)
1. A bus concatenation method, when the hierarchy of the concatenation is two levels, that is, the hierarchy includes a communication master, a first communication slave connected with the communication master, and a second communication slave connected with the first communication slave, wherein the level and logical address of the first communication slave and the second communication slave are the same by default, the method comprising:
the first communication slave machine receives a level signal of the communication master machine, wherein the level signal is opposite to the level of the first communication slave machine default;
the first communication slave machine changes self-default level according to the received level signal, changes self-default logic address and registers the logic address on the communication host machine;
and the second communication slave receives the default level and keeps the self-default logical address unchanged.
2. The bus cascading method of claim 1, wherein the communication master is grounded, the input logic of the first communication slave is connected with the communication master, the output logic of the first communication slave is connected with the input logic of the second communication slave, the bus cascading method comprising:
the communication master machine outputs a low-level signal to the first communication slave machine;
after the first communication slave reads the low level signal through the input logic of the first communication slave, the default high level of the first communication slave is changed into the low level, the default logic address of the first communication slave is changed, and the logic address is registered on the communication host according to the changed logic address;
and the input logic of the second communication slave machine receives a high level signal and keeps the default logic address unchanged.
3. The bus cascading method of claim 2, wherein the manner in which the input logic of the second communication slave is a high signal comprises:
the output logic of the first communication slave machine does not output signals, and the second communication slave machine depends on input pull-up to enable the input logic of the second communication slave machine to be high-level signals; or
The output logic of the first communication slave machine outputs a high level signal to drive the logic driver of the second communication slave machine, so that the input logic of the second communication slave machine is a high level signal; or
The output logic of the first communication slave machine adopts a three-state gate to output a high level signal, and the second communication slave machine depends on input pull-up to enable the input logic of the second communication slave machine to be the high level signal.
4. A method of bus concatenation, the method comprising:
receiving a level signal of a communication host, and changing the self-default level;
determining a logic address of the communication host according to the broadcast signal of the communication host, and registering the logic address on the communication host according to the logic address;
receiving a level signal output by a communication slave machine, and changing the self-default level;
determining a logic address of the communication host according to the broadcast signal of the communication host, and registering the logic address on the communication host according to the logic address;
when the communication host detects that the communication slave machines are not registered for the set time, sending a control broadcast signal to inform all communication slave machines which are not successfully registered to output low-level signals and judge that the communication slave machines which are output to high level in the communication slave machines which are not successfully registered have faults;
the communication slave machines at least comprise a first communication slave machine, a second communication slave machine and a third communication slave machine, and the levels of the first communication slave machine, the second communication slave machine and the third communication slave machine are same by default;
the first communication slave machine receives a level signal of the communication host machine, wherein the level signal is opposite to a default level, and changes the default level state of the first communication slave machine;
the first communication slave machine receives a broadcast signal of the communication host machine after changing the self-default level, determines the self logic address according to the broadcast signal, and registers the logic address on the communication host machine according to the determined logic address;
the second communication slave machine receives an output level signal of the first communication slave machine, changes the default level of the second communication slave machine, receives a broadcast signal of the communication host machine, determines the logic address of the second communication slave machine according to the broadcast signal, and registers the logic address on the communication host machine according to the determined logic address;
and the third communication slave machine receives the output level signal of the second communication slave machine, changes the self default level, receives the broadcast signal of the communication host machine, determines the self logic address according to the broadcast signal, and registers the logic address on the communication host machine according to the determined logic address.
5. A communication slave, wherein the communication slave is used in a two-level bus cascade system, the level and the logic address of the communication slave are the same as the other communication slave by default, the communication slave is characterized by comprising a central processing unit and input logic, wherein,
the input logic is used for being connected with a communication host or being connected with the output logic of the other communication slave and receiving a level signal of the communication host or a level signal of the output logic of the other communication slave;
the central processing unit is used for determining the logic address of the communication slave according to the level signal of the input logic and registering the logic address of the communication slave according to the logic address;
the central processing unit includes:
the address determination module is used for determining the logic address of the communication slave according to the level signal of the input logic input;
and the logical address registration module is used for registering the logical address of the communication slave according to the logical address determined by the address determination module.
6. The communication slave of claim 5, wherein the communication slave further comprises:
and the output logic is used for being connected with the input logic of the next-level communication slave and transmitting the level signal to the input logic.
7. The communication slave of claim 6, wherein said communication slave further comprises:
and the logic driver is connected with the input logic and the output logic and is used for driving the input logic and the output logic to output corresponding level signals under the control of the level signals.
8. A communication slave comprising input logic, a central processing unit and a bus transceiver, wherein,
the input logic is used for being connected with a communication host or being connected with the output logic of another communication slave and receiving the level signal of the communication host or the level signal of the output logic of the another communication slave;
the bus transceiver is used for receiving broadcast signals from the communication host;
the central processing unit is used for determining the logical address of the communication slave according to the broadcast signal when the bus transceiver receives the broadcast signal from the communication host, registering the logical address of the communication slave according to the logical address, and sending a control broadcast signal, informing all communication slaves which do not register successfully to output low-level signals and judging that the communication slaves which do not register successfully output high-level signals have faults when the communication host detects that the communication slaves do not register at the set time, and continuing the logical address registration and the communication flow.
9. The communication slave of claim 8, wherein said communication slave further comprises:
and the output logic is used for being connected with the input logic of the next-level communication slave.
10. The communication slave of claim 9, wherein the communication slave further comprises:
and the logic driver is connected with the input logic and the output logic and is used for driving the input logic and the output logic to output corresponding level signals under the control of level signals and a central processing unit.
11. The communication slave according to claim 8 or 10, wherein said central processor comprises:
the address determination module is used for determining the logic address of the communication slave according to the broadcast signal;
and the logical address registration module is used for registering the logical address of the communication slave according to the logical address.
12. A bus cascade system is characterized by comprising a communication master machine, a first communication slave machine and a second communication slave machine, wherein the level and the logical address of the first communication slave machine and the second communication slave machine are same by default, the level of the first communication slave machine and the second communication slave machine is opposite to the level of the communication master machine, the output logic of the first communication slave machine is logically connected with the input logic of the second communication slave machine, and the bus cascade system comprises:
the communication master machine is connected with the input logic of the first communication slave machine;
the first communication slave is used for receiving a level signal of the communication host machine, wherein the level signal is opposite to the default level of the first communication slave machine, and under the control of the level signal, the first communication slave machine changes the default level of the first communication slave machine, changes the default logical address of the first communication slave machine, and registers the logical address on the communication host machine;
and the second communication slave machine receives the level signal of the output logic of the first communication slave machine and keeps the self-default logic address unchanged.
13. A bus cascade system is characterized by comprising at least three communication slave machines and a communication master machine, wherein:
the communication master machine is in input logic connection with one of the at least three communication slave machines and sends broadcast signals to the at least three communication slave machines;
the input logic of one communication slave machine of the other two communication slave machines is connected with the output logic of one communication slave machine connected with the communication master machine, and the input logic of the other communication slave machine of the other two communication slave machines is connected with the output logic of one communication slave machine of the other two communication slave machines;
the communication master sends broadcast signals to the at least three communication slave machines, and when the communication master detects that the communication slave machines are not registered for the set time, the communication master sends control broadcast signals to inform all the communication slave machines which are not successfully registered to output low-level signals and judge that the communication slave machines which are not successfully registered and output high-level signals have faults;
the at least three communication slave machines determine own logic addresses according to level signals received by own input logics and the broadcast signals, and register the logic addresses on the communication host machine according to the own logic addresses;
the at least three communication slave machines are a first communication slave machine, a second communication slave machine and a third communication slave machine; wherein,
the level and the logic address of the first communication slave machine, the second communication slave machine and the third communication slave machine are same by default, the level of the communication master machine is opposite to the level of the first communication slave machine, the second communication slave machine and the third communication slave machine, wherein,
the input logic of the first communication slave machine is connected with the communication host machine through a bus, the first communication slave machine receives a level signal of the communication host machine, and changes the self-default level under the control of the level signal; the first communication slave machine determines the logic address of the first communication slave machine according to the broadcast signal, and performs logic address registration on the communication host machine according to the determined logic address;
the input logic of the second communication slave machine is connected with the output logic of the first communication slave machine, the second communication slave machine receives the level signal of the output logic of the first communication slave machine, and the level of the second communication slave machine is changed to be default under the control of the level signal of the first communication slave machine; the second communication slave machine determines the logic address of the second communication slave machine according to the broadcast signal, and performs logic address registration on the communication host machine according to the determined logic address;
the input logic of the third communication slave machine is connected with the output logic of the second communication slave machine, the third communication slave machine receives the level signal of the output logic of the second communication slave machine, and the default level of the third communication slave machine is changed under the control of the level signal of the second communication slave machine; and the third communication slave machine determines the logic address of the third communication slave machine according to the broadcast signal, and registers the logic address on the communication host machine according to the determined logic address.
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