CN108155919B - A kind of nonpolarity RS-485 transceiver - Google Patents
A kind of nonpolarity RS-485 transceiver Download PDFInfo
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- CN108155919B CN108155919B CN201711483491.XA CN201711483491A CN108155919B CN 108155919 B CN108155919 B CN 108155919B CN 201711483491 A CN201711483491 A CN 201711483491A CN 108155919 B CN108155919 B CN 108155919B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
Abstract
A kind of nonpolarity RS-485 transceiver, belongs to and is related to design of electronic circuits and microelectronic field, including RS-485 bus L1 line, RS-485 bus L2 line, the receiver to receive RS-485 bus signals and to the driver to RS-485 bus transfer signal；The receiver includes the first differential receiver and the second differential receiver；The driver includes differential transmitter, and the differential transmitter includes input terminal U15_DI, output end U15_A, output end U15_B and enable end U15_DE；The output end U15_A of the input terminal U13_A of first differential receiver, the input terminal U14_B of the second differential receiver and differential transmitter are all connected with RS-485 bus L2；The input terminal U13_B of first differential receiver, the input terminal U14_A of the second differential receiver, differential transmitter output end U15_B be all connected with RS-485 bus L1 line.RS485 transceiver of the present invention can allow RS485 bus not repartition A line, B line, simplify site operation, convenient for safeguarding, improve the reliability of system.
Description
Technical field
The invention belongs to design of electronic circuits and microelectronic fields, and in particular to for a kind of nonpolarity RS-485 transmitting-receiving
Device.
Background technique
Nonpolarity RS485 bus provides very big convenience to scene installation, it is other not to need to distinguish line, as long as wiring is reliably
It can.Later period additional equipment saves manpower without existing line is interrogated and examined.In State Grid Corporation of China company standard Q/GDW 1354-
2013 " intelligent electric energy meter functional specification " 4.9.1 RS485 communication the f) article require in clearly stipulate that " RS485 interface
It should ensure that positive and negative wiring can normal communication in 485 buses."
The patent No. application " nonpolar RS-485 interface circuit " of Publication No. CN102521193B discloses a kind of electrodeless
Property RS-485 interface chip, obtained " nonpolarity RS-485 chip " for wiring polarity judgment basis be bus initial shape
V is kept between A, B line under stateAB> 200Mv, it is real that implementation generally increases upper and lower pull-up resistor at the bus host node end RS485
Existing, resistance value is generally between 1~10K Ω, when bus node increases, the interface protection device on connections and each node
Increase, it is upper and lower that the electric current provided is drawn to be not sufficient to ensure that on distant-end node due to the leakage current of line drop and protection device
It is poor to provide required voltage.It especially under severe conditions, is 120 Ω when RS485 bus needs to connect terminating resistor representative value
Come when improving bus waveform, which can not correctly judge wiring polarity.
Summary of the invention
It is an object of the invention to overcome defect and deficiency mentioned above, and provide a kind of nonpolarity RS-485 transmitting-receiving
Device.
The present invention realizes its purpose, and the technical solutions adopted are as follows.
A kind of nonpolarity RS-485 transceiver, including RS-485 bus L1 line, RS-485 bus L2 line, to receive RS-
The receiver of 485 bus signals and to the driver to RS-485 bus transfer signal；
The receiver includes the first differential receiver and the second differential receiver；
First differential receiver, including input terminal U13_A, input terminal U13_B, output end U13_RO and enable end
U13_RE；
Second differential receiver, including input terminal U14_A, input terminal U14_B, output end U14_RO and enable end
U14_RE；
The driver includes differential transmitter,
The differential transmitter includes input terminal U15_DI, output end U15_A, output end U15_B and enable end U15_DE；
The input terminal U13_A of first differential receiver, the input terminal U14_B of the second differential receiver and difference are sent
The output end U15_A of device is all connected with RS-485 bus L2；
The input terminal U13_B of first differential receiver, the input terminal U14_A of the second differential receiver, difference are sent
The output end U15_B of device is all connected with RS-485 bus L1 line.
A kind of nonpolarity RS-485 transceiver, further includes the 10th resistance and the 11st resistance；10th resistance one end connection
RS-485 bus L2 line, other end ground connection；11st resistance connects RS-485 bus L1 line, other end ground connection.
A kind of nonpolarity RS-485 transceiver, further includes: first resistor, second resistance, 3rd resistor, the 4th resistance,
Five resistance, the 6th resistance, the 7th resistance, the 8th resistance, first diode, the second diode, third diode, first capacitor,
Second capacitor, the first NOT gate, the second NOT gate, the first rest-set flip-flop, first and door, the first latch, the second latch, the one or three
State door, the second tri-state gate, receives output pin, receives enabled pin, VCC supply lines the first XOR gate；
First NOT gate, including input terminal U1_A and output end U1_Y；
Second NOT gate, including input terminal U2_A and output end U2_Y；
First rest-set flip-flop, including signal end U3_CP, input terminal U3_SD, input terminal U3_RD, output end U3_Q,
Output end U3_D.
Described first and door, including input terminal U5_A, input terminal U5_B and output end U5_Y；
First latch, including enable end U6_LE, input terminal U6_D, output end U6_Q；
Second latch, including enable end U7_LE, input terminal U7_D, output end U7_Q；
First tri-state gate, including input terminal U9_A, output end U9_Y and enable end U9_OE；
First XOR gate, including input terminal U10_A, input terminal U10_B, output end U10_Y；
Second tri-state gate, including input terminal U11_A, output end U11_Y and enable end U11_OE；
The input terminal U1_A connection of first NOT gate receive output pin and first with the output end U5_Y of door；Described
The output end of the output end U1_Y connection first diode of one NOT gate；The input terminal connection first resistor of the first diode
One end, one end of first capacitor, the first rest-set flip-flop signal end U3_CP；The other end of first resistor connects VCC supply lines；
The other end of first capacitor is grounded；
The input terminal U2_A connection of second NOT gate receives enabled pin, output end U2_Y the second diode of connection it is defeated
Outlet；One end of the input terminal connection second resistance of second diode, the input terminal U3_SD of the first rest-set flip-flop, third
The input terminal of diode；The other end connection connection VCC supply lines of second resistance；The second electricity of output end connection of third diode
One end of one end of appearance and the 5th resistance；The other end of second capacitor is grounded；The other end of 5th resistance connects the first XOR gate
Output end U10_Y；
The input terminal U3_RD connection VCC supply lines of first rest-set flip-flop, output end U3_Q the first latch of connection
The enable end U7_LE of enable end U6_LE and the second latch, output end U3_D ground connection；
Described first connect one end of the 4th resistance, the input terminal U6_D of the first latch, with the input terminal U5_A of door
The output end U9_Y of one tri-state gate, one end of input terminal U5_B connection 3rd resistor, the input terminal U7_D of the second latch, second
The output end U11_Y of tri-state gate；The other end of 4th resistance, the other end of 3rd resistor are all connected with VCC supply lines；
The enable end U11_OE of output end U6_Q the second tri-state gate of connection of first latch；
The enable end U9_OE of output end U7_Q the first tri-state gate of connection of second latch；
One end of the 6th resistance of input terminal U9_A connection of first tri-state gate, the first differential receiver output end
The input terminal U10_A of U13_RO, the first XOR gate；The other end of 6th resistance connects VCC supply lines；
One end of the 7th resistance of input terminal U10_B connection of first XOR gate, the second tri-state gate input terminal U11_
A, the output end U14_RO of the second differential receiver；The other end of 7th resistance connects VCC supply lines.
4. a kind of nonpolarity RS-485 transceiver as described in claim 1, which is characterized in that further include: it sends enabled
Foot, transmission input pin, third NOT gate, first or door, the second rest-set flip-flop, the 9th resistance, twelfth resistor；
The third NOT gate, including input terminal U4_A and output end U4_Y；
Described first or door, including input terminal U8_A, input terminal U8_B and output end U8_Y；
Second rest-set flip-flop, including signal end U12_CP, input terminal U12_SD, input terminal U12_RD, output end
U12_Q, output end U12_D；
The input terminal U4_A connection of the third NOT gate sends enabled foot, the input terminal U12_RD of the second rest-set flip-flop, the
The input terminal U8_A of one end of nine resistance, output end U4_Y connection first or door；The other end of 9th resistance is grounded；
Described first or door input terminal U8_B connection send input pin, one end of twelfth resistor, differential transmitter
Input terminal U15_DI, the signal end U12_CP of output end U8_Y the second rest-set flip-flop of connection；The other end of twelfth resistor connects
Connect VCC supply lines；
The input terminal U12_SD and output end U12_D of second rest-set flip-flop, which are all connected with, connects VCC supply lines, output end
The enable end U15_DE of U12_Q connection differential transmitter.
The nonpolarity connection of RS485 bus may be implemented in RS485 transceiver of the present invention, and the circuit passes through Double deference
Receiver interconnection carries out logic judgment to bus level；Judge whether there is useful signal in bus by XOR gate；Pass through
Trigger, latch keep polarity selection and state reset；Realize that data start bit starts to send by trigger.Institute of the present invention
The RS485 transceiver stated can allow RS485 bus not repartition A line, B line, simplify site operation, convenient for safeguarding, improve system
Reliability.
Detailed description of the invention
Fig. 1 is logical circuitry of the invention.
Specific embodiment
With reference to the accompanying drawing, invention is further described in detail.
A kind of nonpolarity RS-485 transceiver, including RS-485 bus L1 line, RS-485 bus L2 line, to receive RS-
The receiver of 485 bus signals and to the driver to RS-485 bus transfer signal；
The receiver includes the first differential receiver U13 and the second differential receiver U14；
The first differential receiver U13, including input terminal U13_A, input terminal U13_B, output end U13_RO and enabled
Hold U13_RE；
The second differential receiver U14, including input terminal U14_A, input terminal U14_B, output end U14_RO and enabled
Hold U14_RE；
The driver includes differential transmitter U15,
The differential transmitter U15 includes input terminal U15_DI, output end U15_A, output end U15_B and enable end U15_
DE；
The input terminal U14_B and difference of the input terminal U13_A of the first differential receiver U13, the second differential receiver U14
The output end U15_A of transmitter U15 is divided to be all connected with RS-485 bus L2；
Input terminal U13_B, the input terminal U14_A of the second differential receiver U14, difference of the first differential receiver U13
The output end U15_B of transmitter U15 is divided to be all connected with RS-485 bus L1 line.
Specifically, a kind of nonpolarity RS-485 transceiver, further includes:
First resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6,
Seven resistance R7, the 8th resistance R8, the 9th resistance R9, the 10th resistance R10, the 11st resistance R11, twelfth resistor R12, the one or two pole
Pipe D1, the second diode D2, third diode D3, first capacitor C1, the second capacitor C2, the first NOT gate U1, the second NOT gate U2,
One rest-set flip-flop U3, third NOT gate U4, first and door U5, the first latch U6, the second latch U7, first or door U8, first
Tri-state gate U9, the first XOR gate U10, the second tri-state gate U11, the second rest-set flip-flop U12, reception output pin RO, reception are enabled
Pin nRE, VCC supply lines send enabled foot DE, send input pin DI.
The first NOT gate U1, including input terminal U1_A and output end U1_Y；
The second NOT gate U2, including input terminal U2_A and output end U2_Y；
The first rest-set flip-flop U3, including signal end U3_CP, input terminal U3_SD, input terminal U3_RD, output end U3_
Q, output end U3_D.
The third NOT gate U4, including input terminal U4_A and output end U4_Y.
Described first and door U5, including input terminal U5_A, input terminal U5_B and output end U5_Y；
The first latch U6, including enable end U6_LE, input terminal U6_D, output end U6_Q；
The second latch U7, including enable end U7_LE, input terminal U7_D, output end U7_Q；
Described first or door U8, including input terminal U8_A, input terminal U8_B and output end U8_Y.
The first tri-state gate U9, including input terminal U9_A, output end U9_Y and enable end U9_OE；
The first XOR gate U10, including input terminal U10_A, input terminal U10_B, output end U10_Y；
The second tri-state gate U11, including input terminal U11_A, output end U11_Y and enable end U11_OE；
The second rest-set flip-flop U12, including signal end U12_CP, input terminal U12_SD, input terminal U12_RD, output end
U12_Q, output end U12_D；
The input terminal U1_A connection of the first NOT gate U1 receives the output end U5_Y of output pin RO and first and door U5；
The output end of the output end U1_Y connection first diode D1 of the first NOT gate U1；The input terminal of the first diode D1 connects
Connect one end of first resistor R1, one end of first capacitor C1, the first rest-set flip-flop U3 signal end U3_CP；First resistor R1's
The other end connects VCC supply lines；The other end of first capacitor C1 is grounded；
The input terminal U2_A connection of the second NOT gate U2 receives enabled pin nRE, the two or two pole of output end U2_Y connection
The output end of pipe D2；Input terminal connection one end of second resistance R2 of the second diode D2, the first rest-set flip-flop U3 it is defeated
Enter to hold the input terminal of U3_SD, third diode D3；The other end connection connection VCC supply lines of second resistance R2；Third diode
The output end of D3 connects one end of the second capacitor C2 and one end of the 5th resistance R5；The other end of second capacitor C2 is grounded；5th
The other end of resistance R5 connects the output end U10_Y of the first XOR gate U10；
The input terminal U3_RD connection VCC supply lines of the first rest-set flip-flop U3, output end U3_Q the first latch of connection
The enable end U7_LE of the enable end U6_LE of U6 and the second latch U7, output end U3_D ground connection；
The input terminal U4_A connection of the third NOT gate U4 sends the input terminal of enabled foot DE, the second rest-set flip-flop U12
The input terminal U8_A of one end of U12_RD, the 9th resistance R9, output end U4_Y connection first or door U8；9th resistance R9's is another
End ground connection；
Described first connect the input terminal of one end of the 4th resistance R4, the first latch U6 with the input terminal U5_A of door U5
One end of the output end U9_Y of U6_D, the first tri-state gate U9, input terminal U5_B connection 3rd resistor R3, the second latch U7 it is defeated
Enter to hold the output end U11_Y of U7_D, the second tri-state gate U11；The other end of 4th resistance R4, the other end of 3rd resistor R3 connect
Connect VCC supply lines；
The enable end U11_OE of output end U6_Q the second tri-state gate of connection U11 of the first latch U6；
The enable end U9_OE of output end U7_Q the first tri-state gate of connection U9 of the second latch U7；
The input terminal U8_B connection of described first or door U8 sends input pin DI, one end of twelfth resistor R12, difference
The input terminal U15_DI of transmitter U15, the signal end U12_CP of output end U8_Y the second rest-set flip-flop of connection U12；12nd electricity
The other end for hindering R12 connects VCC supply lines；
One end of the 6th resistance R6 of input terminal U9_A connection of the first tri-state gate U9, the first differential receiver U13
The input terminal U10_A of output end U13_RO, the first XOR gate U10；The other end of 6th resistance R6 connects VCC supply lines；
One end of the 7th resistance R7 of input terminal U10_B connection of the first XOR gate U10, the second tri-state gate U11 it is defeated
Enter to hold the output end U14_RO of U11_A, the second differential receiver U14；The other end of 7th resistance R7 connects VCC supply lines.
The input terminal U12_SD and output end U12_D of the second rest-set flip-flop U12, which is all connected with, connects VCC supply lines, output
Hold the enable end U15_DE of U12_Q connection differential transmitter U15.
Described 10th one end resistance R10 connects RS-485 bus L2 line, other end ground connection；The 11st resistance R11 connection
RS-485 bus L1 line, other end ground connection.
Second rest-set flip-flop U12 realizes that data start bit starts to send.
This circuit is filtered by RC, removal bus signals it is crossing zero when the erroneous judgement that may cause；By receiving enabled letter
Number, discharge latch signal, reset detection circuit；The level useful signal exported by XOR gate, Time Delay Opening or reset are latched
Signal, reset detection circuit；By receiving output signal, Time Delay Opening latches enable signal；By sending enabled and sending defeated
Enter signal, enable effective high level in transmission and send when data bit is 0 low level using differential transmitter, and locks transmission shape
State, until sending enable signal is invalid low level；By built-in bus pull down resistor, avoid no data transmit when bus by
Disturbance fluctuation.
In the initial state, enabled pin nRE is received, low to be effectively in high level by the 8th resistance R8 of inside, first is poor
Dividing receiver U13 output end U13_RO, the second differential receiver U14 output end U14_RO is high-impedance state, passes through the 6th resistance
R6, the 7th resistance R7 are in high level state, and the first XOR gate U10 exports low level at this time, and the second NOT gate U2 exports low level.
Therefore the first rest-set flip-flop U3 exports high level, and the first latch U6, the second latch U7 are in pass-through state, the first tri-state gate
U9, the second tri-state gate U11 are in opening state, export high level, defeated on receiving output pin RO by first and door U5
High level out, the signal make the signal end U3_CP of the first rest-set flip-flop U3 be in low level state by the first NOT gate U1.It is high
The effective enabled foot DE and the 9th resistance R9 of transmission is in low level, and the output end U12_Q output of the second rest-set flip-flop U12 is
Low level, differential transmitter U15 are in invalid state, and RS-485 bus L1 line, RS-485 bus L2 line pass through interior subordinate at this time
Pull-up resistor keeps low level state.
When the high effective enabled foot DE of transmission is high level, the input terminal U12_RD of the second rest-set flip-flop U12 is high electric
Flat, when sending input pin DI and becoming low level from high level or the input terminal of first or door U8 is low level, and output becomes
For high level, trigger signal from low to high, the second rest-set flip-flop are generated in the signal end U12_CP of the second rest-set flip-flop U12
The output end U12_Q of U12 exports high level, and differential transmitter U15 be in enabled state, the signal on transmission input pin DI by
Differential transmitter U15 is sent to RS-485 bus L1 line, on RS-485 bus L2 line.It is inputted when sending input pin DI input terminal
When for high level, output signal is L1 high level, L2 low level, when sending the input of input pin DI input terminal is low level,
Output signal is L1 low level, L2 high level.
When the low effective enabled pin nRE of reception is low level, the first differential receiver U13, the second differential receiver
U14 is in enabled state, when no data transmission is low level on RS-485 bus L1 line, RS-485 bus L2 line, first
It is high level that differential receiver U13, the second differential receiver U14, which are exported, and back-end circuit state is identical as original state.It receives
Enable signal generates high level via the second NOT gate U2, and the second diode D2 is closed.When bus switchs to transmitting state by invalid state,
First data is to be fixed as signal " 0 ", i.e. transmitting terminal L1 low level, L2 high level, if the mode of connection is direct-connected, i.e. L1-
L1, L2-L2, the first differential receiver U13 output end U13_RO is low level, the second differential receiver U14 output end at this time
U14_RO is high level, and two-way receives signal and passes through the first tri-state gate U9 in the open state, the second tri-state gate U11 respectively,
To first and door U5, low level is exported on receiving output pin RO.Because the first latch U6, the second latch U7 are equal at this time
In the open state, so the first latch U6 output is low level, the second latch U7 output is high level, the first tri-state gate
U9 is kept open, and the second tri-state gate U11 is in close state, and is exported and is continued to keep by 3rd resistor R3 for high-impedance state
For high level.The signal generates high level by the first NOT gate U1 simultaneously, and first diode D1 is closed, and first resistor R1 starts
To first capacitor C1 electricity.Meanwhile the output signal of the first differential receiver U13, the second differential receiver U14 are in the first XOR gate
U10 output end generates high level, charges via the 5th resistance R5 to the second capacitor C2, the input terminal U3_ of the first rest-set flip-flop U3
SD voltage gradually rises to high level.Because of time constant t in circuit parameter settingC1>tC2, so when the first rest-set flip-flop U3's
When signal end U3_CP voltage reaches high level threshold values, the level of input terminal U3_SD has been high level, generates trigger signal,
Low level is exported in its output end U3_Q, the first latch U6, the second latch U7 are set to latch mode, by the first tri-state gate
U9 locking is in an open state, and the second tri-state gate U11 locking is in off state.If the mode of connection is to intersect, i.e. L1-L2, L2-
L1, then the first differential receiver U13 output end U13_RO is high level, and the second differential receiver U14 output end U14_RO is low
First tri-state gate U9 locking is finally in off state, the second tri-state gate U11 is locked as open shape by level by above-mentioned logic
State.
When data receiver completion, the low effective enabled pin nRE of reception is set to invalid state (high level), the first difference
Receiver U13, the second differential receiver U14 are in invalid state, export as high-impedance state, output end U13_RO, output end U14_
RO remains high level by pull-up resistor, and the first XOR gate U10 exports low level, the second capacitor C2 electric discharge, the second diode D2
Conducting, the first rest-set flip-flop U3 are set to 1, and the first latch U6, the second latch U7 are in the open state, and circuit reverts to initially
State.
In foregoing circuit description, when the second capacitor C2 delay circuit is to eliminate bus data displacement, because of differential receiver
To the difference of high and low level threshold values, the short time can be generated with level output, circuit is caused to be judged by accident.First capacitor C1 delay circuit
It is to guarantee that input terminal U3_SD is when the signal end U3_CP of the first rest-set flip-flop U3 generates rising edge trigger signal
In reliable high level state, guarantee trigger circuit reliably working.
In foregoing circuit description, receives enabled pin nRE (low effective) and connect via the second NOT gate U2 and the second diode D2
It is connected to the input terminal U3_SD of the first rest-set flip-flop U3, is to enable pin nRE by receiving when bus has data transmission
The first latch U6, the second latch U7 are discharged, circuit is made to restPose, with the delay control from the first XOR gate U10
Signal processed is logical AND.
In foregoing circuit, it is t that time constant, which is arranged, in delay circuit R1+C11It is normal that the time is arranged in=2 μ s, delay circuit R5+C2
Number is t2=1μs。
Increase: 1. delay circuit times；2. automatic direction controlling function.
The present invention is illustrated according to embodiment, under the premise of not departing from present principles, if the present apparatus can also make
Dry modification and improvement.It should be pointed out that it is all using modes technical solutions obtained such as equivalent substitution or equivalent transformations, all fall within this
In the protection scope of invention.
Claims (3)
1. a kind of nonpolarity RS-485 transceiver, including RS-485 bus L1 line, RS-485 bus L2 line, to receive RS-485
The receiver of bus signals and to the driver to RS-485 bus transfer signal；It is characterized by further comprising: the first electricity
Hinder (R1), second resistance (R2), 3rd resistor (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th
Resistance (R7), the 8th resistance (R8), first diode (D1), the second diode (D2), third diode (D3), first capacitor
(C1), the second capacitor (C2), the first NOT gate (U1), the second NOT gate (U2), the first rest-set flip-flop (U3), first with door (U5), the
One latch (U6), the first tri-state gate (U9), the first XOR gate (U10), the second tri-state gate (U11), connects the second latch (U7)
It receives output pin (RO), receive enabled pin (nRE), VCC supply lines；
The receiver includes the first differential receiver (U13) and the second differential receiver (U14)；
First differential receiver (U13), including input terminal U13_A, input terminal U13_B, output end U13_RO and enable end
U13_RE；
Second differential receiver (U14), including input terminal U14_A, input terminal U14_B, output end U14_RO and enable end
U14_RE；
The driver includes differential transmitter (U15),
The differential transmitter (U15) includes input terminal U15_DI, output end U15_A, output end U15_B and enable end U15_
DE；
The input terminal U14_B and difference of the input terminal U13_A of first differential receiver (U13), the second differential receiver (U14)
The output end U15_A of transmitter (U15) is divided to be all connected with RS-485 bus L2；
Input terminal U13_B, the input terminal U14_A of the second differential receiver (U14), difference of first differential receiver (U13)
The output end U15_B of transmitter (U15) is divided to be all connected with RS-485 bus L1 line；
First NOT gate (U1), including input terminal U1_A and output end U1_Y；
Second NOT gate (U2), including input terminal U2_A and output end U2_Y；
First rest-set flip-flop (U3), including signal end U3_CP, input terminal U3_SD, input terminal U3_RD, output end U3_Q,
Output end U3_D；
Described first with door (U5), including input terminal U5_A, input terminal U5_B and output end U5_Y；
First latch (U6), including enable end U6_LE, input terminal U6_D, output end U6_Q；
Second latch (U7), including enable end U7_LE, input terminal U7_D, output end U7_Q；
First tri-state gate (U9), including input terminal U9_A, output end U9_Y and enable end U9_OE；
First XOR gate (U10), including input terminal U10_A, input terminal U10_B, output end U10_Y；
Second tri-state gate (U11), including input terminal U11_A, output end U11_Y and enable end U11_OE；
The input terminal U1_A connection of first NOT gate (U1) receive output pin (RO) and first and door (U5) output end U5_
Y；The output end of the output end U1_Y connection first diode (D1) of first NOT gate (U1)；The first diode (D1)
Input terminal connect the one end of first resistor (R1), one end of first capacitor (C1), the first rest-set flip-flop (U3) signal end U3_
CP；The other end of first resistor (R1) connects VCC supply lines；The other end of first capacitor (C1) is grounded；
The input terminal U2_A connection of second NOT gate (U2) receives enabled pin (nRE), the two or two pole of output end U2_Y connection
Manage the output end of (D2)；One end of input terminal connection second resistance (R2) of second diode (D2), the first rest-set flip-flop
(U3) input terminal of input terminal U3_SD, third diode (D3)；The other end connection connection VCC power supply of second resistance (R2)
Line；One end of the output end connection the second capacitor (C2) of third diode (D3) and one end of the 5th resistance (R5)；Second capacitor
(C2) other end ground connection；The output end U10_Y of the other end connection the first XOR gate (U10) of 5th resistance (R5)；
The input terminal U3_RD connection VCC supply lines of first rest-set flip-flop (U3), output end U3_Q the first latch of connection
(U6) the enable end U7_LE of enable end U6_LE and the second latch (U7), output end U3_D ground connection；
Described first connect one end of the 4th resistance (R4), the input terminal of the first latch (U6) with the input terminal U5_A of door (U5)
The output end U9_Y of U6_D, the first tri-state gate (U9), one end of input terminal U5_B connection 3rd resistor (R3), the second latch
(U7) the output end U11_Y of input terminal U7_D, the second tri-state gate (U11)；The other end of 4th resistance (R4), 3rd resistor
(R3) the other end is all connected with VCC supply lines；
The enable end U11_OE of output end U6_Q the second tri-state gate of connection (U11) of first latch (U6)；
The enable end U9_OE of output end U7_Q the first tri-state gate of connection (U9) of second latch (U7)；
One end of the 6th resistance (R6) of input terminal U9_A connection of first tri-state gate (U9), the first differential receiver (U13)
Output end U13_RO, the first XOR gate (U10) input terminal U10_A；The other end connection VCC power supply of 6th resistance (R6)
Line；
One end of the 7th resistance (R7) of input terminal U10_B connection of first XOR gate (U10), the second tri-state gate (U11)
The output end U14_RO of input terminal U11_A, the second differential receiver (U14)；The other end connection VCC power supply of 7th resistance (R7)
Line；
8th resistance one end (R8) is connect with VCC supply lines, the other end and reception enabled pin nRE, the first differential received
The enable end U14_RE connection of the enable end U13_RE and the second differential receiver (U14) of device (U13).
2. a kind of nonpolarity RS-485 transceiver as described in claim 1, which is characterized in that further include the 10th resistance (R10)
With the 11st resistance (R11)；10th resistance one end (R10) connects RS-485 bus L2 line, other end ground connection；11st electricity
It hinders (R11) and connects RS-485 bus L1 line, other end ground connection.
3. a kind of nonpolarity RS-485 transceiver as described in claim 1, which is characterized in that further include: send enabled foot
(DE), transmission input pin (DI), third NOT gate (U4), first or door (U8), the second rest-set flip-flop (U12), the 9th resistance
(R9), twelfth resistor (R12)；
The third NOT gate (U4), including input terminal U4_A and output end U4_Y；
Described first or door (U8), including input terminal U8_A, input terminal U8_B and output end U8_Y；
Second rest-set flip-flop (U12), including signal end U12_CP, input terminal U12_SD, input terminal U12_RD, output end
U12_Q, output end U12_D；
The input terminal U4_A connection of the third NOT gate (U4) sends the input terminal of enabled foot (DE), the second rest-set flip-flop (U12)
The input terminal U8_A of one end of U12_RD, the 9th resistance (R9), output end U4_Y connection first or door (U8)；9th resistance (R9)
The other end ground connection；
Described first or door (U8) input terminal U8_B connection send input pin (DI), one end of twelfth resistor (R12), difference
Divide the input terminal U15_DI, the signal end U12_CP of output end U8_Y the second rest-set flip-flop of connection (U12) of transmitter (U15)；The
The other end of 12 resistance (R12) connects VCC supply lines；
The input terminal U12_SD and output end U12_D of second rest-set flip-flop (U12), which are all connected with, connects VCC supply lines, output end
The enable end U15_DE of U12_Q connection differential transmitter (U15).
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| CN112838972B (en) * | 2020-12-31 | 2022-05-27 | 广州航天海特系统工程有限公司 | Enabling control method, device and equipment based on RS-485 transceiver and storage medium |
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