CN102169472B - RS485 bus interface circuit - Google Patents
RS485 bus interface circuit Download PDFInfo
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- CN102169472B CN102169472B CN 201110127432 CN201110127432A CN102169472B CN 102169472 B CN102169472 B CN 102169472B CN 201110127432 CN201110127432 CN 201110127432 CN 201110127432 A CN201110127432 A CN 201110127432A CN 102169472 B CN102169472 B CN 102169472B
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Abstract
The invention relates to the technical field of communication of RS485 buses, in particular to an RS485 bus interface circuit. The technical scheme is that: a differential signal transmission circuit section of an RS485 interface consists of a triode inverter, two sets of push-pull type inverting amplifiers and four triple gates, wherein the output end of the triode inverter is connected to the two push-pull signal input ends of a first set of push-pull type inverting amplifier through a first triple gate and a second triple gate respectively; the output end of the first set of push-pull typeinverting amplifier is connected with a first differential signal wire RS485A; and a direct signal of a second set of push-pull type inverting amplifier is communicated with the input end of the triode inverter and a second differential signal wire RS485B. Through the two sets of push-pull type inverting amplifiers, an RS485 differential signal can be output, and the power of an output signal is effectively improved, so that the communication distance in the scheme can reach 2,000 m, 64 transceivers can be hung, and the communication rate can reach 9,600 bps.
Description
Technical field
The present invention relates to RS485 bus communication technical field, relate in particular to a kind of RS485 bus interface circuit.
Background technology
RS485 is a kind of widely used communication protocol, its principal feature is that the electric signal with difference form carries out data transmission, namely, on paired order wire, by adopting a pair of equal and opposite in direction, opposite polarity symmetric signal to carry out the information transmission, this kind data transmission scheme can effectively be resisted outside common mode interference, has stronger antijamming capability.Mostly existing RS485 communication interface scheme is to adopt conventional RS485 interface chip to realize, adopt conventional RS485 interface chip, because the signal of communication output power of chip is standardized designs, at the communication situation remote, that electromagnetic environment is abominable, its traffic rate, interference free performance and the number that hangs over transceiver all can not satisfy the communications demand of these special occasions.
Summary of the invention
At the deficiency of prior art scheme, the present invention proposes a kind of RS485 bus interface circuit that is applicable to the communication situation remote, that electromagnetic environment is abominable.
The technical solution used in the present invention is as follows:
A kind of RS485 bus interface circuit comprises:
One differential signal transtation mission circuit, this differential signal transtation mission circuit comprises: a triode phase inverter, two groups of push-pull type inverting amplifiers and four triple gates, wherein, the input termination data sending terminal of described triode phase inverter, the output terminal of described triode phase inverter is connected to two push-pull signal input ends of first group of push-pull type inverting amplifier respectively by first triple gate and second triple gate, first differential signal line of output termination RS485A of this first group of push-pull type inverting amplifier, the input end of the 3rd triple gate and the 4th triple gate is connected in the input end of described triode phase inverter, the output terminal of described the 3rd triple gate and the 4th triple gate connects two push-pull signal input ends of second group of push-pull type inverting amplifier respectively, second differential signal line of output termination RS485B of this second group of push-pull type see-saw circuit.
One differential signal receiving circuit, this difference letter back receiving circuit comprises: a differential amplifier and a triple gate, wherein, the in-phase input end of described differential amplifier is connected to first differential signal line RS485A, the inverting input of described differential amplifier is connected to second differential signal line RS485B, and the output terminal of described differential amplifier is connected to data receiver by the triple gate of this differential signal receiving circuit.
One data transmit-receive control circuit, this data transmit-receive control circuit comprises a triode phase inverter, the input termination data transmit-receive control end of this triode phase inverter, the input end of this triode phase inverter also is connected to the control Enable Pin of triple gate in the described differential signal receiving circuit, the control Enable Pin of triple gate in the described differential signal transtation mission circuit of the output termination of this triode phase inverter.
Further, the triple gate of described differential signal transtation mission circuit and differential signal receiving circuit all is triple gates that low level control enables, the input end of the triode phase inverter of described data transmit-receive control circuit is connected to the low level of described differential signal receiving circuit and controls the control end that enables that enables triple gate, the output terminal of this triode phase inverter is connected to four low levels of described differential signal transtation mission circuit and controls the control end that enables that enables triple gate, perhaps, the triple gate of described differential signal transtation mission circuit and differential signal receiving circuit all is triple gates that high level control enables, the output terminal of the triode phase inverter of described data transmit-receive control circuit is connected to the high level of described differential signal receiving circuit and controls the control end that enables that enables triple gate, and the input end of this triode phase inverter is connected to four high level of described differential signal transtation mission circuit and controls the control end that enables that enables triple gate.
Further, on described first differential signal line RS485A and second differential signal line RS485B, also comprise: a circuit protection circuit and an impedance matching circuit, this circuit protection circuit comprises: fuse F1 and F2, common mode inductance L1 and L2, glass discharge vessel V1-V3, two-way TVS pipe D1-D3, signal current-limiting resistance R20-R21, wherein, the end of incoming cables of the termination differential signal line RS485A of fuse F1, the end of incoming cables of the termination differential signal line RS485B of fuse F2, the end of the described glass discharge vessel V1 of another termination of described fuse F1, and be connected to the end of described two-way TVS pipe D1 and the end of described signal current-limiting resistance R20 by described common mode inductance L1, the other end of the described glass discharge vessel V1 of another termination of described fuse F2, and be connected to the other end of described two-way TVS pipe D1 and the end of described signal current-limiting resistance R21 by described common mode inductance L2, described glass discharge vessel V2 and glass discharge vessel V3 are the two ends that are connected in described two-way TVS pipe D1 after the series connection again, the intermediate connection point ground connection of this glass discharge vessel V2 and glass discharge vessel V3, described two-way TVS pipe D2 and two-way TVS pipe D3 are connected in the other end of described signal current-limiting resistance R20 and the other end of signal current-limiting resistance R21 after the series connection again, the intermediate connection point ground connection of this two-way TVS pipe D2 and two-way TVS pipe D3, the other end of described signal current-limiting resistance R20 is the leading-out terminal of this circuit protection circuit differential signal line RS485A, and the other end of described signal current-limiting resistance R21 is the leading-out terminal of this circuit protection circuit differential signal line RS485B; Described impedance matching circuit comprises: the biasing resistor R1 that electrically connects described first differential signal line RS485A leading-out terminal and 5V power supply, two ends are connected in the impedance matching resistance R 2 of described first differential signal line RS485A leading-out terminal and described second differential signal line RS485B leading-out terminal, electrically connect the biasing resistor R3 of described second differential signal line RS485B leading-out terminal and ground wire.
The present invention is by adopting technique scheme, the beneficial effect that has is: realize signal output by two groups of push-pull type inverting amplifiers of described differential signal transtation mission circuit, promoted the power of output signal effectively, make the communication distance of this scheme can reach 2000 meters, the transceiver that can articulate can reach 64, and speed letter speed can reach 9600bps.
Description of drawings
Fig. 1 is the circuit theory diagrams of a preferred embodiment of the present invention.
Embodiment
Now the invention will be further described with embodiment by reference to the accompanying drawings.
As shown in Figure 1, RS485 bus interface circuit of the present invention is by constituting with the lower part:
One differential signal transtation mission circuit 1, this differential signal transtation mission circuit 1 comprises: a triode phase inverter 101, two groups of push-pull type inverting amplifier 102A and 102B, triple gate U1, U2, U3 and U4, wherein, the input end of described triode phase inverter 101 is connected to data sending terminal, its output terminal is connected to two push-pull signal input ends of described push-pull type inverting amplifier 102A respectively by described triple gate U1 and triple gate U2, first differential signal line of output termination RS485A of described push-pull type inverting amplifier 102A, the input end of described triple gate U3 and triple gate U4 is connected in the input end of described triode phase inverter 101, two push-pull signal input ends of its described push-pull type inverting amplifier of output termination 102B separately, second differential signal line of output termination RS485B of this push-pull type see-saw circuit 102B; When need send data, transmitting-receiving control end output high level, this high level signal is controlled triple gate U1 after the triode phase inverter of data transmit-receive control circuit 3 is anti-phase, U2, U3 and U4 conducting, when the signal that sends is high level, described triode Q4 conducting of recommending among the inverting amplifier 102B, be described second differential signal line RS485B ground connection, described triode Q1 conducting of recommending among the inverting amplifier 102A, be that described second differential signal line RS485A is connected to+power supply of 5V, the differential signal of generation+5V between differential signal line RS485A and the differential signal line RS485B then, in like manner, when the signal that sends is low level, the differential signal of generation-5V between differential signal line RS485A and the differential signal line RS485B.
One differential signal receiving circuit 2, this difference letter back receiving circuit 2 comprises: a differential amplifier 201 and a triple gate U5, wherein, the in-phase input end of described differential amplifier 201 meets first differential signal line RS485A, its inverting input is connected to second differential signal line RS485B, and its output terminal connects data receiver by the triple gate U5 of this differential signal receiving circuit; Wherein, described differential amplifier 201 is open-collector high-speed comparator LM311, when the signal level on first differential signal line RS485A is higher than second signal level on the differential signal line RS485B, high-speed comparator LM311 exports high level, otherwise, high-speed comparator LM311 output low level, when the transmitting-receiving control end is low level, triple gate U5 conducting, at this moment, the differential signal of differential signal line RS485A and differential signal line RS485B is converted to serial data by high-speed comparator LM311 and delivers to data receiver.
One data transmit-receive control circuit 3, this data transmit-receive control circuit 3 comprises a triode phase inverter, the input termination data transmit-receive control end of this triode phase inverter, its input end and output terminal connect the control Enable Pin of triple gate in described differential signal transtation mission circuit 1 and the differential signal receiving circuit 2 respectively.
Data transmit-receive control circuit 3 of the present invention has following embodiment:
Embodiment 1: the triple gate U1-triple gate U5 of described differential signal transtation mission circuit 1 and differential signal receiving circuit 2 all is triple gates that high level control enables, the output terminal of the triode phase inverter of this data transmit-receive control circuit 3 is connected to the high level of described differential signal receiving circuit 2 and controls the control end that enables that enables triple gate U5, and the input end of this triode phase inverter is connected to four high level of described differential signal transtation mission circuit 1 and controls the control end that enables that enables triple gate U1-U4; Though this embodiment can be realized the transmitting-receiving control of data, yet, the high driving ability that the output terminal of triode phase inverter has, the high level control that connects differential signal receiving circuit 2 enables the control end that enables of triple gate U5, the control end that enables that four high level controls of differential signal transtation mission circuit 1 enable triple gate U1-U4 but is directly to be driven by the data transmit-receive control end, data transmit-receive control end ground driving force is limited originally, and therefore, this embodiment is also unreasonable.
Embodiment 2: in this embodiment, the triple gate U1-U4 of described differential signal transtation mission circuit 1 all is triple gates that high level control enables, the triple gate U5 of described differential signal receiving circuit 2 is triple gates that low level control enables, at this moment, this data transmit-receive control circuit is the control Enable Pin that the data transmit-receive control end directly meets the triple gate U5 that low level control enables in triple gate U1-U4 that the control of high level in the described differential signal transtation mission circuit 1 enables and the described differential signal receiving circuit 2; Though this embodiment can be realized data transmit-receive control function, its data transmit-receive end connects the control Enable Pin of 5 triple gate U1-U5 simultaneously, and factor easily produces the misoperation of transmitting-receiving control according to ground, sending and receiving end driving force deficiency.
Embodiment 3: this embodiment is preferred implementation of the present invention, wherein, the triple gate U1-triple gate U5 of described differential signal transtation mission circuit 1 and differential signal receiving circuit 2 all is triple gates that high level control enables, the output terminal of the triode phase inverter of this data transmit-receive control circuit 3 is connected to the high level of described differential signal receiving circuit 2 and controls the control end that enables that enables triple gate U5, and the input end of this triode phase inverter is connected to four high level of described differential signal transtation mission circuit 1 and controls the control end that enables that enables triple gate U1-U4; Like this, when the transmitting-receiving control end receives with high level control data, this high level signal is anti-phase by the triode phase inverter, and output low level control triple gate U1, U2, U3, U4 conducting have also improved and receive and dispatch the driving force that control end drives a plurality of triple gate U1, U2, U3, U4 simultaneously.
As the present invention one preferred embodiment, on described first differential signal line RS485A and second differential signal line RS485B, also comprise: a circuit protection circuit 4 and an impedance matching circuit 5, this circuit protection circuit 4 comprises: fuse F1 and F2, common mode inductance L1 and L2, glass discharge vessel V1-V3, two-way TVS pipe D1-D3, signal current-limiting resistance R20-R21, wherein, the end of incoming cables of the termination differential signal line RS485A of fuse F1, the end of incoming cables of the termination differential signal line RS485B of fuse F2, the end of the described glass discharge vessel V1 of another termination of described fuse F1, and be connected to the end of described two-way TVS pipe D1 and the end of described signal current-limiting resistance R20 by described common mode inductance L1, the other end of the described glass discharge vessel V1 of another termination of described fuse F2, and be connected to the other end of described two-way TVS pipe D1 and the end of described signal current-limiting resistance R21 by described common mode inductance L2, described glass discharge vessel V2 and glass discharge vessel V3 are the two ends that are connected in described two-way TVS pipe D1 after the series connection again, the intermediate connection point ground connection of this glass discharge vessel V2 and glass discharge vessel V3, described two-way TVS pipe D2 and two-way TVS pipe D3 are connected in the other end of described signal current-limiting resistance R20 and the other end of signal current-limiting resistance R21 after the series connection again, the intermediate connection point ground connection of this two-way TVS pipe D2 and two-way TVS pipe D3, the other end of described signal current-limiting resistance R20 is the leading-out terminal of this circuit protection circuit differential signal line RS485A, and the other end of described signal current-limiting resistance R21 is the leading-out terminal of this circuit protection circuit differential signal line RS485B; Described impedance matching circuit comprises: the biasing resistor R1 that electrically connects described first differential signal line RS485A leading-out terminal and 5V power supply, two ends are connected in the impedance matching resistance R 2 of described first differential signal line RS485A leading-out terminal and described second differential signal line RS485B leading-out terminal, electrically connect the biasing resistor R3 of described second differential signal line RS485B leading-out terminal and ground wire; The present invention is by adopting above-mentioned circuit protection circuit; glass discharge vessel V1, V2 and V3 can carry out clamped to high-voltage signal effectively; common mode inductance L1 and L2 both can suppress outside EMI signal and import into; the EMI signal that produces during the circuit self of can decaying again work can reduce the EMI interference strength effectively.
Although specifically show and introduced the present invention in conjunction with preferred embodiment; but the those skilled in the art should be understood that; in not breaking away from the spirit and scope of the present invention that appended claims limits; can make a variety of changes the present invention in the form and details, be protection scope of the present invention.
Claims (4)
1. RS485 bus interface circuit comprises:
One differential signal transtation mission circuit, this differential signal transtation mission circuit comprises: a triode phase inverter, two groups of push-pull type inverting amplifiers and four triple gates, wherein, the input termination data sending terminal of described triode phase inverter, the output terminal of described triode phase inverter is connected to two push-pull signal input ends of first group of push-pull type inverting amplifier respectively by first triple gate and second triple gate, first differential signal line of output termination RS485A of this first group of push-pull type inverting amplifier, the input end of the 3rd triple gate and the 4th triple gate is connected in the input end of described triode phase inverter, the output terminal of described the 3rd triple gate and the 4th triple gate connects two push-pull signal input ends of second group of push-pull type inverting amplifier respectively, second differential signal line of output termination RS485B of this second group of push-pull type see-saw circuit;
One differential signal receiving circuit, this difference letter back receiving circuit comprises: a differential amplifier and a triple gate, wherein, the in-phase input end of described differential amplifier is connected to first differential signal line RS485A, the inverting input of described differential amplifier is connected to second differential signal line RS485B, and the output terminal of described differential amplifier is connected to data receiver by the triple gate of this differential signal receiving circuit;
One data transmit-receive control circuit, this data transmit-receive control circuit comprises a triode phase inverter, the input termination data transmit-receive control end of this triode phase inverter, the input end of this triode phase inverter also is connected to the control Enable Pin of triple gate in the described differential signal receiving circuit, the control Enable Pin of triple gate in the described differential signal transtation mission circuit of the output termination of this triode phase inverter.
2. RS485 bus interface circuit as claimed in claim 1, it is characterized in that: the triple gate of described differential signal transtation mission circuit and differential signal receiving circuit all is triple gates that low level control enables, the input end of the triode phase inverter of described data transmit-receive control circuit is connected to the low level of described differential signal receiving circuit and controls the control end that enables that enables triple gate, and the output terminal of this triode phase inverter is connected to four low levels of described differential signal transtation mission circuit and controls the control end that enables that enables triple gate.
3. RS485 bus interface circuit as claimed in claim 1, it is characterized in that: the triple gate of described differential signal transtation mission circuit and differential signal receiving circuit all is triple gates that high level control enables, the output terminal of the triode phase inverter of described data transmit-receive control circuit is connected to the high level of described differential signal receiving circuit and controls the control end that enables that enables triple gate, and the input end of this triode phase inverter is connected to four high level of described differential signal transtation mission circuit and controls the control end that enables that enables triple gate.
4. as claim 1 or 2 or 3 described RS485 bus interface circuits, it is characterized in that: on described first differential signal line RS485A and second differential signal line RS485B, also comprise: a circuit protection circuit and an impedance matching circuit, this circuit protection circuit comprises: fuse F1 and F2, common mode inductance L1 and L2, glass discharge vessel V1-V3, two-way TVS pipe D1-D3, signal current-limiting resistance R20-R21, wherein, the end of incoming cables of the termination differential signal line RS485A of fuse F1, the end of incoming cables of the termination differential signal line RS485B of fuse F2, the end of the described glass discharge vessel V1 of another termination of described fuse F1, and be connected to the end of described two-way TVS pipe D1 and the end of described signal current-limiting resistance R20 by described common mode inductance L1, the other end of the described glass discharge vessel V1 of another termination of described fuse F2, and be connected to the other end of described two-way TVS pipe D1 and the end of described signal current-limiting resistance R21 by described common mode inductance L2, described glass discharge vessel V2 and glass discharge vessel V3 are the two ends that are connected in described two-way TVS pipe D1 after the series connection again, the intermediate connection point ground connection of this glass discharge vessel V2 and glass discharge vessel V3, described two-way TVS pipe D2 and two-way TVS pipe D3 are connected in the other end of described signal current-limiting resistance R20 and the other end of signal current-limiting resistance R21 after the series connection again, the intermediate connection point ground connection of this two-way TVS pipe D2 and two-way TVS pipe D3, the other end of described signal current-limiting resistance R20 is the leading-out terminal of this circuit protection circuit differential signal line RS485A, and the other end of described signal current-limiting resistance R21 is the leading-out terminal of this circuit protection circuit differential signal line RS485B; Described impedance matching circuit comprises: the biasing resistor R1 that electrically connects described first differential signal line RS485A leading-out terminal and 5V power supply, two ends are connected in the impedance matching resistance R 2 of described first differential signal line RS485A leading-out terminal and described second differential signal line RS485B leading-out terminal, electrically connect the biasing resistor R3 of described second differential signal line RS485B leading-out terminal and ground wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110127432 CN102169472B (en) | 2011-05-17 | 2011-05-17 | RS485 bus interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110127432 CN102169472B (en) | 2011-05-17 | 2011-05-17 | RS485 bus interface circuit |
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| CN102169472A CN102169472A (en) | 2011-08-31 |
| CN102169472B true CN102169472B (en) | 2013-10-09 |
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| CN 201110127432 Expired - Fee Related CN102169472B (en) | 2011-05-17 | 2011-05-17 | RS485 bus interface circuit |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521193B (en) * | 2011-12-30 | 2015-03-11 | 无锡新硅微电子有限公司 | Nonpolar RS-485 interface circuit |
| CN103873104B (en) * | 2014-04-08 | 2016-08-24 | 深圳麦克维尔空调有限公司 | A kind of host communication circuit and communication system |
| CN108155919B (en) * | 2017-12-29 | 2019-09-10 | 甄荣国 | A kind of nonpolarity RS-485 transceiver |
| CN108305467A (en) * | 2018-03-13 | 2018-07-20 | 中国电子科技集团公司第三十八研究所 | A kind of bicycle road entrance vehicle flow detection system based on self-identifying |
| CN110196828A (en) * | 2019-05-28 | 2019-09-03 | 深圳市雷赛软件技术有限公司 | Support the communicating circuit and the means of communication of RS485 half-duplex protocol |
| CN111522720B (en) * | 2020-05-08 | 2022-02-22 | 深圳智微电子科技有限公司 | RS485 interface access state detection circuit and detection method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005051496A (en) * | 2003-07-28 | 2005-02-24 | Kanji Otsuka | Signal transmission system and signal transmission line |
| FR2916872A1 (en) * | 2007-05-29 | 2008-12-05 | Schneider Electric Ind Sas | DEVICE FOR CONTROLLING POINT-TO-POINT COMMUNICATION BETWEEN A MODULE AND A TRANSMISSION BUS |
| CN201097311Y (en) * | 2007-09-07 | 2008-08-06 | 海尔集团公司 | Induction signal transmission circuit |
| CN102033843B (en) * | 2010-12-02 | 2012-08-01 | 西北工业大学 | Direct interface method of RS485 bus and high-speed intelligent unified bus |
| CN202126687U (en) * | 2011-05-17 | 2012-01-25 | 福建省万华电子科技有限公司 | RS485 bus interface circuit |
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Denomination of invention: RS485 bus interface circuit Effective date of registration: 20170214 Granted publication date: 20131009 Pledgee: Industrial Bank Limited by Share Ltd Quanzhou branch Pledgor: Fujian Wanhua Electronics & Technology Co., Ltd. Registration number: 2017350000022 |
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