WO2020232582A1

WO2020232582A1 - Integrated circuit having interface multiplexing functionality and pin switching method

Info

Publication number: WO2020232582A1
Application number: PCT/CN2019/087464
Authority: WO
Inventors: 刘文学; 朱志军; 彭亢; 黄宽; 曾令慧; 黄观冰
Original assignee: 华为技术有限公司
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2020-11-26
Also published as: CN113383326A

Abstract

Disclosed in embodiments of the present application is an integrated circuit having interface multiplexing functionality, comprising: multiple functional modules, a first pin, a switching circuit and a control circuit, the multiple functional modules providing interface functionality by means of the first pin of the integrated circuit, so as to provide external device access to the integrated circuit; the multiple functional modules multiplex the first pin by means of the switching circuit, so as to cause the integrated circuit to communicate with external devices corresponding to each of the multiple functional modules by means of the first pin; the control circuit is used to control the switching circuit to connect a target functional module to the first pin. By means of the present solution, it is possible to cause multiple functional modules to multiplex the first pin by means of the switching circuit, and to control the switching circuit by means of the control circuit; therefore, it is not necessary for each functional module to be provided with a corresponding pin, decreasing a number of pins, which can thereby lower a chip cost and decrease chip volume.

Description

Integrated circuit with interface multiplexing function and pin switching method

Technical field

This application relates to the technical field of terminal equipment, and in particular to an integrated circuit with an interface multiplexing function and a pin switching method.

Background technique

In order to realize multiple functions of the chip, multiple functional modules are usually integrated inside the chip. For example, referring to the schematic structural diagram of the chip shown in Figure 1, in order to realize the communication between the chip and the external devices of the chip, a universal asynchronous receiver/transmitter (UART) controller and an integrated circuit interconnection bus ( inter-integrated circuit, I2C) controller, etc., where the UART controller can communicate with the UART device outside the chip, and the I2C controller can communicate with the I2C device outside the chip; in addition, in order to meet the needs of chip debugging, it is usually still A joint test action group (JTAG) debugging interface is set in the chip to connect to the JTAG debugging device outside the chip through the JTAG debugging interface.

Further, in order to enable each functional module inside the chip to perform corresponding functions, it is also necessary to set corresponding pins for each functional module, so that each functional module can be connected to devices outside the chip through its corresponding pins. For example, as shown in Figure 1, the three functional modules of the UART controller, I2C controller and JTAG debug interface inside the chip are respectively set with corresponding pins, and each functional module is connected to the external device through its own corresponding pins. . In addition, in Figure 1, TXD/RXD represents the interface signal of the UART controller, SDA/SCL represents the interface signal of the I2C controller, and TMS/TCK represents the interface signal of the JTAG debug interface.

However, the inventor found in the research process of this application that since it is necessary to set corresponding pins for each functional module in the chip, it is often necessary to set more pins for the chip, which not only leads to higher cost of the chip, but also takes up The large size of the chip is not conducive to the miniaturization of the chip.

Summary of the invention

In order to solve the problems of high chip cost and large chip volume caused by the need to set corresponding pins for each functional module in the chip, the chip is provided with more pins, and the chip is large in size. An integrated circuit with interface multiplexing function and a pin switching method.

The embodiment of the application discloses an integrated circuit with an interface multiplexing function, including: a plurality of functional modules, a first pin, a switching circuit, and a control circuit, the plurality of functional modules provide interfaces through the first pin of the integrated circuit Function for an external device to access the integrated circuit; the multiple functional modules multiplex the first pin through the switching circuit, so that the integrated circuit passes through the external device corresponding to the first pin and the multiple functional modules respectively To communicate; the control circuit is used to control the switching circuit to connect the target function module to the first pin, and the target function module is one of the plurality of function modules.

Through the integrated circuit with interface multiplexing function disclosed in the embodiments of the present application, multiple functional modules can be multiplexed with the first pin through the switching circuit, and the switching circuit can be controlled by the control circuit, thereby reducing the number of pins, thereby Can reduce the cost of the chip, and reduce the size of the chip.

In a feasible design method, the control circuit is specifically used to generate a corresponding switching signal according to preset switching data, and send the switching signal to the switching circuit, so that the switching circuit can set the target according to the switching signal. The functional module is connected to the first pin; wherein the preset switching data is used to indicate the switching mode of the switching circuit.

In a feasible design method, the integrated circuit further includes: a processor; the multiple functional modules include: a debug interface module, and the preset switching data includes: a debug interface switching sequence; in the case that the processor hangs, The control circuit is specifically used for: generating a debugging interface switching signal according to the debugging interface switching sequence; sending the debugging interface switching signal to the switching circuit, so that the switching circuit makes the debugging interface module and the second circuit switch according to the debugging interface switching signal One pin is connected.

In the embodiment of the present application, the debugging interface switching sequence may be pre-stored in a storage area, for example, stored in a non-volatile memory. After the processor hangs up, the control circuit can access the storage area to obtain the debugging interface switching sequence. The switching signal is generated to control the switching circuit to multiplex the first pin as a debugging interface, so that the debugging signal can be received through the first interface to realize the debugging of the processor and restore the processor to normal.

In the embodiment of the present application, when the processor hangs up, the switching circuit and the control circuit can still perform corresponding operations, and the debugging interface switching sequence stored in the storage area will not be affected by the hang up of the processor. In this case, even if the processor hangs up, the control circuit can still obtain the debugging interface switching sequence, and generate the corresponding debugging interface switching signal according to the debugging interface switching sequence, so that the switching circuit can connect the debugging interface module with the debugging interface switching signal according to the debugging interface switching signal. The first pin is connected. Therefore, even if the processor hangs up, the integrated circuit disclosed in the embodiments of the present application can still switch pin functions and implement debugging of the processor.

In a feasible design, the control circuit is coupled to the first pin, and the control circuit is also used to monitor the data transmitted on the first pin; when the processor hangs up, the first tube The pin receives the debugging interface switching sequence sent by the external device; the control circuit is specifically used to: after monitoring the debugging interface switching sequence received by the first pin, generate the debugging interface switching signal according to the debugging interface switching sequence; The debugging interface switching signal is sent to the switching circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.

In the embodiment of this application, the debugging interface switching sequence is sent to the first pin by the external device. The external device may be a personal computer (PC) tool. After the processor hangs up, the debugging is sent through the external device. The interface switching sequence is given to the first pin. After monitoring that the first pin receives the debugging interface switching sequence, the control circuit generates a switching signal to control the switching circuit to multiplex the first pin as a debugging interface, so that the first interface can be used Receive the debugging signal to realize the debugging to the processor, make the processor return to normal.

In a feasible design method, the control circuit includes: a state machine, the number of the state machine is not less than the number of types of the preset switching data, and one preset switching data corresponds to a switching method; the first tube The pin is coupled with the state machine; after acquiring the preset switching data, the target state machine in the state machine generates the switching signal corresponding to the preset switching data, wherein the target state machine is switched to the preset switching data The state machine corresponding to the data.

In a feasible design method, the control circuit includes: a memory, a comparator, and a buffer; the memory and the buffer are both coupled with the comparator, the comparator is coupled with the switching circuit, and the buffer is coupled with The first pin is coupled; the memory is used to store preset switching data; the buffer is used to buffer the data received by the first pin; the comparator is used to store data in the buffer When matching with the preset switching data stored in the memory, the switching signal corresponding to the preset switching data is generated.

In a feasible design manner, the switching circuit includes: a multiplexer; the input end of the multiplexer is coupled to the first pin; after receiving the switching signal, the multiplexer The output terminal of the converter is connected with the target function module.

In a feasible design method, the debugging interface module is a joint test working group JTAG debugging interface or a serial wire debugging SWD interface.

In a feasible design method, the multiple functional modules also include: a circuit interconnect bus I2C controller, a universal asynchronous receiver transmitter UART controller or a serial peripheral SPI interface.

In the second aspect, an embodiment of the present application discloses a pin switching method, which is applied to an integrated circuit with an interface multiplexing function. The integrated circuit includes: a plurality of functional modules, a first pin, a switching circuit, and a control circuit, The plurality of functional modules provide interface functions through the first pin of the integrated circuit for external devices to access the integrated circuit, and the method includes: the plurality of functional modules multiplex the first pin through the switching circuit to Make the integrated circuit communicate with the external devices corresponding to the multiple functional modules through the first pin; the control circuit controls the switching circuit to connect the target functional module to the first pin, and the target functional module is the A functional module among multiple functional modules.

In a feasible design method, the control circuit controls the switching circuit to connect the target function module to the first pin, which includes: the control circuit generates a corresponding switching signal according to preset switching data; the control circuit generates the switching signal Sending to the switching circuit so that the switching circuit connects the target function module with the first pin according to the switching signal.

In a feasible design method, when the integrated circuit further includes a processor, the multiple functional modules include: a debug interface module, and the preset switching data includes: a debug interface switching sequence; the control circuit controls the switching circuit to target The functional module is connected to the first pin and includes: when the processor hangs up, the control circuit generates a debugging interface switching signal according to the debugging interface switching sequence; the control circuit sends the debugging interface switching signal to the switch Circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.

In a feasible design manner, the control circuit is coupled to the first pin, and the method further includes: the control circuit monitors the data transmitted on the first pin; when the processor hangs up, the second One pin receives the debugging interface switching sequence sent by the external device;

The control circuit controls the switching circuit to connect the target function module to the first pin, including: after the control circuit monitors the debugging interface switching sequence received by the first pin, generating the debugging according to the debugging interface switching sequence Interface switching signal; the control circuit sends the debugging interface switching signal to the switching circuit so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.

In a feasible design method, the control circuit generates a corresponding switching signal according to preset switching data, including: the target state machine in the control circuit generates the switching signal corresponding to the preset switching data, wherein the control circuit The state machine includes no less than the number of types of the preset switching data, and the target state machine is a state machine corresponding to the preset switching data.

Through the integrated circuit with interface multiplexing function and the pin switching method disclosed in the embodiments of the present application, multiple functional modules can be multiplexed with the first pin through the switching circuit, and the switching circuit can be controlled by the control circuit, so that the switching circuit Connect the target function module to the first pin. In this case, there is no need to set a corresponding pin for each functional module. Therefore, compared with the prior art, the number of pins is reduced, thereby reducing the cost of the chip. Moreover, as the number of pins is reduced, the volume occupied by the pins is reduced, and accordingly, the volume of the chip is also reduced. Therefore, the integrated circuit with interface multiplexing function disclosed in the embodiments of the present application solves the problems of high chip cost and large chip volume caused by the large number of pins in the chip in the prior art.

Description of the drawings

In order to explain the technical solution of the present application more clearly, the following will briefly introduce the drawings needed in the embodiments. Obviously, for those of ordinary skill in the art, without paying creative labor, Other drawings can be obtained from these drawings.

Fig. 1 is a schematic structural diagram of a chip disclosed in the prior art;

2 is a schematic structural diagram of an integrated circuit with interface multiplexing function disclosed in an embodiment of the application;

FIG. 3 is a schematic diagram of an operation of switching through a preset data sequence in an integrated circuit with an interface multiplexing function disclosed in an embodiment of the application;

4 is a schematic structural diagram of a control circuit in an integrated circuit with interface multiplexing function disclosed in an embodiment of the application;

5 is a schematic structural diagram of another control circuit in the integrated circuit with interface multiplexing function disclosed in an embodiment of the application;

6 is a schematic structural diagram of another control circuit in the integrated circuit with interface multiplexing function disclosed in an embodiment of the application;

FIG. 7 is a schematic diagram of a working flow of a pin switching method disclosed in an embodiment of the application.

Detailed ways

In order to solve the problems of high chip cost and large chip volume caused by the need to set corresponding pins for each functional module in the chip, the chip is provided with more pins, and the chip is large in size. An integrated circuit with interface multiplexing function.

In the first embodiment of the present application, an integrated circuit with interface multiplexing function is disclosed. The integrated circuit can be used as a part of a chip. Refer to Figure 2, which is a schematic structural diagram of an exemplary integrated circuit with interface multiplexing function provided by an embodiment of the application. The integrated circuit with interface multiplexing function disclosed in the embodiment of the application includes: multiple functions The module 100, the first pin 200, the switching circuit 300 and the control circuit 400.

The multiple functional modules 100 provide interface functions through the first pin of the integrated circuit for external devices to access the integrated circuit.

Among them, in the embodiment of the present application, the multiple functional modules 100, the switching circuit 300, and the control circuit 400 are all hardware logic circuits. When an external device needs to access a certain functional module, the external device is connected to the first pin 200, and the first pin 200 can also be connected to the functional module corresponding to the external device in the integrated circuit, so that the external device and the functional module A path is formed to facilitate access to integrated circuits by external devices.

In addition, the multiple functional modules 100 can be multiple types of functional modules, and each type of functional module corresponds to at least one type of external device, and the external device can access the multiple types of modules in the integrated circuit through the pins of the integrated circuit. A functional module to realize the access of external equipment to the integrated circuit.

For example, when it is necessary to perform JTAG debugging on the central processing unit (CPU), the functional module of the JTAG debugging interface provides the interface function through the first pin 200, and the external device of the JTAG debugging device through the first pin 200 is connected with the JTAG debugging interface, so that the JTAG debugging device can access the integrated circuit. Specifically, the JTAG debugging interface module receives the debugging signal sent by the JTAG debugging device through the first pin, so as to realize the JTAG debugging of the CPU.

Or, when data transmission is required, the functional module of the UART controller provides interface functions through the first pin 200, and the UART device, an external device, is connected to the UART controller through the first pin 200, so that the UART device can Visit the integrated circuit. Exemplarily, the UART device includes a keyboard, a mouse, etc., specifically, a UART device such as a keyboard or a mouse can access the CPU in the integrated circuit through the UART controller, input data to the CPU, and receive data sent by the CPU.

Of course, other types of functional modules may also be provided in the integrated circuit, which is not limited in the embodiment of the present application.

The multiple functional modules 100 multiplex the first pin 200 through the switching circuit 300, so that the integrated circuit communicates with the external devices corresponding to the multiple functional modules through the first pin.

When a certain functional module multiplexes the first pin 200 through the switching circuit 300, it means that the functional module is connected to the first pin 200 through the switching circuit 300. In this case, the external device, the first pin 200 A path is formed between the pin 200 and the functional module to facilitate communication between the functional module and external devices.

In an optional situation, the first end of the switching circuit is coupled to the first pin, and the second end of the switching circuit is coupled to the target function module, so that the target function module is connected to the first pin through the switching circuit, thereby Make the first pin externally provide the interface function of the target functional module; in another optional case, the first end of the switching circuit is coupled to the first pin, and the multiple second ends of the switching circuit are respectively coupled to multiple Functional modules, but only the second terminal coupled with the target functional module is connected to the first terminal, and the paths between the other second terminals and the first terminal are disconnected.

The control circuit 400 is used to control the switching circuit 300 to connect the target function module to the first pin 200, and the target function module is one of the plurality of function modules 200.

Wherein, the first end of the control circuit 400 is usually coupled to the first pin 200, and the second end is coupled to the switching circuit 300. When it is necessary to switch the pin function of the first pin, the control circuit 400 will The switching circuit 300 performs control.

Through the integrated circuit with interface multiplexing function disclosed in the embodiments of this application, multiple functional modules can be multiplexed with the first pin through the switching circuit, and the switching circuit can be controlled by the control circuit, so that the switching circuit can connect the target functional module with The first pin is connected. In this case, there is no need to set a corresponding pin for each functional module. Therefore, compared with the prior art, the number of pins is reduced, thereby reducing the cost of the chip. Moreover, as the number of pins is reduced, the volume occupied by the pins is reduced, and accordingly, the volume of the chip is also reduced. Therefore, the integrated circuit with interface multiplexing function disclosed in the embodiments of the present application solves the problems of high chip cost and large chip volume caused by the large number of pins in the chip in the prior art.

In a feasible implementation manner, in the embodiment of the present application, the control circuit 400 is specifically configured to generate a corresponding switching signal according to preset switching data, and send the switching signal to the switching circuit, so that the switching The circuit connects the target function module with the first pin according to the switching signal.

Wherein, the preset switching data is used to indicate the switching mode of the switching circuit.

In one embodiment, the preset switching data is pre-stored in a storage area. When the processor in the chip hangs up, the control circuit 400 can access the storage area to obtain the preset switching data to generate a corresponding switching signal. For example, the control circuit reads the debugging interface switching sequence pre-stored in the storage area and generates a debugging interface switching signal, so that the switching circuit switches the first pin to the debugging interface function, thereby receiving the pair from the debugging device through the first pin. The debug signal of the processor.

In another way, the preset switching data is transmitted to the first pin 200 by the external device, and the control circuit 400 sends the data to the switching circuit after monitoring that the first pin 200 receives the preset switching data. 300 for control.

Further, the integrated circuit also includes a processor. The processor may be a central processing unit CPU or the like.

The multiple functional modules include: a debugging interface module, and the preset switching data includes: a debugging interface switching sequence;

When the processor hangs up, the control circuit is specifically used for:

Generate a debugging interface switching signal according to the debugging interface switching sequence;

The debugging interface switching signal is sent to the switching circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.

When the processor hangs up, it is often necessary to debug the processor. In the process of debugging the processor, the debug interface module needs to receive the debug signal. Therefore, the debug interface module needs to multiplex the debug signal through the switching circuit 300. The first pin 200 allows the debug interface module to receive a debug signal through the first pin, and the debug signal is used to debug the processor.

Among them, in the embodiment of the present application, the switching circuit 300 and the control circuit 400 are logic circuits independent of the processor, and when the processor hangs up, it can still perform its own operations.

Moreover, in the embodiment of the present application, when the processor hangs up, the switching circuit and the control circuit can still perform corresponding operations, and the debugging interface switching sequence stored in the storage area will not be affected by the processor hang up. In this case, even if the processor hangs up, the control circuit can still obtain the debugging interface switching sequence, and generate the corresponding debugging interface switching signal according to the debugging interface switching sequence, so that the switching circuit can switch the debugging interface according to the debugging interface switching signal. The module is connected to the first pin. Therefore, even if the processor hangs up, the integrated circuit disclosed in the embodiments of the present application can still switch pin functions and implement debugging of the processor.

In addition, when the processor hangs up, an external device can also generate a debugging interface switching sequence. In this case, in the embodiment of the present application, the control circuit 400 is coupled to the first pin 200, and the control circuit is also used to monitor the data transmitted on the first pin 200.

When the processor hangs up, the first pin 200 receives the debugging interface switching sequence sent by the external device.

The control circuit 400 is specifically used for:

After monitoring the debugging interface switching sequence received by the first pin 200, generate the debugging interface switching signal according to the debugging interface switching sequence;

The debugging interface switching signal is sent to the switching circuit 300, so that the switching circuit 300 connects the debugging interface module to the first pin 200 according to the debugging interface switching signal.

In the embodiment of the present application, since the control circuit 400 is coupled to the first pin 200, the control circuit 400 can monitor the data received by the first pin 200. In this case, when the control circuit 400 detects that the data transmitted on the first pin 200 is a debugging interface switching sequence, it generates a debugging interface switching signal corresponding to the debugging interface switching sequence, and sets the debugging interface switching signal Send to the switching circuit 300. After the switching circuit 300 receives the debugging interface switching signal, based on the debugging interface switching signal, the debugging interface module is connected to the first pin, so that a connection between the debugging interface module and the first pin is formed. Path, so that the debugging interface module receives the debugging signal transmitted by the debugging device outside the chip through the first pin, and the debugging is completed through the debugging signal.

In the integrated circuit with interface multiplexing function disclosed in the embodiment of the present application, the switching circuit 300 and the control circuit 400 are both logic circuits independent of the processor. When the processor hangs up, the switching circuit 300 and the control circuit The circuits 400 can perform their own operations. In this case, the debugging interface switching sequence can be sent to the first pin 200 through the external device, and the control circuit 400 generates the corresponding debugging interface switching signal after monitoring the debugging interface switching sequence in the first pin. The debugging interface switching signal is transmitted to the switching circuit, and after the switching circuit receives the debugging interface switching signal, the debugging interface module is connected to the first pin.

That is to say, even if the processor hangs up, the integrated circuit with the interface multiplexing function disclosed in the embodiment of the present application can switch the multiplexing function of the first pin and complete the debugging of the processor.

In order to clarify the technical characteristics of the control circuit generating the corresponding switching signal according to the preset switching data in the embodiment of the present application, an example is disclosed below.

In this example, three functional modules are set in the integrated circuit, namely, the UART controller, the I2C controller and the JTAG interface module. In order to realize the switching of pin functions, the following four preset switching data can be set:

Seq1:0xdeadbeecdeadbeecdeadbeec;

Seq2:0xdeadbeeddeadbeeddeadbeed;

Seq3:0xdeadbeefdeadbeefdeadbeef;

Seq4:0xdeadbeeedeadbeeedeadbeee.

Among them, the action of switching through various preset switching data is shown in Figure 3.

In this case, if the current pin function is UART function, the pin function needs to be switched to JTAG function (that is, the current switching circuit is connected to the UART controller, and the switching circuit needs to be switched to connect the switching circuit to the JTAG module). The device or the on-chip processor can generate a data sequence Seq1, which is a kind of preset switching data, and then transmit the preset switching data to the first pin. After the control circuit monitors the switching data, Corresponding switching signals are generated so that the switching circuit can be connected with the JTAG module to realize the switching of the pin functions.

If the current pin function is JTAG function, the pin function needs to be switched to UART function (that is, the current switching circuit is connected to the JTAG module, and the switching circuit needs to be switched to connect the switching circuit to the UART controller), chip external device or internal processing The device, etc. can generate a data sequence Seq2, which is a kind of preset switching data, and then transmit the preset switching data to the first pin. After the control circuit monitors the preset switching data, it will generate a corresponding The switching signal is connected to the UART controller to realize the switching of the pin function.

If the current pin function is UART function, the pin function needs to be switched to I2C function (that is, the current switching circuit is connected to the UART controller, and the switching circuit needs to be switched to connect the switching circuit to the I2C controller), chip external device or in the chip The processor, etc. can generate a data sequence Seq3, which is a kind of preset switching data, and then transmit the preset switching data to the first pin. After the control circuit monitors the switching data, it will generate a corresponding Switch the signal so that the switch circuit is connected with the I2C controller to realize the switch of the pin function.

If the current pin function is the I2C function, the pin function needs to be switched to the UART function (that is, the current switching circuit is connected to the I2C controller, and the switching circuit needs to be switched to connect the switching circuit to the UART controller), chip external device or inside the chip The processor, etc. can generate a data sequence Seq4, which is a kind of preset switching data, and then transmit the preset switching data to the first pin. After the control circuit monitors the switching data, it will generate a corresponding Switch the signal so that the switch circuit is connected with the UART controller to realize the switch of the pin function.

In addition, if the current pin function is the JTAG function, the pin function needs to be switched to the I2C function (that is, the current switching circuit is connected to the JTAG module, and the switching circuit needs to be switched to connect the switching circuit to the I2C controller), chip external device or chip The internal processor, etc. can generate data sequences Seq2 and Seq3. The data sequences Seq2 and Seq3 are preset switching data, and then the preset data sequences Seq2 and Seq3 are sequentially transmitted to the first pin. The control circuit is monitoring the preset data sequence After Seq2, a corresponding switching signal is generated to connect the switching circuit with the UART controller. Then, after the control circuit monitors the preset data sequence Seq3, the corresponding switching signal is generated again, so that the switching circuit can communicate with the UART controller. Connect, switch to connect with I2C controller, realize the switch of pin function.

If the current pin function is the I2C function, the pin function needs to be switched to the JTAG function (that is, the current switching circuit is connected to the I2C controller, and the switching circuit needs to be switched to connect the switching circuit to the JTAG module), chip external equipment or in-chip processing The device can generate data sequences Seq4 and Seq1, the data sequences Seq4 and Seq1 are preset switching data, and then the preset data sequences Seq4 and Seq1 are transmitted to the first pin in turn, and the control circuit monitors the preset data sequence Seq4. , Will generate the corresponding switching signal to connect the switching circuit to the UART controller. Then, after the control circuit monitors the preset data sequence Seq1, it will generate the corresponding switching signal again so that the switching circuit can connect to the UART controller. Switch to the connection with the JTAG module to realize the switch of the pin function.

In addition, in actual applications, other forms of data can also be used as preset switching data, which is not limited in this application.

Wherein, the external device may be a terminal device such as a computer, and the external device may be connected to the first pin through a data line. After the preset switching data is generated, the external device then transmits the preset switching data through the data line. It is transmitted to the first pin so that the control circuit can monitor the preset switching data in the first pin.

In the embodiment of the present application, the control circuit is a logic circuit. Further, the control circuit is usually a serial control circuit.

In addition, the control circuit can be implemented in various forms. In one of the feasible forms, the control circuit includes:

The number of state machines is not less than the number of types of the preset switching data, and one type of preset switching data corresponds to a switching method. It should be understood that the state machine in the embodiments of the present application is usually hardware logic, and optionally, the state machine may also be implemented by software.

Wherein, the first pin is coupled with the state machine;

After acquiring the preset switching data, the target state machine in the state machine generates the switching signal corresponding to the preset switching data, wherein the target state machine is corresponding to the preset switching data State machine.

In the embodiment of the present application, the preset switching data includes multiple types, wherein each type of preset switching data corresponds to a switching method, for example, when the preset switching data is:

Seq1:0xdeadbeecdeadbeecdeadbeec;

Seq2:0xdeadbeeddeadbeeddeadbeed;

Seq3:0xdeadbeefdeadbeefdeadbeef;

Seq4:0xdeadbeeedeadbeeedeadbeee.

When each of the above-mentioned data corresponds to one switching mode, the preset switching data is four types.

In addition, the number of the state machines is not less than the number of types of the preset switching data, and for each type of preset switching data, there is at least one state machine, and the corresponding state machine can be generated according to the preset switching data. Switching signal.

Specifically, in one of the feasible examples, referring to the schematic structural diagram shown in FIG. 4, the control circuit includes: at least m first state machines 210 and one second state machine 220, where m is the preset switch For the number of data types, one end of the first state machine 210 is connected to the first pin, and the other end is connected to the second state machine 220. In addition, one end of the second state machine 220 is connected to the first state machine 210, and the other end is connected to the switching circuit. That is to say, in the implementation of this application, the state machines included in the control circuit are divided into two types, namely the first state machine and the second state machine.

Each first state machine 210 is used to monitor one type of preset switching data. In this case, the at least m first state machines can monitor m sets of preset switching data.

In the embodiment of the present application, the first state machine used for monitoring the first target data may be referred to as the first target state machine. Wherein, the first target data is any kind of preset switching data.

In this case, the first target state machine includes n state nodes connected in series, the first target state machine is a first state machine for monitoring the first target data, and n is the first target data The number of bytes contained in.

Wherein, the r-th byte in the first target data satisfies the state transition requirement of the r-th state node in the first target state machine, and the last state node in the first target state machine After determining that the last byte in the first target data satisfies the state transition requirement, the last state node outputs a trigger signal to the second state machine, and r is any positive integer not greater than n

After receiving the trigger signal of the first target state machine, the second state machine generates a switching signal corresponding to the first target data, and transmits the switching signal to the switching circuit.

That is, the first target data includes n bytes, and the first target state machine includes n serially connected state nodes, and each state node monitors its corresponding byte. The state node is usually idle by default. When transmitting data to each state node in the series, after a certain state node receives a byte that meets the state transition requirement, the state node will undergo a state transition. If the state node is not the last state node in the first target state machine, when a state transition occurs, the state node will transfer the remaining bytes in the data to the subsequent state nodes so that the subsequent state nodes can continue to monitor the remaining state nodes. Byte; in addition, if the state node is the last state node in the first target state machine, after the state node determines that the last byte in the data meets its own state transition requirements, it will output a trigger signal to the second state machine for The second state machine generates a corresponding switching signal based on the trigger signal.

Or, during the monitoring process, if a state node in the first state machine detects that the corresponding byte in the data does not meet its own state transition requirements, the state node is still in the idle state, and no more data The remaining bytes in the data are transferred to the subsequent state node, that is, the first state machine ends the monitoring of the data. In this case, the first state machine is not the first target state machine corresponding to the data.

For example, set a certain data received by the first pin as "abc", which contains 3 bytes. After the first state node in the first state node receives the data, monitor whether the byte "a" is Meet its own state transition requirements. If not, the first state node does not undergo state transition. The first state machine ends the monitoring of the data. If it is met, the first state node undergoes state transition, and the remaining The node "bc" is passed to the second state node; after the second state node obtains the remaining node "bc", it monitors whether the byte "b" meets its own state transition requirements, if not, the second state node No state transition occurs, the first state machine ends the monitoring of the data, if it is satisfied, the second state node undergoes a state transition, and the remaining node "c" is transferred to the third state node; the third state node After obtaining the remaining node "c", monitor whether the byte "c" meets its own state transition requirements. If not, the third state node does not undergo state transition, and the first state machine ends the monitoring of the data. If it is satisfied, the third state node undergoes a state transition, and since the third state node is the last state node in the first state machine, the third state node will output a trigger signal to the second state machine so that The second state machine generates a corresponding switching signal according to the data, and in this case, it can be determined that the first state machine is the first target state machine corresponding to the data.

In addition, the second state machine generates a switching signal corresponding to the first target data after receiving the trigger signal of the first target state machine. After the switching signal is transmitted to the switching circuit, the switching circuit can switch according to the The signal completes the switch of the corresponding pin function.

In another feasible form, referring to the structural diagram shown in FIG. 5, the control circuit includes: at least m third state machines 230 and one line-and logic device 240, where m is the number of types of the data sequence One end of the third state machine 230 is connected to the first pin, and the other end is connected to the line and logic device 240. That is to say, in the implementation of this application, the state machine included in the control circuit is the third state machine.

In addition, one end of the line and logic device 240 is connected to the third state machine 230, and the other end is connected to the switching circuit. Wherein, the line and logic device 240 may be an open collector gate or a tri-state gate, etc., which is not limited in the embodiment of the present application.

Each third state machine 230 is used to monitor one type of preset switching data. In this case, the at least m third state machines 230 can monitor m sets of preset switching data.

In the embodiment of the present application, the third state machine for monitoring the third target data may be referred to as the third target state machine. Wherein, the third target data is any preset switching data.

In this case, the third target state machine includes s state nodes connected in series, the third target state machine is a third state machine for monitoring the third target data, and s is the third target data The number of bytes contained in.

Wherein, the t-th byte in the third target data satisfies the state transition requirement of the t-th state node in the third target state machine, and the last state node in the third target state machine After determining that the last byte in the third target data meets the state transition requirement, output a switching signal corresponding to the third target data to the line and logic device, and t is any positive integer not greater than s.

After receiving the switching signal, the line-and logic device outputs the switching signal to the switching circuit.

That is, the third target data includes s bytes, and the third target state machine includes s serially connected state nodes, and each state node monitors its corresponding byte. Each state node is usually in an idle state by default. When data is transmitted to each state node in the series, after a certain state node receives a byte that meets the state transition requirement, the state node will undergo a state transition. If the state node is not the last state node in the third target state machine, when a state transition occurs, the state node will transfer the remaining bytes in the data to the subsequent state nodes so that the subsequent state nodes can continue to monitor the remaining state nodes. Node; In addition, if the state node is the last state node in the third target state machine, after the state node determines that the last byte in the data meets its own state transition requirements, it will output the first to the line and logic device Three switching signals corresponding to the target data, so that the line and logic device can obtain the switching signal.

Or, during the monitoring process, if a certain state node in the third state machine detects that the corresponding byte in the data does not meet its own state transition requirements, the state node is still in the idle state, and no more data The remaining bytes in the data are transferred to the subsequent state node, that is, the third state machine ends the monitoring of the data. In this case, the third state machine is not the third target state machine corresponding to the data sequence.

For example, set a certain data sequence to "def", containing 3 bytes. After the first state node in the third state node receives the data, it monitors whether the byte "d" meets its own state transition requirements If it is not satisfied, the first state node does not undergo a state transition, and the third state machine ends the monitoring of the data. If it is satisfied, the first state node undergoes a state transition and passes the remaining node "ef" to The second state node in the third state machine; after the second state node obtains the remaining node "ef", it monitors whether the byte "e" meets its own state transition requirements, if not, then the second state node No state transition occurs, the third state machine ends the monitoring of the data, if it is satisfied, the second state node undergoes a state transition, and the remaining node "f" is transferred to the third state in the third state machine Node; after the third state node obtains the remaining node "f", it monitors whether the byte "f" meets its own state transition requirements, if not, the third state node does not undergo state transition, the first state machine End the monitoring of the data. If it is satisfied, the third state node will undergo a state transition. Moreover, since the third state node is the last state node in the third state machine, the third state node will go to the line and The logic device outputs a corresponding switching signal, and in this case, it can be determined that the third state machine is the third target state machine corresponding to the data.

In addition, after receiving the switching signal of the third target state machine, the line and logic device transmits the switching signal to the switching circuit, and the switching circuit completes the switching of the corresponding pin function according to the switching signal.

Or, in another feasible form, referring to the structural schematic diagram shown in FIG. 6, the control circuit includes: a memory 250, a comparator 260 and a buffer 270.

Wherein, the memory 250 and the buffer 270 are both coupled with the comparator 260, the comparator 260 is coupled with the switching circuit, and the buffer 270 is coupled with the first pin;

The memory 250 is used to store preset switching data;

The buffer 270 is used to buffer the data received by the first pin;

The comparator 260 is configured to generate the switching signal corresponding to the preset switching data when the data stored in the buffer matches the preset switching data stored in the memory.

In the embodiment of the present application, the control circuit includes a memory 250, a comparator 260, and a buffer 270. Among them, the buffer 270 is connected to the first pin. The buffer 270 can obtain and buffer the data received by the first pin. In addition, in the memory 250, various types of switching data set in advance are stored. The comparator 260 matches the data buffered in the buffer 270 with the switching data stored in the memory 250. If the two match, it indicates that the data received by the first pin can be used for this time. Pin switching, in this case, the comparator 260 generates a corresponding switching signal and transmits the switching signal to the switching circuit, so that the switching circuit completes the corresponding pin switching according to the switching signal.

Wherein, the comparator 260 is used to detect whether the data buffered in the buffer matches the switching data stored in the memory. In the embodiment of the present application, it can be set that when the data cached in the buffer is the same as the switching data stored in the memory, the two kinds of data match, or the data cached in the buffer can be set to match the data stored in the memory. When the similarity of the switching data is greater than the preset threshold, the two data match.

In addition, in the integrated circuit with interface multiplexing function disclosed in the embodiments of the present application,

The switching circuit includes: a multiplexer;

The input terminal of the multiplexer is coupled with the first pin;

After receiving the switching signal, the output terminal of the multiplexer is connected to the target function module.

Further, in the embodiment of the present application, when the multiplexer is connected to the functional module corresponding to the switching signal through the other end, and the first pin is connected to the external device corresponding to the functional module, The function module performs corresponding function operations under the action of the external device.

For example, when the other end of the switching circuit is connected to the JTAG module, and the first pin is connected to the JTAG device outside the chip, the JTAG debugging interface, the switching circuit, and the first pin inside the chip are connected to the JTAG debugging outside the chip. The device forms a path, so the JTAG debugging device can perform JTAG debugging on the chip's processor.

Wherein, the debugging interface module is a joint test working group JTAG debugging interface or a serial wire debugging (SWD) module, or may also be other types of debugging interface modules, which are not limited in the embodiment of the present application.

In addition, in order to meet other functions of the chip and meet the diverse needs of users, multiple types of functional modules are usually set inside the chip. The multiple functional modules also include: a circuit interconnect bus I2C controller, a universal asynchronous receiver transmitter UART controller, or a serial peripheral interface (SPI) interface.

Of course, other types of serial interface modules or chip debugging modules can also be set in the chip. Further, in order to make the chip have multiple functions and meet the diverse needs of users, other functional modules can also be set in the chip. This application does not limit this.

Correspondingly, an embodiment of the present application also discloses a pin switching method, which is applied to an integrated circuit with an interface multiplexing function. The integrated circuit includes a plurality of functional modules, a first pin, a switching circuit, and a control circuit, The multiple functional modules provide interface functions through the first pin of the integrated circuit for external devices to access the integrated circuit. Referring to the schematic diagram of the work flow shown in Figure 7, the method includes the following steps:

Step S11: The multiple functional modules multiplex the first pin through the switching circuit, so that the integrated circuit communicates with the external devices corresponding to the multiple functional modules through the first pin;

Step S12: The control circuit controls the switching circuit to connect the target function module to the first pin, and the target function module is one of the multiple function modules.

Through the method disclosed in the embodiments of the present application, multiple functional modules can multiplex the first pin through the switch circuit, and the switch circuit can be controlled by the control circuit, thereby reducing the number of pins, thereby reducing the cost of the chip, and Reduce chip size.

Further, the control circuit controlling the switching circuit to connect the target function module to the first pin includes:

The control circuit generates a corresponding switching signal according to the preset switching data;

The control circuit sends the switching signal to the switching circuit, so that the switching circuit connects the target function module to the first pin according to the switching signal.

In addition, in the pin switching method disclosed in the embodiment of the present application, when the integrated circuit further includes a processor, the various functional modules include: a debugging interface module, and the preset switching data includes: a debugging interface switching sequence; The circuit controlling the switching circuit to connect the target function module to the first pin includes:

When the processor hangs up, the control circuit generates a debugging interface switching signal according to the debugging interface switching sequence;

The control circuit sends the debugging interface switching signal to the switching circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.

Further, in the pin switching method disclosed in the embodiment of the present application, the control circuit is coupled to the first pin, and the method further includes:

The control circuit monitors the data transmitted on the first pin;

When the processor hangs up, the first pin receives the debugging interface switching sequence sent by the external device;

The control circuit controls the switching circuit to connect the target function module to the first pin, including:

The control circuit generates the debugging interface switching signal according to the debugging interface switching sequence after monitoring the debugging interface switching sequence received by the first pin;

Further, the control circuit generates a corresponding switching signal according to the preset switching data, including:

The target state machine in the control circuit generates the switching signal corresponding to the preset switching data, wherein the control circuit includes state machines no less than the number of types of the preset switching data, and the target state machine is related to the preset switching data. Set the state machine corresponding to the switching data.

In a feasible implementation manner, the debugging interface module is a joint test working group JTAG debugging interface or a serial wire debugging SWD interface.

In a feasible implementation manner, the multiple functional modules further include:

Circuit interconnection bus I2C controller, universal asynchronous receiver transmitter UART controller or serial peripheral SPI interface.

It should be understood that, in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not correspond to the difference in the embodiments of the present application. The implementation process constitutes any limitation.

Each part of this specification is described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments.

Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solutions in the embodiments of the present invention can be embodied in the form of software products, which can be stored in a storage medium, such as ROM/RAM. , Magnetic disks, optical disks, etc., including a number of instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments of the present invention.

The same or similar parts in the various embodiments in this specification can be referred to each other. In particular, as for the embodiment of..., since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the description in the method embodiment.

The embodiments of the present invention described above do not constitute a limitation on the protection scope of the present invention.

Claims

An integrated circuit with an interface multiplexing function, which is characterized by comprising: a plurality of functional modules, a first pin, a switching circuit, and a control circuit; the plurality of functional modules pass through the first tube of the integrated circuit The pin provides an interface function for external devices to access the integrated circuit;

The multiple functional modules multiplex the first pin through the switching circuit, so that the integrated circuit communicates with the external devices corresponding to the multiple functional modules through the first pin;

The control circuit is configured to control the switching circuit to connect a target function module to the first pin, and the target function module is one of the multiple function modules.
The integrated circuit of claim 1, wherein:

The control circuit is specifically configured to generate a corresponding switching signal according to preset switching data, and send the switching signal to the switching circuit, so that the switching circuit transfers the target function module to the switching signal according to the switching signal. Connected with the first pin;

Wherein, the preset switching data is used to indicate the switching mode of the switching circuit.
The integrated circuit according to claim 2, wherein the integrated circuit further comprises: a processor;

The multiple functional modules include: a debugging interface module, and the preset switching data includes: a debugging interface switching sequence;

When the processor hangs up, the control circuit is specifically configured to:

Generating a debugging interface switching signal according to the debugging interface switching sequence;

The debugging interface switching signal is sent to the switching circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.
The integrated circuit of claim 3, wherein:

The control circuit is coupled to the first pin, and the control circuit is also used to monitor the data transmitted on the first pin;

When the processor hangs up, the first pin receives the debugging interface switching sequence sent by the external device;

The control circuit is specifically used for:

After monitoring the debugging interface switching sequence received by the first pin, generating the debugging interface switching signal according to the debugging interface switching sequence;

The debugging interface switching signal is sent to the switching circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.
The integrated circuit according to any one of claims 2 to 4, wherein the control circuit comprises:

State machines, the number of said state machines is not less than the number of types of said preset switching data, and one type of preset switching data corresponds to one switching method;

The first pin is coupled with the state machine;

After acquiring the preset switching data, the target state machine in the state machine generates the switching signal corresponding to the preset switching data, wherein the target state machine is corresponding to the preset switching data State machine.
The integrated circuit according to any one of claims 2 to 4, wherein the control circuit comprises: a memory, a comparator and a buffer;

Both the memory and the buffer are coupled with the comparator, the comparator is coupled with the switching circuit, and the buffer is coupled with the first pin;

The memory is used to store preset switching data;

The buffer is used to buffer the data received by the first pin;

The comparator is configured to generate the switching signal corresponding to the preset switching data when the data stored in the buffer matches the preset switching data stored in the memory.
The integrated circuit according to any one of claims 1 to 6, wherein the switching circuit comprises: a multiplexer;

The input end of the multiplexer is coupled with the first pin;

After receiving the switching signal, the output terminal of the multiplexer is connected to the target function module.
The integrated circuit according to any one of claims 3 to 7, wherein:

The debugging interface module is a JTAG debugging interface of a joint test working group or a serial wire debugging SWD interface.
The integrated circuit according to any one of claims 1 to 8, wherein the multiple functional modules further comprise:

Circuit interconnection bus I2C controller, universal asynchronous receiver transmitter UART controller or serial peripheral SPI interface.
A pin switching method, characterized in that it is applied to an integrated circuit with an interface multiplexing function. The integrated circuit includes a plurality of functional modules, a first pin, a switching circuit, and a control circuit. The multiple functional modules Providing an interface function through the first pin of the integrated circuit for external devices to access the integrated circuit, the method includes:

The multiple functional modules multiplex the first pin through the switching circuit, so that the integrated circuit communicates with the external devices corresponding to the multiple functional modules through the first pin;

The control circuit controls the switching circuit to connect a target function module to the first pin, and the target function module is one of the plurality of function modules.
11. The pin switching method of claim 10, wherein the control circuit controlling the switching circuit to connect the target function module to the first pin comprises:

The control circuit generates a corresponding switching signal according to preset switching data;

The control circuit sends the switching signal to the switching circuit, so that the switching circuit connects the target function module with the first pin according to the switching signal.
The pin switching method according to claim 11, wherein when the integrated circuit further includes a processor, the multiple functional modules include: a debugging interface module, and the preset switching data includes: debugging interface switching Sequence; the control circuit controls the switching circuit to connect the target function module with the first pin, including:

When the processor hangs up, the control circuit generates a debugging interface switching signal according to the debugging interface switching sequence;

The control circuit sends the debugging interface switching signal to the switching circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.
The pin switching method according to claim 12, wherein:

The control circuit is coupled to the first pin, and the method further includes:

The control circuit monitors the data transmitted on the first pin;

When the processor hangs up, the first pin receives the debugging interface switching sequence sent by the external device;

The control circuit controlling the switching circuit to connect the target function module to the first pin includes:

The control circuit generates the debugging interface switching signal according to the debugging interface switching sequence after monitoring the debugging interface switching sequence received by the first pin;

The control circuit sends the debugging interface switching signal to the switching circuit, so that the switching circuit connects the debugging interface module with the first pin according to the debugging interface switching signal.
The pin switching method according to any one of claims 11 to 13, wherein the control circuit generates a corresponding switching signal according to preset switching data, comprising:

The target state machine in the control circuit generates the switching signal corresponding to the preset switching data, wherein the control circuit includes state machines no less than the number of types of the preset switching data, and the target The state machine is a state machine corresponding to the preset switching data.
The pin switching method according to any one of claims 12 to 14, wherein:

The debugging interface module is a JTAG debugging interface of a joint test working group or a serial wire debugging SWD interface.
The pin switching method according to any one of claims 10 to 15, wherein the multiple functional modules further comprise:

Circuit interconnection bus I2C controller, universal asynchronous receiver transmitter UART controller or serial peripheral SPI interface.