CN1005436B - Bus arrangement for a digital television system - Google Patents

Bus arrangement for a digital television system Download PDF

Info

Publication number
CN1005436B
CN1005436B CN85104332.1A CN85104332A CN1005436B CN 1005436 B CN1005436 B CN 1005436B CN 85104332 A CN85104332 A CN 85104332A CN 1005436 B CN1005436 B CN 1005436B
Authority
CN
China
Prior art keywords
bus
unit
address
inlet
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CN85104332.1A
Other languages
Chinese (zh)
Other versions
CN85104332A (en
Inventor
杰伊·斯科特·帕克
利奥·伯纳德·科泽尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/613,062 external-priority patent/US4626846A/en
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to CN85104332.1A priority Critical patent/CN1005436B/en
Publication of CN85104332A publication Critical patent/CN85104332A/en
Publication of CN1005436B publication Critical patent/CN1005436B/en
Expired legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0669Configuration or reconfiguration with decentralised address assignment
    • G06F12/0676Configuration or reconfiguration with decentralised address assignment the address being position dependent
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00Geometric image transformations in the plane of the image
    • G06T3/02Affine transformations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Small-Scale Networks (AREA)

Abstract

The present invention discloses bus configuration for providing addresses for device units (10). Each device unit (10) can automatically obtain an address of each device unit (10) without installing any switch according to the corresponding physical position in a unit organization (10). In short, the present invention is obtained by modifying bus conducting wires of each unit, and comprises the termination of one conducting wire (13), the addition of one conducting wire (21), and the corresponding changes of other conducting wires.

Description

Bus configuration and method thereof to the addressed device unit
In general, the present invention relates to a kind of bus configuration that is used to unit that the address is provided; More particularly, the present invention relates to a kind of like this bus configuration, in this kind bus configuration, each independent unit basis oneself residing relative physical location in the unit tissue automatically obtains its address, and the device of any switch and so on need not be set.
When erecting equipment, the common practice is to set an address to each unit.By this way, can carry out addressing uniquely and it is controlled and irrelevant with other unit each independent unit.In the past, this addressing, makes and determines unique address can for each unit by switch being set to suitable position always by using P cock (for example DIP dual-in-line package switch) to realize on each unit.But can expect that as people it is not only time-consuming but also make the operator produce mistake easily to be with this kind method that the various device unit is provided with the address.
The objective of the invention is: when a unit and miscellaneous equipment unit are connected to each other, automatically provide an address, produce wrong chance thereby reduce the operator to it.
More particularly, the present invention has used a kind of addressing bus of uniqueness, and the addressing bus of this uniqueness in each unit all is the same.Input one side (inlet) of address bus receives the signal from the neighbouring device unit, and these signals are sent to output terminal (outlet).In the process of carrying out this operation, address bus is made amendment, an input lead is stopped, pick up a ground wire simultaneously.These situations are described in detail with reference to the accompanying drawings.
In other words, the present invention is a kind of bus configuration that is connected to each other a plurality of units with following form, promptly only according in being connected to each other with the relative position of miscellaneous equipment unit, each unit is provided a unique address.Bus configuration in each unit comprises: a inlet with N end, and N is equal to or greater than two positive integer; Outlet with N end, this N end corresponds respectively to N end of inlet, and wherein second to N of the inlet end is connected with first to the N-1 end of outlet respectively, simultaneously, initial line is received the N end of outlet.
Below with reference to accompanying drawings the present invention is described in detail, the same section among each figure represents with same reference number, wherein:
Fig. 1 has represented eight according to the present invention and interconnective unit or frame;
Fig. 2 has represented the addressing bus of two equipment racks shown in Figure 1 in more detail;
Fig. 3 has represented the notch configuration in the unit in these unit or the frame;
Fig. 4 has represented first kind of modification of embodiment shown in Figure 1;
Fig. 5 has represented second kind of modification of embodiment shown in Figure 1.
Be detailed description of the present invention below.
Fig. 1 has represented eight equipment rack 10a to 10h, total equipment rack (or unit) 10 that is referred to as.As shown in Figure 1, equipment rack 10a to 10h is connected to each other with bus 11b to 11h respectively.Bus 11b to 11h is total is referred to as bus 11, and they are identical each other, and bus 12 is added to frame 10a to the initial address bus.Should be noted in the discussion above that in Fig. 1 each equipment rack 10 accepts own address according to own with respect to the position of bus 12, that is to say that frame 10a obtains a special address, because it is the frame of reception bus 12; Equipment rack 10b obtains the address of oneself, because of it is a frame that is connected with frame 10a; Equally, the address of frame 10c acquisition oneself is just because it is a frame that is connected with frame 10b.Or the like the rest may be inferred, up to 10h.These situations in Fig. 2, have been shown in more detail.The following describes Fig. 2.
Fig. 2's frame 10a and 10b has only drawn, and certainly, remaining frame all is interconnective in the same way.As shown in Figure 2, bus 12 comprises lead 13,14,15,16,17,18 and 19, and respectively by resistance 13a, 14a, 15a, 16a, 17a, 18 be connected with positive five volts of voltage sources with 19a (annotate: the value of each resistance is 5.1 kilohms among the resistance 13a to 19a).
As shown in Figure 2, provided the address ABCDEFG of equipment rack 10a in the bottom of square frame, its address is a logical one 111111 in this illustrative embodiment certainly.Should be noted in the discussion above that equally lead 13 has just stopped after the address of equipment rack 10a is set up.Be also noted that, lead 14 to 19 continues across the equipment rack 10a position that moves up then, cause when lead 14 to 19 passes equipment rack 10b via bus 11b, their position is the position on the position when being in access arrangement frame 10a, added simultaneously a new lead (ground wire) again, with lead 21 expressions.Provided the address ABCDEFG of equipment rack 10b so again, this address now is a logical one 111110.When these leads pass equipment rack 10b, during by bus 11c, we just see their upward displacements once more, and uppermost lead is discarded, and add a new ground wire 22 simultaneously.Therefore, the address of equipment rack 10c (not shown among Fig. 2) will be that then the rest may be inferred for all the other units for logical one 111100().These addresses (noncoding) have at length been represented in the table 1.Be this table below.
Table 1
Therefore as can be seen, the address of each frame (being frame 10a) is full logical one, and the address that nestles up the frame 10b on its right is and then logical zero of full logical one.The address of next frame (being frame 10C) is and then two logics or the like of five logical ones.Until the address of frame 10h is full logical zero.By this way, each equipment rack 10 obtains a unique address, and the physical location of this frame among institute's organic frame combination only depended in this address.
Just as people can think of, represent frame address some trouble that seems with this seven bits.In order to simplify this address, can within frame 10, reduce to the triad number to them with an encoding scheme, this encoding scheme realizes (for example model is the assembly of SN74LS148) by one 8 line to 3 line scramblers.The net result of this volume case scheme is shown in the table I.Both represent the non-coded address of each equipment rack 10 in the table, represented its coded address again.For example, the non-coded address of equipment rack 10a is 1111111, and its coded address is 111.In table, can also see the similar result of other frame 10.
Each frame 10 can be subdivided into eight notches.Fig. 3 has represented these notches, and four notches that its mid frame 10a arranges on top from left to right are notch 1 to 4, and four notches of frame bottom are notch 5 to 8.These notches can obtain unique address separately during addressing, for example obtain from 000 to 111 triad and count the address.Certainly this just need have three additional wire on address buss such as 11b and 11c.
Please note the table II below.Non-coded address and the coded address of wherein containing frame 10 when the groove slogan is also taken into account.From the table II as can be seen.Last three figure places of each address (coding or noncoding) are exactly the notch address.
The table II
Fig. 4 has represented another bus configuration scheme, and it is about three equipment racks, i.e. 30a, and 30b and 30c are generically and collectively referred to as frame 30.The principle of work of this allocation plan is the same with embodiment shown in Figure 2, and its difference is that interconnect bus (being bus 31b and 31c) and input bus 32 only have two leads.Therefore can only provide three addresses, i.e. logical one 1,10 and 00.
As shown in Figure 4, the address that frame 30a obtains is a logical one 1, and the address that frame 30b obtains is a logical one 0, and the address that frame 30c obtains is a logical zero 0.Input bus 32 is connected with positive five volts of voltage sources with 33b by the resistance 33a of 5.1K Ω.
Fig. 5 is similar to Fig. 4, and just input bus 42 is logical zero (be earth potential rather than positive five volts).Therefore the address of frame 40a is a logical zero 0.Interconnect bus 41b connects together frame 40a and 40b, and interconnect bus 41c connects together frame 40b and 40c.The address of frame 40b is a logical zero 1, and this is to add positive five volts of voltages that come self-resistance 43a because of a lead to bus 41b; The address of frame 40c is a logical one 1, and this is because two leads of bus 41c all have positive five volts of voltages (coming self-resistance 43a and 43b) at this moment.
The table I
Equipment rack is the coded address, coded address not
ABCDEFG AA BB CC
10a 1111111 1 1 1
10b 1111110 1 1 0
10c 1111100 1 0 1
10d 1111000 1 0 0
10e 1110000 0 1 1
10f 1100000 0 1 0
10g 1000000 0 0 1
10h 0000000 0 0 0
The table II
Coded address, the non-coded address of equipment rack groove slogan
10a 1 1111111111 111111
10a 2 1111111110 111110
10a 3 1111111101 111101
10a 4 1111111100 111100
10a 5 1111111011 111011
10a 6 1111111010 111010
10a 7 1111111001 111001
10a 8 1111111000 111000
10b 1 1111110111 110111
10b 2 1111110110 110110
10b 3 1111110101 110101
10b 4 1111110100 110100
10b 5 1111110011 110011
10b 6 1111110010 110010
10b 7 1111110001 110001
10b 8 1111110000 110000
10c 1 1111100111 101111
10c 2 1111100110 101110
10c 3 1111100101 101101
10c 4 1111100100 101100
10c 5 1111100011 101011
10c 6 1111100010 101010
10c 7 1111100001 101001
10c 8 1111100000 101000
10d 1 1111000111 100111
10d 2 1111000110 100110
10d 3 1111000101 100101
10d 4 1111000100 100100
10d 5 1111000011 100011
10d 6 1111000010 100010
10d 7 1111000001 100001
10d 8 1111000000 100000
10e 1 1110000111 011111
10e 2 1110000110 011110
10e 3 1110000101 011101
10e 4 1110000100 011100
10e 5 1110000011 011011
10e 6 1110000010 011010
10e 7 1110000001 011001
10e 8 1110000000 011000
10f 1 1100000111 010111
10f 2 1100000110 010110
10f 3 1100000101 010101
10f 4 1100000100 010100
10f 5 1100000011 010011
10f 6 1100000010 010010
10f 7 1100000001 010001
10f 8 1100000000 010000
10g 1 1000000111 001111
10g 2 1000000110 001110
10g 3 1000000101 001101
10g 4 1000000100 001100
10g 5 1000000011 001011
10g 6 1000000010 001010
10g 7 1000000001 001001
10g 8 1000000000 001000
10h 1 0000000111 000111
10h 2 0000000110 000110
10h 3 0000000101 000101
10h 4 0000000100 000100
10h 5 0000000011 000011
10h 6 0000000010 000010
10h 7 0000000001 000001
10h 8 0000000000 000000

Claims (8)

1, a kind of static method of unique address being provided for the unit that respectively has entrance and exit is characterized in that described method comprises the following steps:
(a) in each unit, provide a bus that comprises many leads;
(b) when bus is crossed corresponding outlet from inlet, stop a lead in the described many leads;
(c) other described leads of a contiguous described lead are moved a position;
(d) ground wire is added to the final position of described bus, makes the lead number of described outlet equal the lead number of described inlet; Thereby make each described unit address acquisition by between each described inlet and described outlet, described bus being carried out tap (tapping) respectively.
2, according to the method for claim 1, it is characterized in that, wherein on following position, described bus is carried out tap (tapping) and obtained described address, promptly before a described lead stops and before the described ground wire adding.
3, according to the method for claim 2, it is characterized in that, wherein said unit is connected to each other by a kind of order, except having each end of its outlet is connected to bus by the respective end of the inlet of the next unit of described order, and has each bus of holding that the fixing predetermined voltage level of non-zero shape is supplied to its inlet by the first module of described order by each unit the last unit of described order.
According to the method for claim 3, it is characterized in that 4, wherein the described first module by described order has the bus that supplies to each end of its inlet to approximately positive five volts.
CN85104332.1A 1984-05-22 1985-06-07 Bus arrangement for a digital television system Expired CN1005436B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN85104332.1A CN1005436B (en) 1984-05-22 1985-06-07 Bus arrangement for a digital television system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/613,062 US4626846A (en) 1984-05-22 1984-05-22 Bus arrangement for addressing equipment units and a method therefor
CN85104332.1A CN1005436B (en) 1984-05-22 1985-06-07 Bus arrangement for a digital television system

Publications (2)

Publication Number Publication Date
CN85104332A CN85104332A (en) 1987-01-28
CN1005436B true CN1005436B (en) 1989-10-11

Family

ID=76482947

Family Applications (1)

Application Number Title Priority Date Filing Date
CN85104332.1A Expired CN1005436B (en) 1984-05-22 1985-06-07 Bus arrangement for a digital television system

Country Status (1)

Country Link
CN (1) CN1005436B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100383771C (en) * 2004-12-04 2008-04-23 鸿富锦精密工业(深圳)有限公司 System and method for dynamically distributing device address on integrated circuit bus
CN100389412C (en) * 2004-12-04 2008-05-21 鸿富锦精密工业(深圳)有限公司 Method for automatically identifying multiple serial device positions

Also Published As

Publication number Publication date
CN85104332A (en) 1987-01-28

Similar Documents

Publication Publication Date Title
US5836785A (en) Apparatus and method to uniquely identify similarly connected electrical devices
US4626846A (en) Bus arrangement for addressing equipment units and a method therefor
CN1004307B (en) Dynamically allocated local/global storage system
CN1005436B (en) Bus arrangement for a digital television system
US4831634A (en) Modem backplane interconnections
US4360913A (en) Multiplexing I/O module
CN1004045B (en) Improved time division multiplexed switching structure for pbx
CN1005437B (en) Transfer circuit for achieving raster working method
CN104734657A (en) Chip and port impedance matching correction circuit thereof
US3268875A (en) Translation operation
US7376096B2 (en) Process for interleaving navigation data
CN85101171B (en) Virtual computer system and its i/o executive method
EP0166523A2 (en) Mask signal generator
US3692945A (en) Circuit arrangement for telecommunication switching systems employing time-division multiplex operation
EP0186595A2 (en) Routing technique
WO2018221780A1 (en) Transmitter for cancelling simultaneous switching noise and data transmission method thereof
KR100311142B1 (en) Apparatus for assigning arbiter address in a communication node as arrangement in an exchange backboard
CN1005304B (en) Method station and system for the transmission of messages in the form of data packets
TWI647554B (en) Tandem signal transmission control module
CN1006257B (en) Digital sexvo system
CN1005435B (en) Chinese character matrix generator capable of generating multiple fonts
CN85106615B (en) Optical data way
CN86102400B (en) Decoding circuit
Amendolia et al. The crate clustering card
JPS62239740A (en) Circuit switching device

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C13 Decision
GR02 Examined patent application
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
C19 Lapse of patent right due to non-payment of the annual fee