CN85101171B

CN85101171B - Virtual computer system and its i/o executive method

Info

Publication number: CN85101171B
Application number: CN85101171A
Authority: CN
Inventors: 梅野英典; 久保隆重; 获原亘喬; 佐藤博昭; 沢本英雄
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1985-04-01
Filing date: 1985-04-01
Publication date: 1988-08-17
Also published as: CN85101171A

Abstract

In a system which comprises a virtual machine system, the virtual machine system can operate at least one operating system by a real computer system and a virtual machine control program. A conversion table is prepared for the virtual machine control program to convert virtual subchannel numbers into real subchannel numbers. A real subchannel control block has a virtual machine information area in which the virtual subchannel numbers and the real subchannel numbers obtained by conversion are stored. A status field in the information area has a characteristic bit for designating whether the subchannel numbers are used for a special purpose. When real interrupt priority is used specially for a virtual machine, only the I/O interrupt request of a subchannel with special real interrupt priority can be arranged in an interrupt request queue with the priority. Thus, the virtual machine mixed in the interrupt priority can be avoided.

Description

The I/O manner of execution of dummy machine system and computer system thereof

The present invention relates to high speed dummy machine system (VMS), especially for the method and system that reduces dummy machine system I/O simulation house-keeping.

The Japanese Laid-Open Patent Application NO that disclosed on June 24th, 1975, the instructions of 55-76950, NO, 56-19153 that on February 23rd, 1981 disclosed, NO, the 55-42326 on March 25th, 1980, and United States Patent (USP) NO, 4,459, the application that 661(1982 was submitted to based on the right of priority of nearest Japanese patent application by golden Tian Sanlang etc. at April 21) dummy machine system of all having touched upon.

Fig. 1 is the structural arrangements of genuine computer system 9000.Numeral 1000 is represented CPU (central processing unit) (CPU), numeral 2000 expression primary memorys, and numeral 3000 expression I/O processors (IOP), numeral 4000 is I/O controller (IOC).Signal transmssion line between numeral 100 expression CPU1000 and the primary memory 2000, numeral 200 signal transmssion lines of representing between CPU1000 and the I/O processor 3000, signal transmssion line between numeral 900 expression I/O processors 3000 and the primary memory 2000, the signal transmssion line between numeral 400 expression I/O processors 3000 and the I/O controller 4000.Genuine computer system 9000 carries out work under the control of total system resource management (CPU, primary memory and the I/O equipment) program of primary memory 2000 operating systems (OS).

The structure of dummy machine system (VMS) is seen Fig. 2.The structural similarity of the hardware configuration of genuine computer system 10000 (CPU, primary memory and I/O equipment) and Fig. 1, but have the control program (VMCP or be abbreviated as CP) of dummy machine system in its primary memory 2000.Polynary logical machine (being referred to as virtual machine (VM)) is the logical organization of carrying out work by the hardware simulation function of virtual machine control program.The 10000-1(VM1 of virtual machine (VM)), 10000-2(VM2) and 10000-3(VM3) be logical organization, its hardware configuration is identical with genuine computer system (being referred to as main system) 10000.The OS-N(N=1,2,3 of control virtual machine) be stored in the primary memory 2000-N(N=1,2,3 of each virtual machine) in, these operating systems (OS) are operation simultaneously under the control of a main system.Hardware configuration (the CPU of each virtual machine among Fig. 2, primary memory, I/O processor and I/O controller), all make logic configuration, thereby most of entity leans on all the corresponding hardware configuration of each virtual machine that is disposed by main system to keep by virtual machine control program (VMCP).For example, as its primary memory, virtual machine can occupy the primary memory 2000 of part main system exclusively, also addressable primary memory 2000, and as its I/O equipment, virtual machine can divide the I/O equipment of prosperous main system, also can take I/O equipment exclusively.In other words, can not have corresponding I/O equipment in the main system, I/O equipment can be made virtual configuration by the analog functuion of virtual computer control program.Under any circumstance, all addressable hardware configuration identical of operating system (OS) (CPU, primary memory, I/O processor, I/O controller) each virtual machine main memory device 2000-N(N=1,2,3) with the main system hardware configuration.The structure (hardware configuration and the function from the operating system angle) that is noted that each virtual machine can be slightly variant with the structure of main system.Equally, the structure of each virtual computer (VM) also can be inequality.For example, the machine instruction group of main system can be accurately identical one by one with the machine instruction group of each virtual machine.But in the present invention, dummy machine system is not adopted diverse machine instruction group, because this will increase the load of virtual machine control program, and increases the scale of main system emulation mechanism.Virtual machine of the present invention (VM) requires most of machine instructions all can directly carry out on main system under the situation that VMCP does not do to intervene, and the performance identical with main system (execution speed) arranged.Though three virtual machines are only arranged among Fig. 2, in fact can hold the virtual machine of any amount, the upper limit of this quantity depends on trading off between main system resource capacity and the virtual machine performance.Main system has a privileged state and a Non-Patent state.The machine instruction (for example instruction is changed in I/O instruction or system interrupt mask position) of system being given significant impact is called as privileged instruction, and it can only use under privileged state.This point is well-known at computing machine circle.

Fig. 3 is the hierarchy of memory of the virtual machine VM1 memory hierarchy among Fig. 2.Numeral 2060 expressions are by the Virtual Space of the OS1 generation of VM1.OS1 is stored among the primary memory 2000-1 of VM1.The primary memory 2000-1 of VM1 is copied in the primary memory 2002 of main system (primary memory 2000 of main system is split into hardware system district 2001 and programmable district 2002, referring to Fig. 7).This copy is provided by address translation table 2010.Fig. 4 a is expressed as address translation table 2010(1).This address translation table contains corresponding to the address V among the VM1 primary memory 2000-1 ₂Entry with appropriate address r in the primary memory 2002.When the OS1 of VM1 moves in storer 2000-1, address translation table 2010(1) start address will be stored in CPU1000 basic controlling register 1100(and see Fig. 7) a control register 1110(real address conversion table initial address register (RATOR) in.At this moment, address translation table 2010(1) be stored among the primary memory 2000-1 of VM10000-1, that is, and in the primary memory 2002 of main system.Simultaneously, start address is stored in by in the described register 1110 in an address in the primary memory 2002 of main system.

The virtual memory that the OS1 of numeral 2060 expression VM1 among Fig. 3 produces; And provide the copy of VM1 primary memory 2000-1 by the address translation table 2040 of OS1 management.Fig. 4 b is the address translation tableau format.It contains the address V of virtual memory 2060 ₃Address V with VM1 primary memory 2000-1 ₂Corresponding entry.When the OS1 of VM1 moved in virtual memory 2060, the start address of address translation table 2040 was stored in CPU1000 basic controlling register 1100(and sees Fig. 7) a control register 1120(virtual address translation tables initial address register (VATOR) in.At this moment, because the address system that address translation table 2040 is stored in the primary memory 2000-1 of OS1 is described address translation table 2010(1) (being called conversion table A) managed and revise for each virtual machine by virtual machine control program VMCP.Address translation table 2040(is called conversion table B) do management and correction by the operating system of each virtual machine for the virtual memory of itself.The primary memory 2002 of main system is referred to as 1 grade of storer, the primary memory 2000-N(N=1 of each virtual machine, 2,3,) be called 2 grades of storeies, the common OS of virtual memory 2060(that is produced by the OS of each virtual machine can produce a plurality of virtual memory) be generically and collectively referred to as 3 grades of storeies.Virtual memory is divided into some pages or leaves that predetermined volumes (for example 4KB) arranged usually; And be transformed in the primary memory of each page, the consecutive numbering of pages of some (for example 256 pages, 1MB) be called one section, this also is well-known at computing machine circle.Numeral 2020 representatives among Fig. 3 are the I/O operational order word (CCW) that its input-output operation of starting produces by VMCP.Because VMCP moves work on 1 grade of storer, thereby produce CCW2020 1 grade of storage address.It is called 1 grade of CCW.1 grade of CCW need not to do address translation; When the I/O starting command was issued 1 grade of CCW, directly to its in addition conversion and send to I/O controller 4000, I/O controller 4000 was carried out each CCW for each I/O equipment by I/O processor 3000.The command word (CCW) that numeral 2030 expressions are produced by VME operating system (OS), it is described by 2 grades of storage addresss.2 grades of CCW are produced by the OS of virtual machine, when the I/O starting order when the OS of virtual machine issues CCW, it can be converted to 1 grade of CCW of equivalence by VMCP; The starting of I/O can be passed through the 1 grade CCW enforcement of virtual machine control program (VMCP) by equivalence.Yet this will increase the house-keeping of virtual machine control program.Thereby, can adopt another kind of method: under the intervention of VMCP, the address that is converted to 1 grade of storer (conversion table A) by 2 grades of storeies in the address translation table is sent to I/O processor 3000, after I/O processor 3000 is searched conversion table 2010,2 grades of CCW(or 2 grades of storage addresss) in data address translation be 1 grade of storage address.This method has reduced the intervention of VMCP, reduce house-keeping, in many cases, the OS of virtual machine carries out on 3 grades of storeies, thereby often be stored in 3 grades of storeies by the CCW that virtual machine OS is produced, the CCW that numeral 2050 expressions among Fig. 3 are described by 3 grades of storage addresss, i.e. 3 grades of CCW.When the OS of virtual machine issued 3 grades of CCW to the I/O starting order, it sent the address in the address translation table to 2 grades of storeies (conversion table B) by 3 grades of storeies and this address is sent to 1 grade of storer (conversion table A) and then sent to I/O processor 3000(Fig. 7 by 2 grades of storeies).I/O processor 3000 is searched conversion table B, and the data address of 3 grades of CCW (3 grades of storage addresss) is converted to 2 grades of storage addresss; Search conversion table A again, 2 grades of memory address translation that conversion is got are 1 grade of address, so that carry out CCW.

Fig. 4 C is an address translation buffer 3030, and it is arranged on I/O processor 3000(Fig. 7) local storage in, be used to reduce the house-keeping of I/O processor 3000 address translation.The field 1 of address translation buffer 3030 contains VM sequence number (VM#); Field 2 contains the start address of address translation Table A and B; Field 3 is held its recognition feature position; Field 4 comprises the CCW data address before the address translation; And field 5 comprises 1 grade of storage address after the address translation.I/O processor 3000(Fig. 7) searches address translation buffer so that make address translation.If search less than this address, then search conversion table B and A and make address translation, and an address that is converted is deposited with in the translation buffer 3030, address translation buffer is a high speed local storage in the I/O processor 3000, its seek rate than in primary memory 2002, search conversion table B and A fast.Should point out, the term of execution of I/O, 2 grades of CCW, 3 grades of CCW and data buffer are all answered on the stuck-at-level storer.Fig. 5 has provided the primary memory that these subregions of method that the continuum of main system primary memory 2002 is divided into subregion are used as each respective virtual machine.When using this virtual machine, on the address of predetermined address displacement α markon virtual machine primary memory, just can try to achieve the address of main system primary memory 2002.Among Fig. 5, the address displacement of VM1 is α ₁, VM ₂The address displacement be α ₂In this case, being 1 grade of storage address from 2 grades of memory address translation, address translation 2010 may be the conversion table of the upper and lower limit address of each virtual machine of management, as Fig. 5,2010(2) shown in.In this case, the address translation of carrying out 2 grades of CCW is very convenient, concerning 2 grades of CCW, the entry entry of (field of address translation buffer 3030 for " 0 ") that does not need address translation buffer 3030 in other words, as shown in Figure 5, conversion table 2010(2) read in I/O processor 3000(Fig. 7) local storage in; Sequence number (VN#) by virtual machine obtains address displacement α, is superimposed with α, thereby realizes the conversion (from 2 grades of memory address translation to 1 grade storage addresss) of address.High speed virtual machine pattern can be provided with down virtual machine use under the situation, and promptly whole primary memorys of virtual machine (Fig. 3) are that reside and fixing in the primary memory 2002 of main system; Perhaps it occupies a continuum (see figure 5) of main system primary memory.When adopting high speed virtual machine pattern, can directly carry out the privileged instruction of sending by virtual machine OS (when not having VMCP to intervene) with almost identical performance execution command with main system.But the I/O instruction of virtual machine still needs VMCP to intervene, and sees for details hereinafter.

Below, illustrate that with reference to Fig. 6 VMCP carries out the mode of the starting I/O instruction that virtual machine OS sends.The OS indication and the corresponding subchannel of I/O equipment number (subchannel #) of virtual machine send starting I/O instruction.Because the numbering of this subchannel is subordinated to virtual machine, therefore be called virtual subnet channel number #.VMCP is converted to corresponding real subchannel # to it.This corresponding relation is determined when the defining virtual machine.The rank of the CCW that the starting I/O that the VMCP check is sent by virtual machine OS instructs.Usually, it is represented with the operand of starting I/O instruction.Suppose that this starting I/O instruction delivers to 3 grades of CCW.Among Fig. 6, CCW2810 is the CCW of 3 grades of storeies, and its data address is 3 grades of storage addresss.VMCP is added to operand 2800 on the CCW2810 of OS generation, sends starting I/O instruction.Operand 2800 includes other field of indication CCW level L; When L=3, also include the start address VATOR of conversion table B, and segment length SS and page size PS, operand 2800 also comprises the start address RATOR of conversion table A, and segment length SS, the address of page size PS and CCW2810.They press the starting I/O instruction of VMCP by signal transmssion line 200, deliver to I/O processor 3000(Fig. 7); And essential information is placed in the corresponding subchannel register 3011.Similarly essential information is stored in subchannel controll block 2090(and sees Fig. 7) corresponding subchannel controll block in (seeing the subchannel controll block 2091 among Figure 10).I/O processor 3000(Fig. 7) adopt the address translation table in the subchannel to carry out the CCW2810 that OS produces, simultaneously the reference address.

The hardware configuration that Fig. 7 has provided original dummy machine system with carry out relevant calcspar with I/O.

The CPU1000 of Fig. 7 comprises a prefix register 1010(, and it comprises the address of the zone prefix (PSA) that contains hardware interrupts information), CPU control register 1100 and program status word (PSW) (PSW) 1020(that includes the CPU basic status are as an interrupt control position or the next machine instruction address that then will carry out).It also comprises 1030, one I/O interrupt circuits of an I/O instruction execution circuit, 1040, one I/O instructions execution microprogram 1050 and an I/O Interrupt Process microprogram 1060.One of the V that represents the virtual machine pattern be as the dummy machine system Q-character 1090 in.At the virtual machine run duration, by VMCP with this position in " 1 ".The Q-character H of high speed virtual machine mode state is stored in 1090.Dummy machine system control mark 1090 also can be other form.For example, can provide VMCP pattern (supervisor mode) and virtual machine pattern.The virtual machine pattern can comprise preferred or high performance virtual machine pattern and not preferred virtual machine pattern.They are more or less similar.As mentioned above, 3 grades of CCW carried out by I/

O processor

3000 or 2 grades of CCW(see Fig. 3), simultaneously under microprogram 3020 controls, according to the information of address conversion (Fig. 6) that is included in subchannel controll block 2090 and the subchannel register 3010, use address translation buffer 3030(to see Fig. 4 C) information.Primary memory 2000 among Fig. 7 is split into hardware system district (HSA) 2001 and programmable district 2002, HSA2001 and includes the hardware information that uses for CPU1000 and I/O processor 3000.It can carry out access and renewal with the

microprogram

1050,1060 and 3020 of CPU and I/O processor, but can not use the general user's of visit CPU1000 machine instruction.Programmable district 2002 available machines used instruction access, with regard to OS or VMCP, it is a main storage area.Those I/O instructions that are associated with the operation of I/O device as starting I/O, all will be lined up in I/O request queue 2070 in the mode of request queue.2070 ask the controll block 2071 of real subchannel number (by the address pointer interconnection) to be formed by including I/O.After request queue was ranked to I/O, initiating signal was delivered to I/O processor 3000 by signal transmssion line 200.Request queue 2070 among 3000 couples of HSA2001 of I/O processor conducts interviews, and the request of sequentially reading is lined up unit 2071, processing I/O request.The I/O interrupt request is lined up in I/O IPQ 2080 by real priority of interrupt.Its structure is shown among Fig. 9.Can obtain 8 interrupt priority levels: 0,1,2,3,4,5,6 and 7.When sending I/O when instruction, by operand together with the subchannel dispatching priority of number coming together.Figure 10 shows subchannel controll block 2090(Fig. 7) in subchannel controll block 2091.These subchannel controll blocks are arranged by real subchannel numeral order, and its position number is determined by real subchannel fully.The start address of subchannel controll block 2090 places CPU1000(Fig. 7) a control register between the control register 1100.Interrupt priority level can be assigned to each subchannel.Suppose that the OS of virtual machine sends I/O instruction, specify certain one-level in subchannel number and 0～7 grade of interrupt priority level simultaneously.Because the pattern position 1090 of VM is " 1 " among Fig. 7, so I/O instruction execution microprocessor (μ P) 1050 sends this control information to virtual machine control program (VMCP).Control information sends VMCP to by a new program status word (PSW) in the VMCP zone prefix (PSA) 2100, as a kind of interrupt control information.Because when VM started, the PSA address of VMCP had been stored Fig. 7 at VMCP prefix register 1010() in, so addressable this address.

VMCP number handles the subchannel of virtual machine OS appointment as the virtual subnet channel number, it is converted to real subchannel number and manages real subchannel state.As the fruit subchannel number is that effectively VMCP sees Fig. 6 with regard to assigned address transitional information 2800() and replace the operating system of virtual machine to send the I/O instruction.

Interrupt priority level by virtual machine OS appointment is virtual interrupt priority level.VMCP is sending virtual interrupt priority level in as real interrupt priority level the I/O instruction.Therefore, real interrupt priority level will be shared with the OS of each virtual machine.So, the real interrupt priority level formation of the I/O IPQ 2080 of the mixed Fig. 9 of being arranged in of I/O interrupt request that sends from each virtual machine OS subchannel.

The reasons are as follows of execution of intervening the I/O instruction of virtual machine OS by VMCP:

(1) must convert real subchannel number to by the virtual subnet channel number of virtual machine OS appointment.

(2) because real subchannel number can be shared by the OS of each virtual machine, so need the subchannel scheduling.

A kind of method that Figure 11 interrupts for control I/O.I/O interrupt request from subchannel sends is detected by I/O processor 3000, and corresponding subchannel controll block comes (see figure 7) in the I/O IPQ 2080.The structure of I/O IPQ as shown in Figure 9.Subchannel controll block is by the order queuing of real interrupt priority level.Corresponding real position of interrupting unsettled register 1042 shown in Figure 11 is become " 1 ", when the position of position of interrupting unsettled register 1042 and corresponding real interrupt priority level mask bit register 1041 all is " 1 ", when the I/O mask bit of PSW1020 also is " 1 ", then starting is in that I/O interruption of corresponding real interrupt priority level, and this control signal is sent to I/O Interrupt Process microprogram 1060.Aforesaid operations is finished by hardware circuit shown in Figure 11.

As mentioned above, real interrupt priority level and each virtual machine OS are shared in dummy machine system.So, at the virtual machine run duration,, that is be set to " 1 " the OR function state of each position of real interrupt priority level mask bit register 1041 in the interrupt priority level mask bit of each virtual machine OS, make and interrupt acceptable always.The I/O mask bit of PSW1020 also is set to " 1 ".Thereby, a position of interrupting unsettled register 1042 as fruit changes over " 1 " by the I/O interrupt request that subchannel sends, so, the output of certain in the AND gate 1046 will become " 1 ", the output of OR-gate 1043 becomes " 1 ", the output of AND gate 1044 also becomes " 1 ", coming corresponding high interrupt priority 〈 ﹠﹠ so I/O Interrupt Process microprogram 1060 makes〉subchannel in the IPQ withdraws formation (Fig. 9), so that this interruption is reflected to the prefix of MCP.IPQ as the fruit interrupt priority level is empty, and the real position of interrupting unsettled register 1042 of then real interrupt priority level is set to " 0 ", and the unsettled register of consequent interruption is cleared.By interruption reflection to VMCP, control information is transmitted to the I/O interrupt handling routine of VMCP, the real subchannel that request I/O is interrupted is number as the I/O interrupt parameters and give VMCP together corresponding VM number, and VMCP finishes following processing, so that I/O is interrupted being reflected to virtual machine.

(1) real subchannel number is converted to the virtual subnet channel number.

(2) check the interrupt priority level mask bit register of VM and the I/O mask bit of PSW, so as to determining that this I/O interrupts whether can accepting.

(3), then this interruption is reflected to the prefix PSA of VM if VM accepts interruption.

(4) if VM does not accept interruption, then this interruption is sentenced pending status by VMCP.

Because real interrupt priority level is shared by each VM, so must be the OR function state (be generally " 1 ") of screening-off position in the corresponding mask bit of each VM.As a result, can not priority of interrupt even in VM, belong to, VMCP is interrupted.Under these circumstances, I/O interrupts sentencing pending status by VMCP.So, concerning the I/O instruction of being sent to subchannel, need be by the simulated operation of VMCP intervention.

As mentioned above, in the I/O of the virtual machine OS of former dummy machine system carries out,, need utilize the function of I/O processor for directly 3 grades of CCW of execution and 2 grades of CCW.Otherwise want VMCP constantly to intervene exactly and carry out simulated operation.So have the simulation house-keeping that load that higher I/O sends frequency will increase VMCP.

The objective of the invention is to reduce the I/O instruction of virtual machine OS and the simulation house-keeping that I/O interrupts with VMCP; Support the I/O instruction of VM and the direct execution that I/O interrupts with hardware and microprogram.

According to the present invention, in the system that contains dummy machine system (VMS), have at least among the VMS operating system can by a genuine computer system (main system) and control VMS control program, whether the I/O equipment of main system takies by the OS special use or by OS, determines according to the information that is stored in the genuine computer system.If the I/O equipment of the I/O starting order appointment of sending by I/O instruction rather than by OS is specialized in the OS that is moving and used, then this I/O equipment is just issued in the I/O instruction; When specializing in the OS that moving and use, then VMCP is interrupted.

From the detailed description of doing below in conjunction with accompanying drawing, just can be well understood to the present invention.Wherein:

Fig. 1 is the calcspar by the genuine computer system of general OS control;

Fig. 2 is the calcspar of dummy machine system in the past;

Fig. 3 is the hierarchy of memory of virtual machine in the past;

Fig. 4～11st, the example of prior art; Wherein:

Fig. 4 A～4C is an address translation table;

Fig. 5 is the configuration that occupies the VM of a continuum of real main storage;

Fig. 6 is to be to carry out the I/O instruction that the I/O simulation of VM is sent by VMCP;

Fig. 7 is the configuration of main system;

Fig. 8 is the I/O request queue;

Fig. 9 is an I/O IPQ;

Figure 10 is real subchannel controll block;

Figure 11 is the I/O interrupt circuit;

Figure 12 to Figure 22 is relevant with the present invention, wherein:

Figure 12 is the structure of main system;

Figure 13 is the prefix control table;

Figure 14 is the address control table of conversion table;

Figure 15 is the virtual machine control table;

Figure 16 is actual subchannel controll block;

Figure 17 is the starting virtual machine instructions;

Figure 18 is the dummy machine system control register;

Figure 19 is dummy machine system controlling features position;

Figure 20 A and 20B have described the mode of assigned interrupt priority;

Figure 21 is the dummy machine system interrupt control register;

Figure 22 is a dummy machine system I/O interrupt circuit.

Narrate optimum implementation of the present invention now.Figure 12 has provided the general construction configuration of one of specific embodiment of the invention.

Each ingredient of CPU1000 ' and Fig. 7's is similar, but wherein the function of some part expands to some extent.The same (the I/O request queue 2070, I/O IPQ 2080 and real subchannel controll block 2090 ') of the ingredient that hardware system district (HSA) 2001 comprises and Fig. 7.But prefix control table 2300, conversion table address control table 2400 and virtual machine control table 2700 have comprised fresh information.

The same (the virtual machine control program PSA2100 of the ingredient in programmable district 2002 and Fig. 7, VM1PSA2110, VM2PSA2120, (and PSA of other VM), virtual machine control program 2200, be converted to the address translation table 2010 of 1 grade of storer by 2 grades of storeies, be converted to the address translation table 2040 of 2 grades of storeies by 3 grades of storeies).But interrupt priority level progression conversion table 2500 and subchannel conversion table 2600 have comprised fresh information.I/O processor 3000 ' expand to some extent with the structurally similar but function of I/O processor 3000 among Fig. 7.Below the new improvement content in hardware system district 2001 and the programmable district 2002 is done new explanation.

Figure 13 is prefix control table 2300.It comprises virtual machine control program PSA address, VM1PSA address, VM2PSA address and VM3PSA address.Though do not mark one by one in Figure 13, other virtual machines PSA address also can be deposited with in this table.The PSA address is by the microprogram visit of CPU1000 ', and they are the addresses in programmable district 2002 main systems.When virtual machine starts, virtual machine PSA address is transmitted as one of enabled instruction operand; When enabled instruction was performed, it was stored in the corresponding entry of prefix control table 2300.The start address of prefix control table 2300 leave in some control registers 1100 of CPU1000 ' ' in (seeing Figure 12).The prefix control table is not essential for selecting for use.Need to use it under a certain situation, this point explains later on again.Figure 14 is conversion table address control table 2400.For each virtual machine, the start address of its control subchannel conversion table 2600 and the start address of interrupt priority level conversion table 2500.The start address of conversion table address control table 2400 also leave in some control registers 1100 of CPU1000 ' ' among.The method of searching subchannel conversion table 2600 and interrupt priority level conversion table 2500 as shown in figure 14.Virtual subnet channel number (two bytes) is split up into D0.256 and D1, can search preceding half table 2601 by D., and 2601 are indicated by the content of corresponding clauses and subclauses in the address control table 2400.The address of half table 2602 in back is left preceding half table 2601 in, in 2601 D0 the clauses and subclauses, so that search D1 clauses and subclauses of half table 2602 in back.In this way, can obtain corresponding real subchannel D0 ' 256+D1 '.The corresponding entry that only need read conversion table 2500 just can convert virtual interrupt priority level to corresponding real interrupt level.Group channel number conversion table 2600 and interrupt priority level conversion table 2500 are to be specified by VMCP order, and during perhaps according to the definition information definition virtual machine of virtual machine, 2600 and 2500 these two tables are formulated by VMCP; When virtual machine activation, 2600 and 2500 are specified by the starting order operand.When carrying out starting order, 2600 and 2500 leave in the corresponding entry of conversion table address control table 2400.Conversion table 2600,2500 and 2400 for selecting for use, is not requisite all.Defer to such criterion as long as adopt the virtual machine of I/O executive system of the present invention in dummy machine system: the virtual subnet channel number equals real subchannel number, and virtual interrupt priority level equals real interrupt priority level, and so above-mentioned these conversion tables just all are unnecessary.

Shown in Figure 15 is the content of virtual machine control table 2700.It comprises the main memory size (Z of each corresponding virtual machine ₀, Z ₁), by the address of 2 grades of memory address translation conversion table 2010 that is 1 grade of storage address (RATORO, RATOR1 ...).This information is provided by virtual machine definition information, and by the starting virtual machine instructions it is stored in the corresponding entry of the virtual machine control table 2700 among the HSA2001.The start address of virtual machine control table 2700 leave in the some control registers 1100 of CPU1000 ' ' in (seeing Figure 12).Among the HSA2001 start address of controll block leave in control register 1100 among the CPU1000 ' ' in, this is the same with original system.Take primary memory 2002(Fig. 5 when the virtual machine of supporting I/O executive system of the present invention is defined as) on continuum during as main memory, virtual machine control table 2700 can be by the conversion table 2010(2 of definition upper and lower limit) replace.Adopting conversion table 2010(2 shown in Figure 5) time, specify by the virtual machine activation instruction, LLA α i and α i+1(i=1,2,3 ...).When carrying out enabled instruction, conversion table 2010(2) corresponding entry is placed among the HSA2001.Figure 16 shows that real subchannel controll block 2090 ', and one real subchannel controll block 2091 ' and it virtual machine information district 2092 ', virtual machine information district 2092 ' contain mode field, the virtual machine sequence number, the virtual subnet channel number, corresponding real subchannel number, virtual interrupt priority level, corresponding real interrupt priority level and channel command word CCW information of address conversion 2094 mode fields include some Q-characters, and whether be used for indicating this subchannel occupied and whether be in I/O and directly carry out suppression mode.The content of CCW information of address conversion 2094 is the same with the information of address conversion of Figure 10 2092.When under following three kinds of situations: during the defining virtual machine, or when coming designated virtual machine, or when carrying out the I/O instruction by the virtual control program order, virtual machine information district 2092 ' in information all come given by virtual machine definition information.

During when the defining virtual machine or by the command specifies virtual machine of virtual machine control program, special-purpose real subchannel or special-purpose real interrupt priority level have also just been specified simultaneously.After special use is designated, virtual machine information district 2092 ' in will put into following field:

Subchannel specific features position in the mode field 2093;

The direct execution pattern of I/O suppresses Q-character and places " 0 " usually, and the direct execution pattern set of I/O is in status of support;

The dedicated virtual machine sequence number;

Virtual subnet channel number and real subchannel number;

(real address conversion table originating register (RATOR) is seen Fig. 4 a), is placed in channel command word (CCW) information of address conversion 2094 to be converted to the start address of the address translation table of 1 grade of storer by special-purpose VM primary memory (2 grades of storeies).If special-purpose VM occupies primary memory shown in Figure 5, so just can determine upper limit α i and lower limit α i+1(i=1,2,3 ...).

In shared subchannel, when carrying out the I/O instruction, this information is to determine as required.In this case, it is placed on I/O and issues in the respective field of virtual machine VM block of information.

Figure 17 shows that a kind of form of starting VM instruction.The instruction of numeral 2900 expression starting VM, numeral 2910 expression operands.Operand 2910 comprises the VM sequence number, VM program status word (PSW) PSA, the VMPSA address, subchannel conversion table 2600(Figure 14) start address, interrupt priority level conversion table 2500(Figure 14) start address, be converted to address translation table 2010(Figure 15 of main system main memory by the VM primary memory) start address RATOR(see Fig. 4 a), and VM main memory capacity.For back two, when continuum that the VM that will start uses primary memory 2002 shown in Figure 5 during, can specify upper limit α i and lower limit α i+1(i=1 as the VM primary memory, 2,3 ...).When starting VM, the VM working procedure status word in above-mentioned those operand information, VMPSA address, real interrupt priority level state and VMS controlling features position also just have been determined, and other many information are then determined by VM definition information when definition VM.The real interrupt priority level single user state and the VM system controlling features position of real interrupt priority level state will be explained in the back.Those operands are stipulated by VM control program (VMCP).Though information shown in Figure 17 needs as operand, start the instruction form not necessarily shown in Figure 17 of VM.Figure 18 shows that the control register 1080 of VMS.Register 1081 comprises the VM sequence number of moving, and it is stipulated by the instruction of starting VM.The content of field operand 2910(Figure 17 that the content of this register is instructed by starting VM) is given.Figure 19 shows that controlling features position 1090 ' (the seeing Figure 12) of VMS.These Q-characters are by a field initialize of VM starting order (Figure 17) operand.They have following meaning respectively.

V: at the VM run duration, it is " 1 ".When virtual machine control program moves or when the genuine computer pattern, it is " 0 ".It places " 1 " by starting VM instruction; When by interrupt instruction control information being sent to VMCP, it places " 0 ".This and prior art system (Fig. 7) are same.

H: at the VM run duration, in the time can directly carrying out privileged instruction, it places " 1 ".When this Q-character is " 1 ", all directly carry out by the instruction execution circuit of CPU1000 ' in the operating most of privileged instructions of VM.When H was " 1 ", the same with original system (Fig. 7), it was a high speed VM pattern.

R: when the OS of VM is restricted, cause the virtual subnet channel number to equal real subchannel number, when virtual interrupt priority level equaled real interrupt priority level, R was placed in " 1 ".When R is " 1 ", then need not to carry out subchannel number conversion and interrupt priority level is changed (in this case, shown in Figure 14 conversion table 2400,2600 and 2500 be exactly unnecessary) by microprogram.

D: when can by the present invention by VM(under the situation that virtual machine control program is not done to intervene) carry out direct I/O when carrying out, D is " 1 ".It places " 1 " by the starting VM instruction of virtual machine control program at first.

N: when the VM that is turning round has one to interrupt the unsettled factor (be actually sentenced by VMCP unsettled) on shared interrupt priority level for VM, it is placed in " 1 ", virtual interrupt priority level mask bit for the VM that turning round, be interruptable (when the I/O of VM program status word (PSW) mask bit is " 0 ", can not interrupt) at this moment.When the instruction of checking the VMI/O interrupt request that can be accepted by virtual interrupt priority level is performed, will use this Q-character.It passes through starting VM instruction initialize by virtual machine control program.

Figure 20 a and 20b are a kind of methods of distributing real interrupt priority level.Here 32 real interrupt priority levels of from 0 to 31 have been used.Real interrupt priority level 0 is a limit priority.By virtual machine control program special use.The real interrupt priority level that is exclusively used in each VM is distributed to each special-purpose VM to arrange (is descending for interrupt priority level) from the ascending order of real interrupt priority level 1 beginning.Shared interrupt priority level is according to distributing to each VM from the descending (interrupt priority level is ascending order) of real interrupt priority level 31 beginnings.In Figure 20 a and 20b, real interrupt priority level 1 is assigned to the virtual interrupt priority level 0 of VM1, and it is special-purpose; Real interrupt priority level 31 is distributed to virtual interrupt priority level 1-7, and it is shared by each VM.For VM ₂And VM ₃, the distribution of real interrupt priority level is shown in Figure 20 a and 20b.VM ₁In virtual interrupt priority level be actually 0 or (1-7).Therefore, there are two real interrupt priority levels can be effectively by VM ₁OS use.Can limit this operating system by operational order.The special interrupt priority level that is exclusively used in VM fully should be determined according to the general plan of VMS, and should be controlled by virtual machine control program.The shared state 1 of the special use of the real interrupt priority level of Que Dinging provides (seeing Figure 17) by the operand that starts the VM instruction thus, and when carrying out this instruction, special-purpose shared state 1 will be deposited with in the real interrupt priority level single user state register 1049 (Figure 21).

Shown in Figure 21 be real interrupt priority level mask bit register 1041 ', real interrupt unsettled register 1042 ', real interrupt priority level status register 1045 and real interrupt priority level single user state register 1049.They all be included in the I/O interrupt circuit 1040 of Figure 12 ' in.Register 1041 ' and 1042 ' with those registers in the prior art system be similar, but figure place has increased.In Figure 21, they have 32, are 84 times in the prior art system, and the purpose of increase is to support the dedicated system of real interrupt priority level among the VM.Because same meaning, thus omitted register 1041 ' and 1042 ' explanation.Narrate the meaning of real interrupt priority level status register 1045 below.Its implication is, as n(0-31) when the position was " 0 ", real interrupt priority level n was exclusively used in the VM that is moving.In other cases, it places " 1 ", below the implication of the real interrupt priority level single user state register 1049 of narration.As C(0-31) when the position is " 0 ", mean that interrupt priority level C is exclusively used in VM really; When C was " 1 " when the position, real interrupt priority level C was shared.Register 1045 and 1049 operand initializes by starting VM instruction.Real interrupt priority level mask bit register 1041 ' by VMCP control and renewal.The real unsettled register 1042 ' of interrupting by 3000 ' (Figure 12) set of I/O processor, and reset by I/O Interrupt Process microprogram 1060 ' (Figure 22).

Figure 22 be I/O interrupt circuit 1040 of the present invention ' wiring diagram.For for simplicity, Figure 22 only provides 10 real interrupt priority levels, but in fact 32 priority that connect with similar approach are arranged.Suppose real interrupt priority level C(C=0-31) there is a unsettled factor of interruption (to that is to say, have the subchannel of interrupt request to be arranged in the class queue of real interrupt priority level (C) of I/O IPQ 2080, simultaneously unsettled register 1042 ' corresponding positions be placed in " 1 ").If interrupt priority level C is exclusively used in the virtual machine that was moving at that time, the corresponding positions of then real interrupt priority level status register 1045 is " zero ", OR-gate 1048 is with the content of written-out program status word (PSW) I/O mask bit, thereby the I/O interrupt mask bit of program status word (PSW) 1020 can play effective function.Therefore, have only when corresponding real interrupt priority level mask bit register 1041 ' corresponding positions be that the I/O mask bit of " 1 " and program status word (PSW) is when also being " 1 ", be only " 1 " with the corresponding output of door 1047, this moment, I/O interrupted being started, and this control information be sent to I/O Interrupt Process microprogram 1060 '.When interruption priority C is shared or is exclusively used in other virtual machines, then the corresponding positions of register 1045 is " 1 ", the corresponding output of OR-gate 1048 is " 1 ", the I/O mask bit of program status word (PSW) 1020 is inoperative, thereby when corresponding real interrupt priority level mask bit register 1041 ' when being " 1 ", I/O interrupts being started.Behind microprogram 1060 ' make Interrupt Process, if the IPQ of interrupt priority level C is empty, then unsettled register 1042 ' corresponding positions remove by microprogram and return " 0 ".

Explanation now: use hardware, the method for virtual machine OSI/O instruction and I/O interruption is carried out and handled to microprogram on the primary memory and information.

Here made following 2 hypothesis, and virtual machine is in high speed virtual machine pattern.

(1) the whole primary memory of virtual machine resides in the primary memory of main system.

(2) value of virtual machine OS connects I/O and carries out the subchannel that (not having the virtual machine control program intervention to comprise the direct execution that I/O is interrupted) only supplied with nonsharod subchannel and dedicated interrupt priority is arranged.

When starting during virtual machine, virtual machine control program is with following a kind of method, give the operand of starting VM instruction of Figure 17 and real interrupt priority level mask bit register 1041 ' a C set.

As real interrupt priority level C(0-31) when being exclusively used in the virtual machine that is moving, the screening-off position of the virtual interrupt priority level of respective virtual machine OS (for hypothesis for simplicity has only one-level) in position C.

When interrupting priority C when being exclusively used in other virtual machines, the AND-function set of the I/O mask bit of the respective virtual interrupt priority level mask bit of virtual machine and virtual machine program status word in the C position.In other words,, the interruption of interrupt priority level C can not cause problem if lagging behind, then can be position C set in " 0 ".

When interrupting priority C by each virtual machine when shared, a C set in " 1 ".

At the virtual machine run duration, when changing virtual interrupt priority level mask bit, this change will be reflected to real interrupt priority level mask bit register 1041 ' (Figure 21) immediately.Correspondingly, the instruction that changes the virtual interrupt priority level mask bit of OS can be controlled the processing procedure preface by virtual machine and simulate, perhaps can by the microprogram of CPU handle this change be reflected to register 1041 ', this with previous system in done the same.When starting was in the virtual machine of high speed virtual machine pattern, the program status word (PSW) of virtual machine is placed on Figure 17 started in the virtual machine working procedure status word of virtual machine instructions operand, and it is placed on 1020 li of the program status word (PSW) (Figure 12) of CPU1000 '.Therefore, the I/O mask bit of program status word (PSW) is consistent with operating virtual machine I/O shielding with operating virtual machine I/O mask bit.Because the virtual machine run duration, the variation of the program status word (PSW) of operating system can be reflected to program status word (PSW) 1020 immediately, so can realize this consistance.By immediate execution mode, can be reflected to the instruction that changes the OS program status word (PSW) program status word (PSW) 1020 of CPU1000 ', perhaps can simulate and reflect by virtual machine control program.Carry out after those set,, can be sent to control information the OS of virtual machine by starting VM instruction (Figure 17).When execution command, the ongoing virtual machine serial number register 1031 of Figure 18, program status word (PSW) 1020(Figure 12 of CPU1000 '), the corresponding entry of level control table (LCT) before Figure 13.The corresponding entry of Figure 14 conversion table address control table 2400, the corresponding entry of Figure 15 virtual machine control table, the real interrupt priority level status register 1045 of Figure 21 and Figure 19 VMS controlling features position all are predisposed original state.

Our hypothesis, I/O instruction is to be sent by VME operating system, microprogram 1050 ' control under, the I/O of CPU1000 ' carries out the following processing of circuit 1030 ' finish.

(1) if be not in high speed virtual machine state (VMS controlling features position H=" 0 " sees Figure 19), then utilize prefix register 1010(Figure 12 of virtual machine control program), the PSA2100 that interrupts being reflected to VMCP, virtual machine control program is interrupted.

(2) when being in high speed virtual machine state (VMS controlling features position H=" 1 "), check whether be in the direct executing state of virtual machine I/O (VMS controlling features position D=" 1 ") (Figure 19).

(3) when D=" 0 ", interrupt virtual machine control program.

(4) when D=" 1 ", check VMS controlling features position R.If R=" 0 " then searches corresponding virtual subnet channel number conversion table 2600, so that given virtual subnet channel number is converted to real subchannel number.If virtual interrupt priority level is provided by instruction operands, then search the interrupt priority level conversion table, so that it is converted to real interrupt priority level.Whether it is special-purpose, check by real interrupt priority level single user state register 1040, and it write subchannel controll block VM block of information 2092 ' mode field in (Figure 16).

This will write the corresponding relation between virtual interrupt priority level and the real interrupt priority level.When R=" 1 ", do not require any conversion, and write same value.

(5) when the real subchannel controll block 2091 ' (Figure 16) that is obtained be special-purpose subchannel, and when dedicated interrupt priority is arranged, carry out the I/O instruction.The class of operation of operation after this and genuine computer system seemingly.When requiring the asynchronous I/O operation of equipment, subchannel in I/O request queue 2070, line up (Fig. 8).Condition code and control information are turned back to the program of sending I/O.

(6) if the real subchannel that is obtained is a shared subchannel, or interrupt priority level is shared, then interrupts virtual machine control program and carries out simulated operation, and the simulated operation of remaining process being entrusted to VMCP carries out.

(7) if during (also can accept) I/O interrupt request that the I/O that is sent by virtual machine OS instruction is check can be accepted by virtual interrupt priority level, then carry out following the processing by virtual interrupt priority level mask bit.Check that interrupt request is corresponding to the practical interrupt priority level that now moves virtual machine.If there is no the I/O interrupt request then should be checked shared interrupt priority level.Keep because virtual machine control program is being controlled the interruption of shared interrupt priority level, thereby must send control information to virtual machine control program.But,, thereby use controlling features position N(Figure 19 of VMS owing to this and rule of directly carrying out are disagreed).When N=" 1 ", this means that virtual machine control program is keeping the I/O of examine to interrupt keeping (can be accepted by shared interrupt priority level and virtual interrupt priority level).So, interrupt virtual machine control program.When N=" 0 ", do not exist such I/O to interrupt keeping, virtual machine control program needn't interrupt, and allows directly to keep straight on.The I/O Interrupt Process now is described.

(1) the I/O interrupt request sent of I/O equipment is by I/O processor 3000 ' detection, corresponding real subchannel controll block HSA2001(Fig. 9) the corresponding real interrupt priority level of I/O IPQ 2080 is lined up, and this is as formerly having in the technological system to be done.

(2) I/O processor 3000 shown in Figure 22 ' with real interrupt unsettled register 1042 ' the relevant position in " 1 ", this is also as formerly having in the technological system to be done.

(3) real interrupt priority level mask bit register 1041 ' by foregoing mode set.The I/O interrupt circuit of Figure 22 is worked in a manner described.Our supposition has been started I/O and has been interrupted, and control information pass to I/O Interrupt Process microprogram 1060 '.

(4) if having the interruption of the real dedicated interrupt priority of virtual machine, the virtual machine that then occupies can be accepted the interruption of virtual interrupt priority level because real interrupt priority level mask bit register 1041 ' and real interrupt priority level status register 1045 in set.If the virtual machine that occupies can not be accepted interruption, because program status word (PSW) 1020I/O mask bit and register 1041 ' and 1045 effect, for that real interrupt priority level, I/O can not take place interrupt, this control information will not send 1060 to ', it is sentenced unsettled by hardware.

(5) I/O interrupts the following processing of microprogram 1060 ' execution.

(1) the real interrupt priority level C that interrupts according to request removes the real subchannel (Fig. 9) in the I/O IPQ 2080.

(2) check VMS controlling features position 1090 ' virtual machine Q-character V and high speed virtual machine pattern feature position H(Figure 19), if V=" 0 " or H=" 0 " then will interrupt being reflected to the PSA of VMCP.Use prefix register 1010(Figure 12 of VMCP).

(3) if V=" 1 " and H=" 1 " check the direct execution pattern of the I/O position D of virtual machine.If D=" 0 ", it is not the direct execution pattern of I/O just, and the PSA that interrupts being reflected to VMCP.

(4) if D=" 1 " then carries out following the processing.

(a) determine that with the mode field (Figure 16) of real subchannel controll block subchannel is special-purpose, if it is a shared subchannel, then the PSA that interrupts being reflected to VMCP.

(b) if the real interrupt priority level C that request is interrupted is exclusively used in the virtual machine that is moving.That is to say, are " 0 " (seeing Figure 21) as the corresponding positions of fruit interrupt priority level status register 1045, then interrupting being reflected to existing PSA with virtual machine, make now to work on virtual machine.Use virtual machine prefix register 1070(Figure 12).With real subchannel controll block 2092 ' in virtual subnet channel number or virtual interruption priority number, the I/O interrupting information is reflected to the virtual machine prefix.

(c) when real interrupt priority level C is exclusively used in other virtual machines, interrupting being reflected to virtual machine control program.Then, by virtual machine control program interruption is reflected to the PSA of VM.

(d) when real interrupt priority level C is shared, interrupting being reflected to virtual machine control program.Then, by virtual machine control program interruption is reflected to virtual machine.Virtual machine can not accepted interruption.In this case, virtual machine control program the I/O interruptions with unsettled.

As mentioned above, special-purpose and when being in special-purpose real interrupt priority level when subchannel, provide the I/O of VME operating system directly to carry out (need not the intervention of virtual machine control program) can for this subchannel.Interrupt for I/O, only interrupt, just directly carried out from the I/O that now uses the virtual machine nonsharod subchannel.The I/O that comes for other virtual machine nonsharod subchannels interrupts, and virtual machine control program will be intervened, because this will dispatch each virtual machine.

The direct I/O execution pattern inhibition Q-character of mode field 2093 is generally " 0 " in the real subchannel controll block of Figure 16, so that ensure the direct I/O execution pattern of this subchannel.In nonsharod subchannel, the operating system that the I/O instruction does not come self virtualizing machine, but from the virtual machine that occupies, but it can be from virtual machine control program.In the case, the direct I/O execution pattern in state subgroup section 2093 is suppressed Q-character 1 set in " 1 ", until till the I/O of the virtual machine control program end.So that suppress the direct execution pattern of the I/O of this subchannel.

Therefore, this Q-character can and reset in set under the virtual machine control program control.In above-mentioned I/O executive system, point out following some.

(a) the R position of dummy machine system controlling features position 1090 ' (Figure 19) can be omitted.If virtual subnet channel number and virtual interrupt priority level always will be changed, perhaps work as dummy machine system and use direct I/O executive mode of the present invention, and these numbers are always identical, then the R position is unnecessary.

(b) the D Q-character can replace with the H Q-character, but high speed virtual machine pattern feature position H can not control the direct execution of I/O instruction, because except that the I/O instruction, it also controls the direct execution of privileged instruction.

(c) in the I/O Interrupt Process, as mentioned above, come the I/O of the special-purpose real interrupt priority level of self virtualizing machine (except the virtual machine that is moving) to interrupt, be reflected to virtual machine control program.Because the virtual machine that occupies can receive interruption,, with the virtual machine control program access stencil virtual machine control program is handed in control then so interrupt to be reflected to the PSA of that virtual machine.The PSA address of virtual machine can be determined by the prefix control table of Figure 13.In this case, be necessary to determine the program status word (PSW) of virtual machine, therefore need information, it can be determined according to the virtual machine sequence number in various manners, though do not illustrate it.

(d) start address of subchannel conversion table, the start address of interrupt priority level conversion table, real interrupt priority level status register 1045 and real interrupt priority level single user state register 1049(Figure 21), all the operand by the starting virtual machine instructions comes initialize (Figure 17).In other words, they can instruct initialize separately by of virtual machine control program.

As mentioned above, according to the present invention, the I/O instruction is sent and can directly be carried out by VME operating system, causes the I/O simulation house-keeping of VMCP to significantly reduce.This is to make the virtual machine performance very near a key function of genuine computer.

Claims

1, in a system with dummy machine system (VMS), VMS has an operating system (OS) at least, can move simultaneously by means of the control program (VMCP) of a genuine computer system (main system) and a control VMS, and native system is characterised in that:

The I/O manner of execution of dummy machine system comprises following a few step,

Specify genuine computer when the virtual machine of decision dummy machine system real subchannel or the special use of real interrupt priority level;

When being exclusively used in an OS in service, the I/O of this subchannel of test instruction, determines whether each I/O equipment of above-mentioned main system is exclusively used in a specific OS according to the information that is stored in the genuine computer; With

When above-mentioned I/O equipment is scheduled to be exclusively used in operating OS, send above-mentioned I/O instruction to this I/O equipment from above-mentioned OS.

2, according to a system of claim 1 definition, the primary memory of an OS in the primary memory of its main system (real main storage) has first kind of means to be used for the address that convert real main storage of address from the OS primary memory; With second kind of means are the main memory address that the virtual address translation of OS become OS when OS sets up virtual memory, it is characterized in that:

The I/O manner of execution of this dummy machine system comprises following a few step,

When OS sends the promoter passage and carries out the I/O instruction of I/O operation, determine whether be exclusively used in the OS that is moving by the subchannel of this I/O instruction appointment;

When I/O equipment is dedicated to the OS of this operation,, the data address translation that comprises in the address of the I/O instruction appointment of above-mentioned indication I/O operation and the I/O operation is become the real main storage address by above-mentioned first kind and/or second kind of means;

Having determined subchannel when above-mentioned means is when being exclusively used in operating OS, carries out above-mentioned I/O instruction;

Otherwise the operation of interrupt operation system turns to virtual machine control program with control.

3, according to a system of claim 1 definition, wherein there is maintenance to interrupt the means of prior information, every kind of corresponding a kind of priority of means is used for indicating acceptance and does not accept the I/O interruption, is characterized in:

When one or more above-mentioned interrupt priority levels are predetermined when being exclusively used in an OS, make the interrupt control information of the real interrupt priority level of the OS that is exclusively used in operation equal to indicate the empty interrupt control information of operating OS interrupt priority level;

The acceptance of interrupting based on corresponding I/O determines that with the interrupt control information of the above-mentioned interrupt priority level of receive status not can the I/O interrupt request be accepted;

When the I/O interrupt request is defined as accepting, then the operating OS of this interrupt notification;

4, according to a system of claim 3 definition, a direct execution pattern Q-character of I/O is arranged wherein, it is used for specifying the I/O operator scheme, it is characterized in that:

Above-mentioned notifying process can be realized;

And when above-mentioned Q-character is in second state, just interrupts the OS of interrupt run and control is turned to virtual machine control program with arbitrary I/O instruction and I/O among the OS.

5, according to a system of claim 1 definition, it is characterized in that:

The I/O manner of execution of this dummy machine system may further comprise the steps,

Utilize first kind of above-mentioned conversion means, the virtual subnet channel number by I/O instruction appointment is converted to the real subchannel that calls the device address number.

6, according to a system of claim 1 definition, it is characterized in that:

Virtual interrupt priority level by I/O instruction appointment is converted to the real interrupt priority level that calls the priority conversion means.

7, according to a system of claim 5 definition, it is characterized in that:

When the I/O interrupting information is informed to operating operating system, the real subchannel of I/O interrupt request number is converted to the virtual subnet channel number.

8, a system according to claim 5 or 6 definition has an I/O address to equate the pattern feature position, is used to refer to the operator scheme of I/O, it is characterized in that:

The I/O manner of execution of this virtual system comprises following a few step,

Equate I/O operator scheme of pattern feature position appointment by an I/O address;

When above-mentioned Q-character is in first state, above-mentioned device address and priority conversion means can be set up;

When above-mentioned Q-character is in second state, use virtual subnet channel number or virtual interrupt priority level as real subchannel number or real interrupt priority level.

9, according to the I/O manner of execution of claim 2 definition, it is characterized in that: said first means are that conversion comprises the fixedly exchange between OS primary memory and the real main storage.

10, according to the I/O manner of execution of claim 3 definition, it is characterized in that: above-mentioned notifying process can be determined the prefix of operating OS by means of the prefix addresses storer means of OS in service, and the I/O interrupt notification is arrived this prefix.

11, the I/O executive system of a dummy machine system has:

A dummy machine system (VMS), it can make an operating system (OS) move simultaneously by a genuine computer system (main system) at least;

A virtual machine control program (VMCP) is used for controlling above-mentioned dummy machine system, it is characterized in that:

Above-mentioned I/O executive system includes,

Determine whether each I/O interrupt priority level is exclusively used in the means of an operating OS;

Above-mentioned definite means have the register of depositing the status information of the real interrupt priority level of a plurality of real I/O interrupt priority levels in the above-mentioned genuine computer system;

When being exclusively used in operating OS, there is certain methods to make to have at least a unit to be in first state in the above-mentioned register and accepts the control of operating operating system with the corresponding real interrupt priority level in the some unit of above-mentioned register;

When above-mentioned corresponding real interrupt priority level by shared or when being exclusively used in other operating system, have some modes can make this unit of above-mentioned register be in second state and pay no attention to the interrupt control of operating system in service.

12, one has in dummy machine system (VMS) system, and VMS has an operating system (OS) at least, can move simultaneously by means of the control program (VMCP) of a genuine computer system (main system) and a control VMS, and native system is characterised in that:

The I/O executive means of dummy machine system comprises the means of determining whether to be exclusively used in one to one corresponding to the subchannel of an I/O equipment OS; Determine that this subchannel is exclusively used in the means of which OS; When having determined that above-mentioned subchannel is exclusively used in operating OS, above-mentioned means send the means of the I/O instruction of this subchannel state of test to this subchannel.And when above-mentioned means determine that above-mentioned subchannel is not exclusively used in operating OS, interrupt the operation of this OS and control is turned to the means of VMCP.

13, according to a system of claim 12, in the primary memory (real main storage) of its main system, an OS primary memory is arranged, this main system has first means that an address translation of OS primary memory is become the address of real main storage and second means converts the virtual address of OS to the primary memory of OS when OS produces an empty storage address, it is characterized in that:

The I/O executive means of dummy machine system comprises:

When OS sends the I/O instruction of I/O operation of promoter passage, determine whether a subchannel by an I/O instruction appointment is exclusively used in the means of operating OS;

The means that address translation is the real main storage address to indicating during in operating OS address that the above-mentioned I/O of above-mentioned I/O operation indicates and above-mentioned I/O to comprise in operating by above-mentioned first means when the I/O device-specific; And

Determining above-mentioned subchannel when above-mentioned means is the means of carrying out above-mentioned I/O instruction when being exclusively used in operating OS, otherwise the means of interrupting the OS operation and control being turned to VMCP are arranged.

14, according to a system of claim 12, it is characterized in that:

The I/O executive means of dummy machine system comprise when an OS among the VM send test to VM when test I/O is interrupted unsettled I/O instruction in the I/O of real interrupt priority level of operating OS special use interrupt unsettled means; Determine that the I/O that OS that whether VMCP has at least one shared its operation of interrupt priority level equals " 1 " (promptly accepting) interrupts unsettled means; And interrupt when unsettled when VMCP has such I/O, interrupt the operation of OS and control is turned to the means of VMCP; Otherwise continue the means of OS operation.

15, a system according to claim 12 has the means that keep interrupt control information, the corresponding priority of each maintenance means, to indicate the acceptance that I/O interrupts or not accept, it is characterized in that: the I/O manner of execution of dummy machine system comprises when one or more above-mentioned interrupt priority levels are predetermined when being exclusively used in operating OS, makes the interrupt control information of OS of operation of the interrupt priority level of the OS that the interrupt control information of the real interrupt priority level of the OS that is exclusively used in operation equals to move.

16, according to a system of claim 15, it is characterized in that further comprising the I/O executive means of a dummy machine system, it comprises:

Determine that based on the interrupt control information of the above-mentioned real interrupt priority level that is exclusively used in operating OS can an I/O interrupt request received means; When the I/O interrupt request with special-purpose real interrupt priority level is determined when being acceptable, with the means of the OS that moves in this I/O interrupt notification virtual machine.

17, a system according to claim 16 has a direct execution pattern Q-character of I/O with assigned I/O operator scheme, it is characterized in that:

The I/O executive means of dummy machine system comprises:

When above-mentioned Q-character is in the means that first state can make above-mentioned notifying process set up; And

When above-mentioned Q-character is in second state, interrupts the OS of interrupt run and control is turned to VMCP by any one I/O instruction and I/O under the OS.

18, according to a system of claim 12, it is characterized in that:

The I/O executive means of dummy machine system comprises:

Instruct the empty subchannel of appointment number to be converted to the means of real subchannel number I/O, be called equipment ground conversion means.

19, according to a system of claim 12, it is characterized in that:

The I/O executive means of dummy machine system comprises:

Instruct the empty interrupt priority level of appointment to convert the means of real interrupt priority level to I/O, be called the priority conversion means.

20, according to a system of claim 18, it is characterized in that:

The I/O executive means of dummy machine system comprises:

When the I/O interrupting information is notified the OS of operation, the real subchannel of I/O interrupt request number is converted to empty subchannel number.

21, have the equal pattern feature position of I/O address of assigned I/O operator scheme according to a system of claim 18 or 19, it is characterized in that:

Dummy machine system comprises for the I/O executive means:

Be loaded with the means that the I/O address that indicates the I/O operator scheme equates the pattern feature position;

When being in first state, above-mentioned Q-character makes the means of the said equipment address and the work of priority conversion means; And

When above-mentioned Q-character is in second state, use empty subchannel number or empty interrupt priority level means respectively as real subchannel number or real interrupt priority level.

22,, it is characterized in that above-mentioned first means are conversions, comprise the fixedly exchange between OS primary memory and the real main storage address according to an I/O executive means of claim 13.

23, according to an I/O executive means of claim 16, it is characterized in that above-mentioned notification means can determine the prefix of operating OS by means of the prefix addresses storer means of OS of operation, and the I/O interrupt notification to prefix.

24, the I/O executive system of a dummy machine system comprises:

Can move a dummy machine system (VMS) of at least one operating system (OS) down simultaneously in a genuine computer system (main system); It is characterized in that also comprising with the control program (VMCP) of the above-mentioned VMS of control:

Determine whether each I/O interrupt priority level is exclusively used in the means of operating OS;

Above-mentioned definite means have the register of depositing the real interrupt priority level status information of a plurality of real I/O interrupt priority levels in the above-mentioned genuine computer system;

When being exclusively used in operating OS with the corresponding real interrupt priority level in the some unit of above-mentioned register, make to have at least a unit to be in first state in the above-mentioned register, and follow OS control means and

When above-mentioned corresponding real interrupt priority level is shared or is exclusively used in other OS, ignore the control of the OS of operation, make to have at least a unit to be in second state in the above-mentioned register.