CN1267828C - Electron system using bus between integrated circuits as interface and its data transmission method - Google Patents
Electron system using bus between integrated circuits as interface and its data transmission method Download PDFInfo
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- CN1267828C CN1267828C CN 03107781 CN03107781A CN1267828C CN 1267828 C CN1267828 C CN 1267828C CN 03107781 CN03107781 CN 03107781 CN 03107781 A CN03107781 A CN 03107781A CN 1267828 C CN1267828 C CN 1267828C
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Abstract
The present invention relates to an electronic system which takes a bus (I<2>C bus) among integrated circuits as an interface and a data transmission method thereof. The electronic system comprises a bus among integrated circuits, a plurality of auxiliary devices, a main control device and a selector, wherein the auxiliary devices are coupled with the bus among integrated circuits, and the auxiliary devices have the same I<2>C address. The main control device is coupled with the bus among integrated circuits, and is used for receiving and transmitting data. The selector is coupled with the bus among integrated circuits and the main control device, and is provided with a plurality of output ends which are respectively coupled with the auxiliary devices, and one auxiliary device is selected so as to be matched with the main control device for transmitting data.
Description
Technical field
The present invention relates to a kind of electronic system, relate in particular to electronic system and data transmission method thereof that a kind of use inter-IC bus (internal integrate circuit bus) interface transmits data.
Background technology
I
2C (Inter-Integrated Circuit, internal integrated circuit) bus is a kind of existing industrial standard serial bus, is used for a computer installation or other electronic system, realizes the connection and the data transmission of a plurality of integrated circuit or chip chamber.The inter-IC bus of standard has two lines, article one, begin (start), address (address), data (data), control (control), confirm (acknowledge) and stop signals such as (stop) in order to transmission for SDA (serial data) signal wire, and one be SCL (serial clock) signal wire, in order to transfer clock pulse (clock).
Briefly, when bus master assembly (master) will carry out data transmission, can transmit the start bit (start bit) of a uniqueness, exactly when the SCL signal wire is noble potential, the SDA signal wire can be by noble potential step-down current potential, and the SCL signal wire can become electronegative potential after a bit of time.And, the then address and the read of 8 (bit) of extended meeting behind the start bit, and contain 7 address bits and 1 read/write in follow-up 8.After these addresses and read/write transmission, the subordinate assembly (slave) that is addressed to can one of response be confirmed the position.Therefore, master component just can be carried out the transmission of data with the subordinate assembly that is addressed to.In general, computing machine or other electronic system limit the chip that is up to 8 same model usually and are connected to an inter-IC bus.
Please refer to Fig. 1, Fig. 1 utilizes the inter-IC bus interface to carry out the electronic system of data transmission in the prior art, when master component 110 will be carried out data transmission by internal integrated circuit interface 150 with subordinate assembly 120, master component 110 can produce an initial state, and internal integrated circuit start signal (start) is delivered to subordinate assembly all on the SDA signal wire 120,130 and 140.In order to respond this start signal, subordinate assembly 120,130 and 140 can be accepted each own address.The next clock period after initial state, address signals of master component 110 transmission (unique address that contains the subordinate assembly 120 of supporting the internal integrated circuit interface protocol).So the subordinate assembly 130 and 140 of being named by above-mentioned address signal all can not busyly not stagnate, the subordinate assembly 120 of being named simultaneously sends one and confirms that the position signal is on the SDA signal wire, inform that master component 110 can transmission of data signals, and pending data such as begin.
Above-mentioned initial state, exactly when the SCL signal wire is noble potential, the SDA signal wire becomes electronegative potential by noble potential, and the SCL signal wire can become electronegative potential after a bit of time; And halted state, exactly when the SDA signal wire is electronegative potential, the SCL signal wire becomes noble potential by electronegative potential, and the SDA signal wire also becomes noble potential through a bit of time.
Yet, when if all subordinate assemblies are just had identical inner integrated circuit address when dispatching from the factory, master component once will activate more than one subordinate assembly and carry out data transmission, therefore, will cause master component to carry out data transmission with the subordinate assembly on the inter-IC bus.Or say, must use the bus of many groups to separate subordinate assembly, but can cause the increase of cost so again with identical inner integrated circuit address.
In summary, the use inter-IC bus interface of described prior art carries out the electronic system of data transmission, on reality is used, obviously has inconvenience and defective, so be necessary to be improved.
Summary of the invention
At above-mentioned defective, fundamental purpose of the present invention is, a kind of electronic system of using the inter-IC bus interface to come data transmission is provided, and wherein master control set can carry out data transmission with a plurality of slave units with identical inner integrated circuit address.
In addition, another object of the present invention is to, a kind of master control set and a plurality of data transmission method with electronic installation of identical inner integrated circuit address are provided.
The invention provides a kind of electronic system of using inter-IC bus as interface, carry out data transmission, comprising by a master control set and a plurality of slave units with identical inner integrated circuit address:
One inter-IC bus has a data signal line and a time clock signal wire;
One master control set, have one first end, second end and be coupled to the data signal line and the clock pulse signal line of described inter-IC bus respectively, select signal and export an initial signal by the current potential that drags down described data signal line and described clock pulse signal line and carry out data transmission to export one;
A plurality of slave units all have an identical internal integrated circuit address, and described each slave unit all has one first end and one second end, are coupled to the data signal line of described inter-IC bus and a plurality of output terminals of selector switch respectively;
One selector switch, have an input end and a plurality of output terminal, couple the clock pulse signal line of described inter-IC bus and second end of a plurality of slave units respectively,, select one of them and described master control set of a plurality of slave units to carry out data transmission with after receiving described selection signal.
The present invention also provides a kind of data transmission method that uses inter-IC bus as interface, described inter-IC bus is connected between a master control set and a plurality of slave unit with identical inner integrated circuit address, reportedly defeated to count according to the control of master control set, this data transmission method comprises:
Drag down the current potential of the data signal line of described inter-IC bus; Dragging down the current potential of the clock pulse signal line of described inter-IC bus, is the initial of described data transmission as an initial signal; And
Signal to one selector switch is selected in output one, carries out the action of this data transmission with this slave unit of selecting one of them.
Brief Description Of Drawings
Below in conjunction with accompanying drawing,, will make technical scheme of the present invention and other beneficial effects apparent by detailed description to preferred embodiment of the present invention.
In the accompanying drawing,
Fig. 1 is the existing electronic system of using the inter-IC bus interface to carry out data transmission;
Fig. 2 is the synoptic diagram of electronic system of the present invention;
Fig. 3 is the synoptic diagram of selector switch of the present invention;
Fig. 4 is another synoptic diagram of the selector switch among the present invention.
Embodiment
Hereinafter, will describe the present invention in detail.
Please refer to shown in Figure 2ly, the invention provides a kind of electronic system of utilizing master control set to carry out data transmission by inter-IC bus interface and a plurality of slave units with identical inner integrated circuit address.
In electronic system of the present invention, a plurality of slave unit 20-1～20-4 are coupled to inter-IC bus 10, and a plurality of slave unit 20-1～20-4 all has identical internal integrated circuit address, for example a 1111000h.In addition, inter-IC bus 10 is made up of a data signal line SDA and a time clock signal wire SCL.Master control set 30 is coupled to inter-IC bus 10, in order to receive and to send data.One selector switch 40, be couple to inter-IC bus 10 and master control set 30, this selector switch 40 has a plurality of output terminal SCL1～SCL4 and is coupled to a plurality of slave unit 20-1～20-4 respectively, to select any of a plurality of slave unit 20-1～20-4, cooperate master control set 30 to carry out data transmission.
Wherein, when master control set 30 carried out data transmission, master control set 30 can reach a selection signal SS to selector switch 40 by output one initial signal on inter-IC bus 10.Therefore, selector switch 40 can be selected signal SS according to this, selects any in a plurality of slave unit 20-1～20-4, receives start signal and carries out data transmission with master control set 30.
Please refer to Fig. 2 and Fig. 3, selector switch 40 by one separate multiplexer 401 and a plurality of or the door an OR1～OR4 constituted, separate multiplexer 401 and have a plurality of input end AI0, AI1, couple the selection signal SS that master control set 30 is exported, and a plurality of output terminals A O0～AO3 is coupled to first input ends a plurality of or door OR1～OR4 respectively.And second input ends a plurality of or door OR1～OR4 are coupled to the clock pulse signal line SCL of inter-IC bus 10.And output terminal SCL1～SCL4 a plurality of or door OR1～OR4 are coupled to a plurality of slave unit 20-1～20-4.
In preferred embodiment of the present invention, because the control end D ground connection of separating multiplexer 401, therefore, separate multiplexer 401 bases from the selected output terminal that arrives of the selection signal SS of master control set 30, for example AO0 can remain on electronegative potential, and the output terminal that is not chosen to, for example AO1～AO3 then can remain on noble potential.Also because so, or the output terminal of door OR2～OR4 can remain on noble potential always, has only or the current potential of the output terminal SCL1 of door OR1 can change along with the clock pulse signal line SCL of inter-IC bus 10.As shown in Figure 3, separating multiplexer 401, can to use sequence number be that a TTL logic lock (Transistor-Transistor Logic transistor-transistor logic) of 74139 is realized, and a plurality of or door OR1～OR4 can to use sequence number be that a TTL logic lock of 7432 is realized.
Because initial state, be by master control set 30 when clock pulse signal line SCL is noble potential, data signal line SDA by noble potential step-down current potential, is become clock pulse signal line SCL into electronegative potential again and produces after a bit of time.And have only one along with clock pulse signal line SCL changes among output terminal SCL1～SCL4 of a plurality of or door OR1～OR4, remaining output terminal can remain on noble potential always, has only a slave unit can receive the initial state that master control set 30 is produced.Therefore, when master control set 30 will carry out data transmission, selector switch 40 is according to the selection signal from master control set 30, cause and have only a meeting to receive master control set 30 among a plurality of slave unit 20-1～20-4 to be output in initial state on the inter-IC bus 10, and carry out data transmission with master control set 30.
That is to say among the output terminal SCL1～SCL4 of a plurality of or door, to have only a current potential might be dragged down constituting initial state, thereby a slave unit that only receives initial state can activate.The slave unit that is activated can be accepted the address of itself, as 1111000h.After the initial state, the next clock period of beginning, master control set 30 can transmit an address signal (1111000h), confirms that the position signal is on data signal line SDA so the slave unit that is activated can send one, it has been ready to receive data to inform master control set 30, and pending data such as begins.Then master control set 30 just begins transmission of data signals.
The present invention also provides a kind of data transmission method that uses inter-IC bus as interface, be applicable to a master control set and a plurality of slave unit with identical inner integrated circuit address, wherein master control set 30, have one first end, second end and be coupled to the data signal line SDA and the clock pulse signal line SCL of an inter-IC bus 10 respectively, and each slave unit 20-1～20-4 all has one first end and one second end, and wherein each first end is coupled to the data signal line SDA of inter-IC bus 10.
Data transmission method of the present invention, comprise at first, one selector switch 40 is provided, has second end that a plurality of output terminal SCL1～SCL4 are coupled to a plurality of slave unit 20-1～20-4 respectively, an input end is coupled to the clock pulse signal line SCL of inter-IC bus 10.
Then, when master control set 30 will carry out data transmission, master control set 30 can output one be selected the control end (AI0, AI1) of signal SS to selector switch 40, and an initial signal is to inter-IC bus 10.
At last, selector switch 40 is according to described selection signal SS and start signal, select in a plurality of slave unit 20-1～20-4 one, carries out data transmission with master control set 30.Because selector switch 40 can be with among a plurality of slave unit 20-1～20-4, the current potential on second end of three slave units that are not chosen to remains on noble potential.So have only the current potential on second end of the slave unit of being chosen, can change along with the clock pulse signal line SCL of inter-IC bus 10, therefore, drag down the current potential of data signal line SDA earlier when master control set 30, then drag down the current potential of clock pulse signal line SCL again, with as the start signal that exports on the inter-IC bus 10, a plurality of slave unit 20-1～20-4 have only a meeting to receive an initial signal, and then carry out data transmission with master control set 30.
Therefore, in electronic system provided by the present invention, master control set can pass through an inter-IC bus interface, carries out data transmission with a plurality of slave units with identical inner integrated circuit address.And need not as prior art, need to use a plurality of inter-IC bus to separate a plurality of slave units, so the cost of system also can reduce with identical inner integrated circuit address.
Be understandable that; for the person of ordinary skill of the art; can make other various corresponding changes and distortion according to technical scheme of the present invention and technical conceive, and all these changes and distortion all should belong to the protection domain of accompanying Claim of the present invention.
Claims (5)
1, a kind of electronic system of using inter-IC bus as interface is characterized in that, carries out data transmission by a master control set and a plurality of slave units with identical inner integrated circuit address, comprising:
One inter-IC bus has a data signal line and a time clock signal wire;
One master control set, have one first end, second end and be coupled to the data signal line and the clock pulse signal line of described inter-IC bus respectively, select signal and export an initial signal by the current potential that drags down described data signal line and described clock pulse signal line and carry out data transmission to export one;
A plurality of slave units all have an identical internal integrated circuit address, and described each slave unit all has one first end and one second end, are coupled to the data signal line of described inter-IC bus and a plurality of output terminals of selector switch respectively;
One selector switch, have an input end and a plurality of output terminal, couple the clock pulse signal line of described inter-IC bus and second end of a plurality of slave units respectively,, select one of them and described master control set of a plurality of slave units to carry out data transmission with after receiving described selection signal.
2, the electronic system of using inter-IC bus as interface according to claim 1 is characterized in that described selector switch comprises:
One separates multiplexer, and have a plurality of input ends and couple described selection signal, and a plurality of output terminal; And
A plurality of or the door, all have a first input end and be coupled to one of described a plurality of output terminals of separating multiplexer person, one second input end is coupled to the clock pulse signal line of described inter-IC bus, and an output terminal one of is coupled in described a plurality of slave unit person's second end.
3, the electronic system of using inter-IC bus as interface according to claim 2 is characterized in that, the described multiplexer of separating is realized by a transistor-transistor logic lock.
4, the electronic system of using inter-IC bus as interface according to claim 2 is characterized in that, described a plurality of or the door realize by a transistor-transistor logic lock.
5, a kind of data transmission method that uses inter-IC bus as interface, it is characterized in that, described inter-IC bus is connected between a master control set and a plurality of slave unit with identical inner integrated circuit address, carry out data transmission with control according to master control set, this data transmission method comprises:
Drag down the current potential of the data signal line of described inter-IC bus; Dragging down the current potential of the clock pulse signal line of described inter-IC bus, is the initial of described data transmission as an initial signal; And
Signal to one selector switch is selected in output one, carries out the action of this data transmission with this slave unit of selecting one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03107781 CN1267828C (en) | 2003-04-01 | 2003-04-01 | Electron system using bus between integrated circuits as interface and its data transmission method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03107781 CN1267828C (en) | 2003-04-01 | 2003-04-01 | Electron system using bus between integrated circuits as interface and its data transmission method |
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| CN1534500A CN1534500A (en) | 2004-10-06 |
| CN1267828C true CN1267828C (en) | 2006-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 03107781 Expired - Fee Related CN1267828C (en) | 2003-04-01 | 2003-04-01 | Electron system using bus between integrated circuits as interface and its data transmission method |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100363918C (en) * | 2004-12-04 | 2008-01-23 | 鸿富锦精密工业（深圳）有限公司 | System and method for dynamically distributing I2C address |
| CN100383771C (en) * | 2004-12-04 | 2008-04-23 | 鸿富锦精密工业（深圳）有限公司 | System and method for dynamically distributing device address on integrated circuit bus |
| CN100389412C (en) * | 2004-12-04 | 2008-05-21 | 鸿富锦精密工业（深圳）有限公司 | Method for automatically identifying multiple serial device positions |
| KR100772389B1 (en) * | 2006-01-12 | 2007-11-01 | 삼성전자주식회사 | Apparatus for cognizing memory |
| FR3036513B1 (en) | 2015-05-19 | 2018-06-08 | Stmicroelectronics (Rousset) Sas | COMMUNICATION METHOD ON A BIFILAR BUS |
| CN106248522B (en) * | 2016-07-19 | 2019-06-07 | 西安思坦环境科技有限公司 | A kind of laboratory investment method about soil moisture content sensor |
| CN114756500A (en) * | 2021-07-28 | 2022-07-15 | 义明科技股份有限公司 | Master-slave system and sub-integrated circuit thereof |
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Assignee: HAOYANG TIANYU TECHNOLOGY (SHENZHEN) CO., LTD. Assignor: Accton Technology Corporation Contract fulfillment period: 2009.1.1 to 2013.12.31 Contract record no.: 2009990000290 Denomination of invention: Electron system using bus between integrated circuits as interface and its data transmission method Granted publication date: 20060802 License type: Exclusive license Record date: 20090410 |
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Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.1.1 TO 2013.12.31; CHANGE OF CONTRACT Name of requester: HAO YANG TIN YU TECHNOLOGY (SHENZHEN) CO., LTD. Effective date: 20090410 |
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Granted publication date: 20060802 Termination date: 20190401 |
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