CN106547713B - Address allocation method and device - Google Patents
Address allocation method and device Download PDFInfo
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- CN106547713B CN106547713B CN201510601035.5A CN201510601035A CN106547713B CN 106547713 B CN106547713 B CN 106547713B CN 201510601035 A CN201510601035 A CN 201510601035A CN 106547713 B CN106547713 B CN 106547713B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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Abstract
The invention provides a method and a device for allocating addresses, relates to the field of communication, and can save address pin resources on a PHY chip. The method comprises the following steps: the controller allocates a chip management address to the PHY chip; the controller sends a first signal to the PHY chip, wherein the first signal is an operation signal for controlling writing; the controller writes the chip management address into an address configuration register of the PHY chip within an effective time of the first signal. The invention is used for managing address allocation.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method and an apparatus for allocating addresses.
Background
With the rapid development of hardware and network technology, the compactness and density of system boards are higher and higher, and devices already have 48 or more physical ports. These physical ports are derived from several physical layer (PHY) chips, for example, an 8-port PHY chip provides 8 physical ports and a 4-port PHY chip provides 4 physical ports. Each physical port led out by the PHY chip corresponds to a port management address so as to be distinguished from other physical ports.
Generally, if a device controls a PHY chip through a Serial Management Interface (SMI) bus controller, a frame format of communication between the SMI bus controller and the PHY chip is fixed, and the PHY chip is distinguished by a 5-bit address. Under the condition, 1-5 pins are generally reserved in the PHY chip and are used as address pins when the chip is designed. After power-on, the pull-up (representing "1") and pull-down (representing "0") designs of the level of the address pin on the PHY chip automatically form 1-5 bit addresses, which are used as chip management addresses of the PHY chip and used for managing physical ports under the PHY chip. . If the address pins reserved by the chip are less than 5, namely the address is less than 5 bits, 0 is supplemented to the high bits of the address to form a 5-bit address.
However, generating the chip management address of the PHY chip in the above manner may consume valuable pin resources on the PHY chip.
Disclosure of Invention
The embodiment of the invention provides a method and a device for allocating addresses, which can save pin resources on a PHY chip.
In a first aspect, a method for allocating an address is provided, where the method is used in an apparatus including a controller and a PHY chip, the controller is connected to the PHY chip through a bus, and the method includes:
the controller allocates a chip management address to the PHY chip;
the controller sends a first signal to the PHY chip, wherein the first signal is an operation signal for controlling writing;
the controller writes the chip management address into an address configuration register of the PHY chip within an effective time of the first signal.
With reference to the first aspect, in a first possible implementation manner, the chip includes a flag register therein,
the controller transmitting the chip management address to the chip includes: when the controller is able to read the value of the flag register, the controller transmits the chip management address to the chip.
With reference to the first aspect, in a second possible implementation manner, the apparatus includes a plurality of PHY chips,
the controller allocating a chip management address to the PHY chip includes: the controller assigns a unique chip management address to each PHY chip in the device;
the controller transmitting a first signal to the PHY chip includes: the controller sequentially transmits a first signal to each of the PHY chips in the apparatus.
With reference to the first aspect, in a third possible implementation manner, after the controller writes the chip management address into an address configuration register of the PHY chip, the method further includes:
and the PHY chip generates a unique port management address for each physical port under the PHY chip according to the chip management address so as to manage the corresponding physical port.
With reference to the first aspect or the second possible implementation manner of the first aspect, in a fourth possible implementation manner, the first signal is a reset signal,
the controller writing the chip management address into an address configuration register of the first PHY chip during the active time of the first signal comprises:
the controller writes the chip management address into an address configuration register of the chip within an active time of the reset signal.
In a second aspect, an apparatus for allocating an address is provided, which includes a controller and a PHY chip, the controller and the PHY chip are connected via a bus, the PHY chip includes an address configuration register,
the controller is configured to generate a chip management address for the PHY chip and send a first signal to the PHY chip, where the first signal is an operation signal for controlling writing; writing the chip management address into an address configuration register of the chip within an active time of the first signal.
With reference to the second aspect, in a first possible implementation manner, a flag register is included in the chip,
the controller is configured to transmit the chip management address to the chip when the controller is capable of reading the value of the flag register.
With reference to the second aspect, in a second possible implementation manner, the apparatus includes a plurality of PHY chips,
the controller is specifically configured to: assigning a unique chip management address to each of the PHY chips in the apparatus; transmitting a first signal to each of the PHY chips in the apparatus in sequence.
With reference to the second aspect, in a third possible implementation manner, the apparatus for allocating an address further includes a plurality of physical ports, the chip is coupled to the physical ports,
after the controller writes the chip management address into an address configuration register of the PHY chip, the PHY chip to:
and generating a unique port management address for each physical port under the PHY chip according to the chip management address so as to manage the corresponding physical port.
With reference to the second aspect or the second possible implementation manner of the second aspect, in a fourth possible implementation manner, the first signal is a reset signal,
the controller is specifically configured to:
and writing the chip management address into an address configuration register of the chip within the effective time of the reset signal.
According to the method and the device for allocating the address, the controller allocates the chip management address, and the allocated chip management address is directly written into the chip, so that the chip management address can be delivered from the controller to the chip instead of the traditional mode of pulling up and down the address pin, and the pin of the chip can not be used in the process, so that precious chip pin resources are saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of a method of address assignment provided by an embodiment of the present invention;
FIG. 2 is a flow chart of another method for address assignment according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an apparatus for allocating addresses according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an apparatus for allocating an address according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
According to the method and the device for allocating the address, provided by the embodiment of the invention, the address can be defined in a software mode instead of a hardware address line, so that pin resources on a PHY chip can be saved. Meanwhile, when a plurality of PHY chips exist in the device, a controller in the device allocates unique chip management addresses for the plurality of PHY chips and writes the unique chip management addresses into an address configuration register, so that address conflicts among the PHY chips and address conflicts among physical ports of different PHY chips can be avoided on the basis of not additionally increasing the controller.
The apparatus in embodiments of the present disclosure may include a controller and one or more PHY chips. And when applied to managing physical ports, the device further includes a plurality of physical ports. The controller and the PHY chip are connected by a bus, the PHY chip may be coupled to the physical port, the PHY chip includes an address configuration register, and the PHY chip has a plurality of pins, one of which may be connected to a write control signal line to transmit an operation signal for controlling writing, where the operation signal for controlling writing is a first signal. This pin connected to the write control signal line may be a pin already used on the PHY chip or may be a pin reserved (not used) on the PHY chip. In the embodiment of the present invention, it is only necessary to ensure that the write control signal line with the pin connected thereto can transmit the first signal, and the specific type of the write control signal line is not limited in the present invention. For example, the write control signal line may be a reset signal line, or may be other configuration lines, such as an interrupt line, or the like, and of course, in the case where the PHY chip uses a reserved pin, it may also be a signal line that is separately set up on the PHY chip and is dedicated to transmitting the first signal.
By adopting the technical scheme provided by the invention, the chip management address is defined without using a mode of pulling up and down address pins, thereby saving precious pin resources on a PHY chip, and the advantage is obvious through the following description. Of course, even if the address pins for defining the chip management address are reserved, the technical solution provided by the embodiment of the present invention can also achieve the effect of avoiding the conflict of the port management address without adding an additional bus controller.
The controller in the embodiment of the present invention may be an SMI bus controller, and accordingly, the controller is connected to each PHY chip through an SMI bus; of course, the controller may also be another controller suitable for implementing the present invention, and the controller is connected to each PHY chip through a corresponding bus, which is not limited in the present invention. The other controller may be, for example, a Serial Management Bus (SMB) controller, in which case the SMB controller connects the PHY chips via an SMB Bus. The controller mentioned in the embodiments of the present invention may be integrated into a Central Processing Unit (CPU), or may be used as an independent controller, which is not limited in the present invention.
The chip management address in the embodiment of the invention is used for uniquely identifying the PHY chip, and the port management address is used for uniquely identifying the physical port so as to facilitate the PHY chip to identify and manage each physical port.
Fig. 1 is a method for allocating an address according to an embodiment of the present invention. The method is applicable to a device comprising a controller and a PHY chip controlled by the controller, wherein the controller is connected with the PHY chip through a bus. Referring to fig. 1, an embodiment of the present invention provides a method for allocating an address, where the method may include:
11. and the controller allocates a chip management address for the PHY chip.
In this embodiment of the present invention, the chip management address may be an address for managing a physical port under the PHY chip. The chip management address is used to uniquely identify the PHY chip.
Wherein, in a case that the chip management address is used for managing a physical port under the PHY chip, the controller may allocate a chip management address to each PHY chip on the device in the following manner:
the controller may obtain (e.g., by reading firmware on the apparatus) the number of all physical ports set on the apparatus and the number of physical ports led out by each PHY chip on the apparatus when the apparatus is powered on, and generate a unique chip management address for each PHY chip on the apparatus by using the number of all physical ports on the apparatus and the number of physical ports led out by each PHY chip on the apparatus.
12. The controller transmits a first signal to the PHY chip, where the first signal is an operation signal for controlling writing.
13. The controller writes the chip management address into an address configuration register of the PHY chip within an effective time of the first signal.
In the embodiment of the present invention, in order to ensure that the writing time is long enough, the effective time of the first signal, that is, the time for the operation signal for controlling writing to work, for example, 5ms, may be set. The valid time of the first signal may be set according to a PHY chip, a controller, a bus connected between the controller and the PHY chip, and the like, which are not limited in the present invention.
The first signal may be a reset signal, so that the writing of the port management address can be controlled by using the existing reset signal, and the compatibility with the existing PHY chip design operation flow is facilitated.
When the write signal is a reset signal, the writing, by the controller, the chip management address into the first address configuration register in the valid time of the first signal in step 13 may include:
and the PHY chip writes the chip management address into an address configuration register of the PHY chip within the time when the reset signal is effective. The address configuration register is used for recording a chip management address written by the first signal. The address configuration register is readable and writable, but is only writable when the first signal is active and is read only for the remainder of the time. This prevents random tampering with the address configuration registers. In addition, the address configuration register is only triggered to reset and restore by the power-on signal, so that the address configuration register is not triggered to reset and restore by the first signal even if the first signal is the reset signal.
In the case that the chip management address is used for managing a physical port under the PHY chip, after step 13, the method for allocating an address according to the embodiment of the present invention may further include:
and the PHY chip generates a unique port management address for each physical port under the PHY chip according to the chip management address, and manages the corresponding physical port under the PHY chip by using the port management address. The port management address is used for uniquely identifying the physical port so as to facilitate the PHY chip to identify and manage each physical port.
When the method for allocating the address provided by the invention is applied to the management of the physical port, once the chip management address is determined, the port management address of each physical port led out under the PHY chip can be determined. That is, the port management address of the physical port is formed based on the chip management address. For example, the port management address of each physical port under the PHY chip may be obtained by sequentially adding 1 to the chip management address, where the chip management address may be used as the port management address of the first physical port under the PHY chip.
Optionally, after step 13, the method may further comprise:
and when receiving a reading request for the address configuration register, the PHY chip reads a chip management address in the address configuration register. In this way, the chip management address stored in the address configuration register can be subsequently used to manage and configure the physical port, for example, setting the transmission rate of the physical port, for example, setting the physical port a as a physical port supporting hundreds of megabits of rate transmission, setting the physical port B as a physical port supporting gigas of rate transmission, and setting the physical port C as a physical port supporting tens of megabits of rate transmission.
In the embodiment of the invention, the port management address of the physical port led out by the PHY chip can be defined in a software mode, the controller is used for allocating the chip management address, and the allocated chip management address is directly written into the PHY chip, so that the delivery of the chip management address from the controller to the PHY chip is realized in a software mode, and the delivery of the chip management address from the PHY chip to the controller is realized in a non-traditional mode of pulling up and down address pins, so that the pins of the PHY chip can be bypassed (not used), and the precious pin resources of the PHY chip are saved.
Optionally, in an embodiment of the present invention, the apparatus includes a plurality of PHY chips, where the allocating, by the controller in step 12, a chip management address to the PHY chip includes: the controller assigns a unique chip management address to each of the PHY chips. Accordingly, the controller transmitting the first signal to the PHY chip in step 13 may include: the controller sequentially transmits a first signal to each of the PHY chips.
When a plurality of PHY chips exist in the device, only the PHY chip controlled by the first signal can configure the address, and the rest PHY chips are not influenced. No matter the device comprises a plurality of PHY chips, the addresses can be respectively configured for the PHY chips in the device by controlling the PHY chips one by one through the first signal.
The number of physical ports led out by one PHY chip is limited, and a plurality of PHY chips are often used when a device needs a large number of physical ports. If one controller is used to control a plurality of PHY chips simultaneously, and a hardware address line (address pin) is pulled up and down, address conflicts may occur between the plurality of PHY chips due to the limited number of hardware address lines (address pins). It is common to add a controller to control each PHY chip individually to solve the problem of port management address collision, but adding a controller will increase the cost greatly. In the embodiment of the invention, because the chip management addresses generated by the controller have uniqueness, the port management addresses of all the physical ports on the device also have uniqueness, thereby avoiding the collision of the chip management addresses of the PHY chip on the basis of not adding an additional bus controller, and because the port management addresses among the physical ports are generated on the basis of the chip management addresses, the collision of the port management addresses among the physical ports can be further avoided under the condition that the chip management addresses do not collide. Therefore, the technical scheme provided by the embodiment of the invention not only can save precious PHY chip pin resources, but also can avoid address conflict on the basis of not additionally increasing a controller when a plurality of PHY chips are used.
In the embodiment of the present invention, the first signal may be a reset signal, and may also be another signal suitable for controlling writing, for example, an interrupt signal, so that a dedicated signal is not required to be set, which may save pins of the PHY chip and improve the resource utilization rate of the PHY chip. Of course, the first signal may also be a customized signal, and the first signal may be transmitted through an additional signal line.
In order to be compatible with the existing PHY chip, when the PHY chip can not adopt the method of the invention to allocate the address, the original method can be still adopted to allocate the address so as to avoid address conflict. In this embodiment of the present invention, the identification may be performed through a PHY chip flag register, and whether the mode of allocating the port management address provided in this embodiment of the present invention is supported is determined by reading a value of the PHY chip flag register.
Specifically, in one embodiment of the present invention, a flag register may be included in the PHY chip, and the flag register may be readable and used to distinguish the type of the PHY chip, i.e., determine whether the PHY chip supports the new PHY chip of the present invention or the legacy PHY chip of the present invention. The flag register can be set to a fixed value by a manufacturer according to the self requirement when the PHY chip leaves a factory. Once the controller is able to read this fixed value of the flag register, it indicates that this PHY chip is a new PHY chip supporting the present invention. At this time, the controller transmitting the PHY chip management address to the PHY chip in step 11 may include: when the controller is able to read the value of the flag register, the controller transmits the chip management address to the PHY chip.
Of course, when the controller cannot read the value of the flag register or a read error occurs, the PHY chip that allocates the port management address in a manner of pulling up and down the address pin may be used.
As can be seen from the above, the embodiment of the present invention identifies the type of the PHY chip by setting the identification register, and can ensure that the PHY chip can still adopt the conventional method to allocate addresses when the PHY chip does not support the method for allocating addresses of the present invention.
Fig. 2 is a flowchart of a method for allocating an address according to an embodiment of the present invention. Referring to fig. 2, a method for allocating an address according to an embodiment of the present invention may include:
21. after power-on, if the controller can read the value of the flag register, it is determined that the PHY chip is a PHY chip supporting the address allocation method provided by the embodiment of the present invention, otherwise, it is determined that the PHY chip is an original PHY chip determining a chip management address through a hardware pin.
If the PHY chip is a PHY chip supporting the port management address assignment method provided in the embodiment of the present invention, step 22 is continuously performed, and if not, step 211 is performed.
The identification register can be read only or read and written. Unauthorized malicious tampering can be prevented when the identification register is readable only.
211. The chip management address is determined by conventional hardware pin methods.
22. The controller generates a unique chip management address for each PHY chip on the device.
Specifically, the step may specifically be: the controller acquires the number of all physical ports on the equipment and the number of physical ports led out by each PHY chip on the equipment; the controller generates a unique chip management address for each PHY chip on the equipment by using the number of all physical ports on the equipment and the number of the physical ports led out by each PHY chip on the equipment. The chip management address is used to uniquely identify a PHY chip.
23. After power-on, an address configuration register in the PHY chip is initialized. The address configuration register can be written only under the action of an operation signal for controlling writing and can be read only under the condition of an operation signal not used for controlling writing.
Wherein, steps 22 and 23 have no sequential dependency relationship, and they can be performed simultaneously or sequentially.
24. The controller transmits a first signal to the PHY chip, where the first signal is an operation signal for controlling writing.
In the embodiment of the present invention, the valid time of the first signal may be set for configuring the address of the PHY chip. Assuming that the frequency of the SMI bus is 1MHz, one read/write cycle is typically 64 clock cycles, i.e. 0.064ms, and furthermore, in order to secure a sufficient write time in consideration of a transmission delay, a reception delay, and the like that may occur during the read/write operation, the effective time of the first signal is typically set to 10 to 100 times of 64 clock cycles, for example, the effective time of the first signal may be set to 5 ms.
The first signal may be, for example, a reset signal. When the first signal is valid, the address configuration register of the PHY chip can be written, and after the write signal is invalid, the address configuration register of the PHY chip can not be written and only be read.
25. The controller writes the chip management address into an address configuration register of the PHY chip within a valid time of the first signal.
After the write is complete, the address configuration registers of the PHY chip may become read-only and non-writable.
26. And the PHY chip generates a unique port management address for each physical port under the PHY chip according to the chip management address so as to manage the corresponding physical port.
In the method for allocating addresses provided in the embodiments of the present invention, the controller allocates chip management addresses to all PHY chips on the device in a unified manner, and the PHY chips write the allocated chip management addresses into the address configuration register under the action of the operation signal for controlling the write, so that valuable PHY chip pin resources can be saved.
Moreover, it should be noted that the method for allocating an address provided by the embodiment of the present invention further has the following advantages: the chip management address is flexibly configured by the controller and is not limited by the hardware configuration of hardware any more, so that the problems of limited address space and address conflict are avoided; the pin function of the existing PHY chip is borrowed, additional hardware configuration is not needed, the design of the existing PHY chip can be compatible, and the cost is basically not needed to be consumed.
Fig. 3 is a schematic structural diagram of an apparatus for allocating an address according to an embodiment of the present invention. Referring to fig. 3, an apparatus 300 for allocating an address according to an embodiment of the present invention may include a controller 301 and a PHY chip 302, where the controller 301 and the PHY chip 302 are connected by a bus 303, and the PHY chip 302 includes an address configuration register 304, where:
a controller 301, configured to generate a chip management address for the PHY chip and send a first signal to the PHY chip, where the first signal is an operation signal for controlling writing; writing the chip management address into an address configuration register of the chip within the valid time of the first signal;
the device for allocating the address provided by the embodiment of the invention allocates the chip management address by the controller and directly writes the allocated chip management address into the chip, so that the delivery of the chip management address from the controller to the chip can be realized, the delivery of the chip management address is realized in a non-traditional mode of pulling up and down address pins, and the pins of the chip can not be used in the process, thereby saving precious chip pin resources.
Optionally, in an embodiment of the present invention, a flag register is included in the PHY chip, the flag register being readable and used for distinguishing a type of the PHY chip,
the controller 301 is configured to send the first signal to the PHY chip when the controller is able to read the value of the flag register.
Optionally, in an embodiment, referring to fig. 4, the apparatus 300 for allocating an address includes a plurality of PHY chips 302, and the controller 301 is specifically configured to: assigning a unique chip management address to each PHY chip 302; the first signal is transmitted to each PHY chip 302 in sequence.
Optionally, in another embodiment of the present invention, referring to fig. 4, the apparatus 300 for assigning addresses further comprises a plurality of physical ports 305, the PHY chip 302 is coupled to the physical ports 305, the chip management address is used for managing the physical ports under the first PHY chip,
after the controller 301 writes the chip management address into the address configuration register of the PHY chip, the PHY chip 302 is further configured to:
according to the chip management address, a unique port management address is generated for each physical port 305 under the PHY chip 302 to manage the corresponding physical port 3305.
Optionally, the controller 301 may be specifically configured to:
the controller 301 obtains the number of all physical ports on the address assigning apparatus 300 and the number of physical ports led out by each PHY chip on the address assigning apparatus 300;
the controller 301 generates a unique chip management address for each PHY chip on the address assigning apparatus 300 by using the number of all physical ports on the address assigning apparatus 300 and the number of physical ports led out by each PHY chip on the device.
Optionally, the first signal is a reset signal, and the PHY chip 302 is specifically configured to:
writing the chip management address into an address configuration register of the PHY chip within an active time of the reset signal.
Optionally, the address configuration register 304 is readable, and after the PHY chip 302 writes the chip management address into the address configuration register of the PHY chip within the valid time of the first signal, the PHY chip 302 is further configured to: upon receiving a read request to the address configuration register 304, the chip management address in the address configuration register 304 is read.
Optionally, the controller 301 is an SMI bus controller or an SMB controller.
According to the address allocation device provided by the embodiment of the invention, the controller is used for uniformly allocating the chip management addresses to all PHY chips on the address allocation device, and the PHY chips are used for writing the allocated chip management addresses into the address configuration register under the action of the operation signal for controlling writing.
Moreover, it should be noted that the apparatus for allocating an address provided by the embodiment of the present invention further has the following advantages: the chip management address is flexibly configured by the controller and is not limited by hardware configuration any more, so that the problems of limited address space and address conflict are avoided; compared with the traditional PHY chip, the method saves address pins and saves precious PHY chip pin resources; the pin function of the existing PHY chip is borrowed, additional hardware configuration is not needed, the design of the existing PHY chip can be compatible, and the cost is basically not needed to be consumed.
It should be noted that: the apparatus for allocating an address and the method for allocating an address provided in the above embodiments belong to the same concept, and specific implementation processes thereof are described in the method embodiments in detail and are not described herein again.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the device-like embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention.
Claims (10)
1. A method for allocating an address, used in an apparatus including a controller and a plurality of physical layer PHY chips, wherein the controller is connected to the plurality of PHY chips through buses, respectively, the method comprising:
the controller allocates a chip management address to each PHY chip in the plurality of PHY chips, wherein each chip management address is used for uniquely identifying a corresponding PHY chip;
the controller respectively sends first signals to the plurality of PHY chips, wherein the first signals are operation signals for controlling writing;
the controller writes the chip management addresses into address configuration registers of the plurality of PHY chips respectively within the effective time of the first signal.
2. The method of claim 1, wherein a flag register is included in the PHY chip,
the controller respectively transmitting the first signals to the plurality of PHY chips includes: when the controller is able to read out the value of the flag register, the controller transmits first signals to the plurality of PHY chips, respectively.
3. The method of claim 1, wherein the controller transmitting first signals to the plurality of PHY chips, respectively, comprises: the controller sequentially transmits a first signal to the each PHY chip in the apparatus.
4. The method of claim 1, wherein after the controller writes the chip management address into an address configuration register of the plurality of PHY chips, the method further comprises:
and each PHY chip generates a unique port management address for each physical port under each PHY chip according to the chip management address so as to manage the corresponding physical port.
5. The method of claim 1 or 3, wherein the first signal is a reset signal,
the controller respectively writing the chip management addresses into address configuration registers of the plurality of PHY chips during an active time of the first signal comprises:
the controller writes the chip management addresses into address configuration registers of the plurality of PHY chips respectively during an active time of the reset signal.
6. An address allocation device is characterized by comprising a controller and a plurality of physical layer (PHY) chips, wherein the controller is respectively connected with the plurality of PHY chips through buses, each PHY chip comprises an address configuration register,
the controller is configured to allocate a chip management address to each PHY chip of the plurality of PHY chips, where each chip management address is used to uniquely identify a corresponding PHY chip; and respectively writing the chip management address into the address configuration register of each PHY chip in the effective time of the first signal.
7. The apparatus of claim 6, wherein each PHY chip includes a flag register therein, the flag register being readable and configured to distinguish a type of each PHY chip,
the controller is configured to send a first signal to the plurality of PHY chips, respectively, when the controller is capable of reading the value of the flag register.
8. The apparatus of claim 6, wherein the controller is specifically configured to: transmitting a first signal to the each PHY chip in the apparatus in sequence.
9. The apparatus of claim 6, wherein the means for assigning addresses further comprises a plurality of physical ports, each PHY chip coupled to each physical port,
after the controller writes the chip management addresses into the address configuration registers of the plurality of PHY chips, respectively, each PHY chip is configured to:
and generating a unique port management address for each physical port under the PHY chip according to the chip management address so as to manage the corresponding physical port.
10. The apparatus of claim 6 or 8, wherein the first signal is a reset signal,
the controller is specifically configured to:
writing the chip management addresses into address configuration registers of the plurality of PHY chips respectively within the valid time of the reset signal.
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