CN1705103A - 具胶材填充导体基板的集成电路封装产品 - Google Patents

具胶材填充导体基板的集成电路封装产品 Download PDF

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CN1705103A
CN1705103A CNA2004100383946A CN200410038394A CN1705103A CN 1705103 A CN1705103 A CN 1705103A CN A2004100383946 A CNA2004100383946 A CN A2004100383946A CN 200410038394 A CN200410038394 A CN 200410038394A CN 1705103 A CN1705103 A CN 1705103A
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conductor
glue material
substrate
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integrated circuit
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黄禄珍
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XIANGHU CO Ltd
Mutual Tek Industries Co Ltd
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XIANGHU CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

一种具胶材填充导体基板的集成电路封装产品。为提供一种降低制造成本、提高生产速度及良品率的集成电路封装产品，提出本发明，它由胶材填充导体基板、设置于胶材填充导体基板上的半导体元件、电性连接半导体元件的导线及封装用填充胶材构成；胶材填充导体基板由导体及填充于导体四周借以支撑导体的胶材构成；导体为铜导线、金属导体或凸块，并于导体表面镀设借以保护导体及与焊线电性连接的保护金属层。

Description

具胶材填充导体基板的集成电路封装产品
技术领域
本发明属于集成电路封装产品，特别是一种具胶材填充导体基板的集成电路封装产品。
背景技术
如图1所示，在一般引线框架或导线接脚的集成电路封装产品上，引线框架70或导线71都是连续金属线及上、下镂空的结构。在金属导线上都必须相互连接以作为支撑，这是由导线或引线框架70的制程上所产生的结构。这种连续性的金属导线支架结构，在集成电路(IC)封装之后段制程中，必须有所谓的切脚(TRIM)及弯脚(FORM)的制程，测试也必须是在切脚、弯脚之后，以避免导线连续所造成的困扰，在量产的效率上变的很差，高效率平面无脚封装QFN(Quad Flat Non-Leaded)产品具有越来越多的趋势，但是也有上述问题。
而连续接脚的导线或是引线框架在封装产品应用上亦会因为下列的原因而造成许多的不便：
高效率平面无脚封装QFN(Quad Flat Non-leaded)封装在封胶时，其引线框架底面必须底层贴胶，此贴胶步骤可能会造成封胶材质流至镂空引线框架的底面而污染底部接脚；或在引线框架底部设置密封基板当作灌胶底垫，封胶完成再去除。但是无论任何方式，在生产上都造成成本增加，良率降低。在切割步骤时，由于金属引线框架的连接特性，所以在以刀具切割时，很可能造成切割刀具的耗损增加成本。且测试也必须要等到切割之后才可进行，无法大量一次测试。
发明内容
本发明的目的是提供一种降低制造成本、提高生产速度及良品率的具胶材填充导体基板的集成电路封装产品。
本发明由胶材填充导体基板、设置于胶材填充导体基板上的半导体元件、电性连接半导体元件的导线及封装用填充胶材构成；胶材填充导体基板由导体及填充于导体四周借以支撑导体的胶材构成；导体为铜导线、金属导体或凸块，并于导体表面镀设借以保护导体及与焊线电性连接的保护金属层。
其中：
保护金属层为金银、镍或银、镍、钴的合金。
填充胶材为介电材料，其可为环氧树脂、聚醯亚氨或复合高分子的胶材。
半导体元件为晶片。
为晶片的半导体元件借由锡球与胶材填充导体基板上为铜导线、金属导体或凸块的导体结合。
为晶片的半导体元件借由凸块与胶材填充导体基板上为铜导线、金属导体或凸块的导体结合。
为晶片的半导体元件借由与胶材填充导体基板导体结合的凸块为金、铜、镍或其合金。
半导体元件与胶材填充导体基板上为铜导线、金属导体或凸块的导体之间利用热压或超音波固结。
由于本发明由胶材填充导体基板、设置于胶材填充导体基板上的半导体元件、电性连接半导体元件的导线及封装用填充胶材构成；胶材填充导体基板由导体及填充于导体四周借以支撑导体的胶材构成；导体为铜导线、金属导体或凸块，并于导体表面镀设借以保护导体及与焊线电性连接的保护金属层。本发明封胶时亦具有相当大的好处，其胶材填充导体基板的填充胶同时具有封胶及密封的功能，而且没有贴合及去除底胶的问题；切割时，由于各集成电路封装产品之间并不存在任何的导线，因为导线已被填充胶支撑，所以用于切割的刀具并不会因此而遭致耗损而增加成本；同时，亦可在切割的前进行测试，而不会存在金属导线连接的问题；不仅降低制造成本，而且提高生产速度及良品率，从而达到本发明的目的。
附图说明
图1、为习用的半导体引线框架结构示意俯视图。
图2、为本发明胶材填充导体基板结构示意剖视图。
图3、为本发明胶材填充导体基板结构示意剖视图(半蚀刻状态)。
图4、为本发明切片步骤示意图。
图5、为本发明完成固晶、焊线、灌胶并切片的填充胶金属导体基板结构示意剖视图。
图6、为本发明结构示意剖视图。
图7、为本发明在胶材填充导体基板上倒装晶片步骤示意图。
图8、为本发明在胶材填充导体基板倒装晶片后灌胶步骤示意图。
图9、为本发明在胶材填充导体基板上倒装晶片步骤示意图(晶片下方设置凸块)。
图10、为本发明在胶材填充导体基板倒装晶片后灌胶步骤示意图(晶片下方设置凸块)。
具体实施方式
如图1、图2、图3、图4所示，本发明为一种集成电路(IC)封装产品，其由胶材填充导体基板、为晶片的半导体元件及填充胶材20构成。
胶材填充导体基板由实心铜导体、金属导体或凸块10及填充于实心铜导体、金属导体或凸块10四周借以支撑金属导体或凸块10的胶材构成。
金属导体或凸块10的表面及底面之间相互形成电气导通，且在金属导体或凸块10的表面上镀设一层金银、镍或银、镍、钴的合金，或是任何可作为保护表面的金属层11；金属层11亦可为导通材料的合金，借以同时作为保护表面、与焊线12电性连接或表面黏着组装用。
铜导体、金属导体或凸块10可呈片状、块状等不同的形状，亦即是说，铜导体、金属导体或凸块10的形状可依电性及热性作出特殊的设计。
铜导体、金属导体或凸块10的制作方式可利用电镀、蚀刻等不同方式形成。
填充胶材20的功能是①用来支撑铜导体或金属导体或凸块10，②作为介电材料之用，③作为导热基材，④作为灌胶时的止漏密封底材，⑤切割道，⑥表面黏着技术(Surface Mount Technology；SMT)的焊垫罩(Solder Mask)；其可以为环氧树脂(EPOXY)或是聚醯亚氨(Polyimide；PI)或是其它不论是在电性及热传性的高分子适合复合高分子胶材制作，并可以涂布、压合或是网印形成。
具胶材填充导体基板的集成电路(IC)封装产品皆可适用不同封装技术，例如在固晶、焊线封装技术的产品，由于固晶和焊线是直接接合在硬性的铜导体、金属导体或凸块10上，所以强度及结合度会相当好。
如图5所示，本发明具胶材填充导体基板的集成电路(IC)封装产品的结构在封胶时亦具有相当大的好处，尤以在高效率平面无脚封装QFN封装产品为例，封胶时必须底层密封，但封胶完成后，底层必须去除，而且不能污染底层，传统作法为：(1)贴底胶或(2)在不锈钢板上镀金(Au)或镍金合金(Ni/Au)。在灌完胶之后，再将底胶或钢板去除。本发明胶材填充导体基板的填充胶同时具有封胶及密封的功能，而且没有贴合及去除底胶的问题。
如图6所示，本发明在切割时，由于各集成电路封装产品之间并不存在任何的导线，因为导线已被填充胶支撑，所以用于切割的刀具30并不会因此而遭致耗损而增加成本；同时，亦可在切割的前进行测试，而不会存在金属导线连接的问题。
如图7、图8所示，亦可将晶片40组装在铜导体、金属导体或凸块10之上构成倒装晶片结构，晶片40的下方设置借以与镀在铜导体、金属导体或凸块10外部的保护金属层11相互连接的锡球41，晶片40组装在铜导体、金属导体或凸块10上之后，再将填充胶20填充于上述总成的底部，以形成本发明具胶材填充导体基板的集成电路封装产品。
如图9、图10所示，亦可将晶片40组装在铜导体、金属导体或凸块10之上构成倒装晶片结构，晶片40的下方设置借以与镀在铜导体、金属导体或凸块10外部的保护金属层11相互连接的为金、铜、镍或其合金或类似金属的凸块42。
晶片40与铜导体、金属导体或凸块10结合的方式可为热压、超音波或非导聚合物(Non-Conductive Polymer)的方式结合在铜导体、金属导体或凸块10上；凸块42与铜导体、金属导体或凸块10间的结合可为金-金或银以热压形成，或以导电胶压合而成，在晶片40与铜导体、金属导体或凸块10完成结合后，再以底层填充胶(Underfill)填充于晶片40与铜导体、金属导体或凸块10之间形成本发明具胶材填充导体基板的集成电路封装产品。

Claims (8)

1、一种具胶材填充导体基板的集成电路封装产品，它由基板、设置于基板上的半导体元件、电性连接半导体元件的导线及封装用填充胶材构成；其特征在于所述的基板为胶材填充导体基板，其由导体及填充于导体四周借以支撑导体的胶材构成；导体为铜导线、金属导体或凸块，并于导体表面镀设借以保护导体及与焊线电性连接的保护金属层。
2、根据权利要求1所述的具胶材填充导体基板的集成电路封装产品，其特征在于所述的保护金属层为金银、镍或银、镍、钴的合金。
3、根据权利要求1所述的具胶材填充导体基板的集成电路封装产品，其特征在于所述的填充胶材为介电材料，其可为环氧树脂、聚醯亚氨或复合高分子的胶材。
4、根据权利要求1所述的具胶材填充导体基板的集成电路封装产品，其特征在于所述的半导体元件为晶片。
5、根据权利要求4所述的具胶材填充导体基板的集成电路封装产品，其特征在于所述的为晶片的半导体元件借由锡球与胶材填充导体基板上为铜导线、金属导体或凸块的导体结合。
6、根据权利要求4所述的具胶材填充导体基板的集成电路封装产品，其特征在于所述的为晶片的半导体元件借由凸块与胶材填充导体基板上为铜导线、金属导体或凸块的导体结合。
7、根据权利要求6所述的具胶材填充导体基板的集成电路封装产品，其特征在于所述的为晶片的半导体元件借由与胶材填充导体基板导体结合的凸块为金、铜、镍或其合金。
8、根据权利要求1所述的具胶材填充导体基板的集成电路封装产品，其特征在于所述的半导体元件与胶材填充导体基板上为铜导线、金属导体或凸块的导体之间利用热压或超音波固结。
CNA2004100383946A 2004-05-27 2004-05-27 具胶材填充导体基板的集成电路封装产品 Pending CN1705103A (zh)

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CN107801320A (zh) * 2017-09-22 2018-03-13 郑州云海信息技术有限公司 一种组件与印刷电路板之间的封装结构及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107801320A (zh) * 2017-09-22 2018-03-13 郑州云海信息技术有限公司 一种组件与印刷电路板之间的封装结构及其制造方法

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