CN1682446A - 锁相回路 - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
- H03C3/0925—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop applying frequency modulation at the divider in the feedback loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
- H03C3/0933—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop using fractional frequency division in the feedback loop of the phase locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
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Abstract
依据本发明的锁相回路乃具有被预期用以产生控制电压(UVCO)的一可调整充电泵(2)。一电压控制振荡器(4)及一评估单元(14)乃向下地连接于该充电泵(2)。此例中,该评估单元(14;14’)以其可用于使用该电压控制振荡器(4)的控制电压(UVCO)及名义梯度(vco)来产生一修正信号(Iref)及施加该信号至评估输出的方式来设计。后者乃依序连接至该充电泵(2)的输入。
Description
技术领域
本发明系有关例如可被用于行动无线系统中之调频传送器之锁相回路。
背景技术
用于调频之现代行动无线系统之传送器简单实施设计系藉由以下亦被称为∑Δ分式-N锁相回路(PLL)或仅为锁相回路之∑Δ分式-N锁相回路所提供。
如图1所示,锁相回路10系包含一相位/频率侦测器1,一电荷帮浦2,一回路滤波器3,一电压控制振荡器4(简写为VCO)及一分频器5。被施加至锁相回路10之一输入者系为参考频率fref,其相位系藉由该相位/频率侦测器1与产生自被分数值N分割之输出频率fvco之频率fdiv之相位做比较。若需要,该相位/频率侦测器1可产生致动信号并将其供应至电荷帮浦2,一旦藉由滤波器3滤波时,其采用该致动信号为产生被施加至电压控制振荡器4之输入作为调谐电压UVCO之电压U之基础。该电压控制振荡器视调谐电压UVCO而定依序产生输出频率fvco。
预期频率调变系藉由∑Δ调制器6改变频率分数值N来数字实行。数字传输资料D系使用加法器7被与信道文字KW组合且被供应至∑Δ调制器6,其接着使用其来决定其供应至分频器5之分数值N。此例中,信道文字KW制定信道。
当非整合回路滤波器3被使用时,锁相回路10之传输频宽系直接与电压控制振荡器梯度Kvco成正比。封闭控制回路10之转换函数H(jw)系被决定如下:
其中
φvco系为锁相回路输出处之相位,
φref系为锁相回路输入处之相位,
w系为角频率,及
N系为分数值。
锁相回路10之-3dB频宽之截止频率(cut-off frequency)f0系被计算自:
其中
Kp系为相位侦测器梯度
R系为接地之回路电阻
Kvco系为电压控制振荡器梯度
相位侦测器梯度Kp系与电荷帮浦电流Icp成正比。
迄今先前技术尚未揭示可被用来稳固设定所有信道及所有容差之直流电压无负载增益及截止频率。
本发明目的系明确说明可稳固设定所有信道及所有容差之直流电压无负载增益及截止频率之锁相回路。
本发明有利地可补偿电压控制振荡器梯度。
该目的系可藉由具有被明确说明于本说明书之锁相回路来达成。
发明内容
依据本发明之锁相回路系具有预期可产生控制电压之可调电荷帮浦。电压控制振荡器及评估单元系被向下连接该电荷帮浦。此例中,评估单元系以其可被用来使用电压控制振荡器之控制电压及名义梯度产生修正信号及施加该信号至该评估输出之方式来设计。后者依序被连接至电荷帮浦之输入。
本发明有利发展可于附带权利要求所明确说明之特征中被找到。
本发明一有利发展中,评估单元系以其可被用来计算电压控制振荡器之梯度误差之方式来设计。
依据本发明之锁相回路另一有利发展中,可转换控制电压为数字文字之模拟/数字转换器系被向下连接评估单元。
本发明另一实施例中,储存数字文字之寄存器系被连接于评估单元及模拟/数字转换器之间。
表内存可被连接于评估单元及寄存器之间以便使用数字文字及信道文字来确定电压控制振荡器之梯度实际值。
再者,评估单元可具有处理单元以便从电压控制振荡器之梯度实际值计算梯度误差,信道文字及电压控制振荡器之名义梯度。
依据本发明之锁相回路另一实施例中,多个寄存器系被向下连接评估单元来储存多个信道群组之个别梯度误差。
可控制电流源系有利地被向下连接评估单元从梯度误差产生修正信号。
此外,依据本发明之锁相回路可包含被连接于电荷帮浦及电压控制振荡器间之回路滤波器。
本发明例中,反馈路径可再包含一除法器。
最后,本发明另一有利改进中,除法器可具有使用∑Δ调制器来设定之分数值。
附图说明
本发明将使用多个实施例及参考四个图被进一步解释于下文,其中:
图1显示先前技术已知之锁相回路,
图2显示方块图型式之依据本发明之锁相回路第一实施例基本设计,
图3显示作为频率函数之电压控制振荡器梯度轮廓之频率图,及
图4显示方块图型式之依据本发明之锁相回路第二实施例基本设计。
具体实施方式
如用于截止频率及频宽之公式(2)所示,截止频率系等比于
Icp*R*Kvco/N (3)
且亦等比于环增益RV。乘积Icp*R系定义电压控制振荡器4之控制范围,且因受供给电压限制而无法如预期改变。设定锁相回路频宽及直流环增益RV之一可能方法系精确地设定电压控制振荡器梯度Kvco。然而,因为电压控制振荡器梯度Kvco系随处理变动而改变,所以补偿方法必须确保截止频率f0维持固定。乘积Icp*R本质上与技术变动无关,因而固定提供电流Icp被产生自相同电阻类型。
图2显示依据本发明之锁相回路第一实施例之基本设计。参考频率fref系被施加至相位/频率侦测器1之第一输入。已藉由分数值N分割且使用fdiv被标示之输出频率fout系被施加至相位/频率侦测器1之第二输入。若已藉由分数值N分割之频率fdiv之相位不同于参考频率fref之相位,则相位/频率侦测器1可产生控制信号使用电荷帮浦2产生修正输出电压U。如调谐电压UVCO,输出电压U系使用低通滤波器3被滤波及传送至电压控制振荡器4之输入及模拟/数字转换器9之输入。电压控制振荡器4接着产生被匹配该调谐电压UVCO之输出频率fout。模拟/数字转换器9系被用来转换调谐电压UVCO为数字文字dUVCO。输入及模拟/数字转换器9之输出系被连接至缓冲储存数字文字dUVCO之寄存器8。表内存11依序被向下连接寄存器8。数字文字dUVCO及信道文字KW(其同样被传送至表内存11)系被用于使用被储存于表内存11来确认电压控制振荡器4之实际梯度Kvco。电压控制振荡器4之梯度Kvco系与名义梯度
一起被供应至使用其来计算梯度误差εr及储存后者于另一寄存器12之评估单元14。可程电流源13系被用来转换梯度误差εr为参考电流Iref。输入侧一方面被连接至相位/频率侦测器1,另一方面被连接至可程电流源13输出之电荷帮浦2现在系使用源自相位/频率侦测器1及参考电流Iref之致动信号来确认对应输出电压U。如图1之锁相回路10实施例中,分数值N可不需图2明确显示而藉助∑Δ调制器6,加法器7,信道文字KW及数字传输资料D来确认。
图3显示信道频率fchan被绘制于x轴而调谐电压UVCO被绘制于y轴之频率图。参考符号15系被用来标示理想调谐特性,而参考符号16系被用来标示被测量之调谐特性。理想调谐特性15之斜率系对应电压控制振荡器4之梯度
名义值且被计算自:
被测量之调谐特性之斜率系对应电压控制振荡器4之梯度Kvco实际值且被计算自:
图4显示方块图型式之依据本发明之锁相回路第二实施例。此例中,低通滤波器3系藉由电阻器17及电容器18之组合而形成。
如图2所示,评估单元14系被修正评估单元14’所取代。可程电流源13系使用参数ΔS来控制,其系使用以下公式针对各信道频率fchan及信道文字KW来计算:
且被缓冲储存于寄存器数据库12中。
如图4左侧描述之图标,若参考电流源13已9位分辨率操作,则参考电流Iref可假设511个不同值。给定Snom值=255,则参考电流Iref系等于Inom。参考电流ΔI之变化系产生自:
ΔI=Ilsb*ΔS (8)
其中Ilsb系为参考电流Iref之最小可能变化。Ilsb产生自可程电流源13之分辨率精确度。
本发明运作方法将被更详细说明如下。第一操作中,锁相回路系锁住信道文字KW所制定之特定信道。锁相回路之”安顿时间”之后,输入及模拟/数字转换器9系将电压控制振荡器4之调谐电压UVCO转换为被储存于寄存器8中之数字文字dUVCO。此操作接着针对多个频率信道被执行,所以电压控制振荡器4之调谐梯度Kvco可被计算自对应被设定之信道频率fchan之信道文字KW及调谐电压UVCO之振幅离散值dUVCO。因为电压控制振荡器梯度
名义值已之为主要值(见图3),所以被陈述于以上方程序(6)中之相对误差εr可被计算如下:
为了补偿误差εr,可被数字设定之电荷帮浦2之参考电流Iref系以最终误差εr为基础而改变。此例中,分数值N之改变亦必须被考虑及依据信道组来补偿。然而,此可使用包含有关分数值N信息之信道文字KW来实行。所以当被用于分时多任务存取(TDMA)系统,如数字欧洲无线电话(DECT),WDCT或蓝牙时,此补偿操作不必于各槽或时槽之前被实行,此操作可于该装置一但被开启,如重置任务之后被实行。该操作可针对特定信道群组被连续实行。可被数字设定之参考电流Iref之致动位系针对各信道及信道群组被储存于寄存器12中,结果信道文字KW被设计程序之后,对应参考电流值Iref可于一般操作期间被读取自寄存器12。
依据本发明之解系提供补偿锁相回路环增益RV之简单实施:
锁相回路之环增益RV及截止频率系因非线性电压控制振荡器特性及跨越信道之分数因子N之变异而改变。考虑电压控制振荡器调谐特性或梯度Kvco藉由改变电荷帮浦参考电流Iref而被决定,数字化及补偿之方式,系可设定实质固定锁相回路之环增益RV及截止频率。
参考符号表
1 相位/频率侦测器
2 电荷帮浦
3 路滤波器
4 电压控制振荡器
5 分频器
6 ∑Δ调制器
7 加法器
8 寄存器
9 模拟/数字转换器
10 锁相回路
11 表内存
12 寄存器数据库
13 电流源
14 评估单元
14’修正评估单元
15 理想调谐电压
16 被测量之调谐电压
17 电阻器
18 电容器
N 分数值
U 电荷帮浦之输出电压
KW 信道文字
D 数字信号资料
UVCO 调谐电压
d UVCO 数字化调谐电压
fout 输出频率
fref 参考频率
Iref 参考电流
Fchan 信道频率
Claims (11)
1.一种锁相回路,
具有被预期产生控制电压(UVCO)的一可调整充电泵(2),所述可调整充电泵(2)具有一电压控制振荡器(4)及连接于其下游的一评估单元(14;14’),具有一评估输出的该评估单元(14;14’)可被用于使用该电压控制振荡器(4)的该控制电压(UVCO)及名义梯度(
)来产生一修正信号(Iref)及施加该信号至该评估输出且该评估输出乃被连接至该充电泵(2)的一充电泵输入的方式来设计。
2.如权利要求1所述的锁相回路,其中该评估单元(14;14’)以其可被用于计算该电压控制振荡器(4)的梯度误差(εr;ΔS)的方式来设计。
3.如权利要求2所述的锁相回路,其中用于转换该控制电压(UVCO)为数字文字(d UVCO)的模拟/数字转换器(9)乃向上地连接该评估单元。
4.如权利要求3所述的锁相回路,其中用于储存该数字文字(dUVCO)的寄存器(8)乃连接于该评估单元(14;14’)及该模拟/数字转换器(9)间。
5.如权利要求4所述的锁相回路,其中表内存(11)被连接于该评估单元(14;14’)及该寄存器(8)间,以便使用该数字文字(d UVCO)及信道文字(KW)来确认该电压控制振荡器(4)的该梯度(K vco)实际值。
7.如权利要求1至6之一所述的锁相回路,其中多个寄存器(12)乃向下连接该评估单元(14’)来储存多个信道群组的个别梯度误差(ΔSf)。
8.如权利要求第1至7之一所述的锁相回路,其中可控制电流源(13)乃向下连接该评估单元(14’)以便从该梯度误差(ΔSf)产生该修正信号(Iref)。
9.如权利要求1至8之一所述的锁相回路,其具有被连接于该充电泵(2)及该电压控制振荡器(4)间的一回路滤波器(3)。
10.如权利要求1至9之一所述的锁相回路,其具有包含一除法器(5)的一反馈路径。
11.如权利要求10所述的锁相回路,其中该除法器(5)具有可被设定之一分数值(N),该锁相回路具有可用来设定该分数值(N)的一∑Δ调制器(6)。
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DE10242364.4 | 2002-09-12 | ||
DE10242364A DE10242364A1 (de) | 2002-09-12 | 2002-09-12 | Phasenregelkreis |
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CN03821801.1A Pending CN1682446A (zh) | 2002-09-12 | 2003-08-11 | 锁相回路 |
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US (1) | US7106141B2 (zh) |
EP (1) | EP1543621B1 (zh) |
CN (1) | CN1682446A (zh) |
DE (2) | DE10242364A1 (zh) |
WO (1) | WO2004027997A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101640537B (zh) * | 2008-07-31 | 2012-04-18 | 索尼株式会社 | 锁相环电路、读写装置及电子装置 |
CN101421928B (zh) * | 2006-01-26 | 2012-05-23 | 日本电波工业株式会社 | Vco驱动电路以及频率合成器 |
CN101282116B (zh) * | 2007-04-04 | 2012-11-14 | 阿尔特拉公司 | 生成最小脉冲宽度的相位频率检测器 |
CN102055467B (zh) * | 2009-11-05 | 2013-02-06 | 晨星软件研发(深圳)有限公司 | 锁相回路与其相关方法 |
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US7352249B2 (en) | 2003-10-03 | 2008-04-01 | Analog Devices, Inc. | Phase-locked loop bandwidth calibration circuit and method thereof |
CA2555468C (en) * | 2004-02-20 | 2016-05-03 | Gct Semiconductor, Inc. | Improvement of the coarse tuning time in pll with lc oscillator |
US20090128242A1 (en) * | 2005-05-26 | 2009-05-21 | Freescale Semiconductor, Inc. | Frequency generation in a wireless communication unit |
KR101515099B1 (ko) * | 2008-10-07 | 2015-04-24 | 삼성전자주식회사 | 전하펌프, 전하펌프 보정 장치 및 이를 포함한 위상 동기 루프 |
US7952436B2 (en) * | 2009-06-23 | 2011-05-31 | Fortemedia, Inc. | Phase lock loop circuit |
US10141941B2 (en) * | 2016-12-30 | 2018-11-27 | Huawei Technologies Co., Ltd. | Differential PLL with charge pump chopping |
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US5126692A (en) * | 1987-08-03 | 1992-06-30 | Western Digital Corporation | Variable frequency system having linear combination of charge pump and voltage controlled oscillator |
US5631587A (en) * | 1994-05-03 | 1997-05-20 | Pericom Semiconductor Corporation | Frequency synthesizer with adaptive loop bandwidth |
EP0961412B1 (en) * | 1998-05-29 | 2004-10-06 | Motorola Semiconducteurs S.A. | Frequency synthesiser |
US6157271A (en) * | 1998-11-23 | 2000-12-05 | Motorola, Inc. | Rapid tuning, low distortion digital direct modulation phase locked loop and method therefor |
US6163184A (en) * | 1998-12-09 | 2000-12-19 | Lucent Technologies, Inc. | Phase locked loop (PLL) circuit |
US6680653B2 (en) * | 2000-09-29 | 2004-01-20 | Skyworks Solutions, Inc. | VCO tuning curve compensated charge pump current synthesizer |
US6583675B2 (en) * | 2001-03-20 | 2003-06-24 | Broadcom Corporation | Apparatus and method for phase lock loop gain control using unit current sources |
DE10132799A1 (de) * | 2001-07-06 | 2002-10-02 | Infineon Technologies Ag | Phasenregelschleife |
US6724265B2 (en) * | 2002-06-14 | 2004-04-20 | Rf Micro Devices, Inc. | Compensation for oscillator tuning gain variations in frequency synthesizers |
-
2002
- 2002-09-12 DE DE10242364A patent/DE10242364A1/de not_active Ceased
-
2003
- 2003-08-11 DE DE50302636T patent/DE50302636D1/de not_active Expired - Lifetime
- 2003-08-11 WO PCT/DE2003/002695 patent/WO2004027997A1/de active IP Right Grant
- 2003-08-11 EP EP03797167A patent/EP1543621B1/de not_active Expired - Fee Related
- 2003-08-11 CN CN03821801.1A patent/CN1682446A/zh active Pending
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101421928B (zh) * | 2006-01-26 | 2012-05-23 | 日本电波工业株式会社 | Vco驱动电路以及频率合成器 |
CN101282116B (zh) * | 2007-04-04 | 2012-11-14 | 阿尔特拉公司 | 生成最小脉冲宽度的相位频率检测器 |
CN101640537B (zh) * | 2008-07-31 | 2012-04-18 | 索尼株式会社 | 锁相环电路、读写装置及电子装置 |
CN102055467B (zh) * | 2009-11-05 | 2013-02-06 | 晨星软件研发(深圳)有限公司 | 锁相回路与其相关方法 |
Also Published As
Publication number | Publication date |
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DE10242364A1 (de) | 2004-03-25 |
DE50302636D1 (de) | 2006-05-04 |
US20050212605A1 (en) | 2005-09-29 |
EP1543621B1 (de) | 2006-03-08 |
WO2004027997A1 (de) | 2004-04-01 |
EP1543621A1 (de) | 2005-06-22 |
US7106141B2 (en) | 2006-09-12 |
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