CN1661808A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1661808A
CN1661808A CN2005100062507A CN200510006250A CN1661808A CN 1661808 A CN1661808 A CN 1661808A CN 2005100062507 A CN2005100062507 A CN 2005100062507A CN 200510006250 A CN200510006250 A CN 200510006250A CN 1661808 A CN1661808 A CN 1661808A
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guard ring
semiconductor layer
raceway groove
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冈田哲也
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Sanyo Electric Co Ltd
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Abstract

一种半导体装置。目前在肖特基势垒二极管的周围设有用于确保耐压的护圈。护圈由于是p+型区域，故在施加反向电压时，耗尽层会向其周围扩展构成低电容化的障碍。而在施加正向电压时，当超过规定电压时，就要从护圈注入空穴，不能实现高速动作。本发明在现有护圈区域设置沟道并在内部设置绝缘膜。沟道一直设到n+型半导体衬底。由此，耗尽层在到达n+型衬底前仅沿深度方向扩展，可实现低电容化。且由于不再需要p+型区域，故也不会再注入空穴，不产生反向恢复时间(Trr)。因此，可提高开关动作速度。

Description

半导体装置
技术领域
本发明涉及半导体装置，尤其是涉及实现了肖特基势垒二极管的低电容化及高速开关的半导体装置。
背景技术
图4显示现有肖特基势垒二极管D2。图4(A)是平面图，图4(B)是图4(A)的B-B剖面图。另外，在平面图中省略了肖特基金属层及阳极电极。
衬底是在n+型半导体衬底12a上层积n-型外延层12b而形成的衬底，在n-型外延层12b表面设置与n-型外延层12b形成肖特基结的金属层13。该金属层13例如是Mo。金属层13和n-型外延层12b接触的区域构成肖特基结区域。
在肖特基结区域最外周，为确保规定耐压设有扩散了P+型杂质的护圈15。
覆盖金属层13整个面设置由Al等构成的阳极电极16，在衬底背面设置阴极电极17(例如参照专利文献1)。
专利文献1：特开平6-224410号公报(第二页、图2)。
但是，如图4所示，现有肖特基势垒二极管D2通过在周围设置护圈15扩展了耗尽层，形成了可得到规定耐压的结构。
在肖特基势垒二极管中，与n-型半导体层形成肖特基结的肖特基金属层可认为是模拟的p区域，在施加反向偏压时，耗尽层自肖特基结区域起在n-型半导体层扩展。在例如不设护圈的情况下，在肖特基结区域端部耗尽层的曲率大。因此电场集中在肖特基结区域端部，造成损坏。
因此，如图5所示，在肖特基结区域端部设置p+型护圈。由此，在施加反向偏压时，虚线所示的耗尽层50沿横(衬底水平)向扩展。因此，可缓和肖特基结区域端部的耗尽层50的曲率并得到规定的耐压。
但是，耗尽层50当然也向护圈周围扩展。耗尽层50形成电容分量，故不能促进肖特基势垒二极管的低电容化。
另外，还存在护圈会成为高速动作的障碍的问题。护圈15和n-型外延层2形成pn结。护圈15还和肖特基金属层13接触，故在施加正向电压时当超过规定的电压时，该区域作为pn结二极管工作。
通常，pn结二极管的正向上升电压为0.6V左右，肖特基势垒二极管的正向上升电压为0.4V左右，另外，当超过0.65V程度时，两二极管的正向电压VF-反向电压IF特性反转。即在0.6V左右之前pn结二极管不工作，但当超过使正向电压VF-反向电压IF特性反转的电压时，护圈15作为pn结二极管工作，实际工作区域的肖特基势垒二极管也同时动作。
图6是肖特基势垒二极管D2施加正向电压时护圈15的局部放大图。
在大于导通时的电压(例如0.65V)的正向电压下使用肖特基势垒二极管D2时，如前所述，护圈部分作为pn结二极管工作，并从护圈15向n-型外延层12b注入载流子(空穴)。
然后，当为了切换到切断状态施加反向电压时，如图6所示，载流子被蓄积在n-型外延层12b，故在蓄积在外延层12b的载流子进行流出或再结合后，耗尽层50开始扩展。也就是说，在形成切断状态之前产生用于该载流子的流出或再结合的时间(反向恢复时间：Trr)。
即通过设置用于确保耐压的护圈不能促进低电容化，且存在成为高速动作的妨碍的问题。
发明内容
本发明就是鉴于上述问题而开发的，本发明第一方面提供一种半导体装置来解决上述问题，其包括：一导电型半导体衬底；设置在该衬底上的一导电型半导体层；与该半导体层表面形成肖特基结的金属层；设置在所述半导体层和所述金属层的肖特基结区域外周并贯通所述半导体层直至所述一导电型半导体衬底的沟道；至少覆盖所述沟道内壁的绝缘膜。
所述沟道内部由所述绝缘膜掩埋。
所述沟道内部由所述绝缘膜覆盖且埋设所述金属层的一部分。
在向所述金属层和所述半导体层施加反向电压时，在所述半导体层扩展的耗尽层于衬底水平方向的扩展在所述沟道终结。
另外，当在所述金属层和所述半导体层施加反向电压时，在所述半导体层扩展的耗尽层仅向所述半导体衬底的深度方向扩展。
根据本发明，在肖特基结区域端部和中央附近耗尽层的扩展均匀，故可得到稳定的耐压。
通过设置氧化膜(沟道)直至n+型衬底，可消除目前扩展到护圈周围的耗尽层，实现低电容化。
另外，由于不再需要构成护圈的p+型区域，故在施加正向电压时不进行空穴的注入。即没有载流子的蓄积，因此不需要进行空穴的流出或再结合。因此，不产生反向恢复时间(Trr)，可提高开关动作速度，具体地说，可将目前数百ns的开关动作速度提高到数十ns左右。另外可消除开关时的损耗，故可提高装置的效率
附图说明
图1是说明本发明的半导体装置的(A)平面图，(B)剖面图；
图2是说明本发明的半导体装置的剖面图；
图3(A)、(B)、(C)是说明本发明的半导体装置制造方法的剖面图；
图4是用于说明现有半导体装置的(A)平面图、(B)剖面图；
图5是用于说明现有半导体装置的剖面图；
图6是说明现有半导体装置的剖面图。
具体实施方式
参照图1～图3详细说明本发明的实施例。
图1表示本发明的肖特基势垒二极管D1。图1(A)是平面图，图1(B)是图1(A)的A-A线剖面图。另外，图1(A)中省略了表面的肖特基金属层和阳极电极。
本发明的肖特基势垒二极管D1由一导电型半导体衬底1、一导电型半导体层2、沟道5、绝缘膜6与肖特基金属层9构成。
衬底是在n+型半导体衬底1上通过例如外延成长等而层积了n-型半导体层2的衬底。
在n-型半导体层2表面设置与n-型半导体层2表面形成肖特基结的例如Mo等的肖特基金属层9。n-型半导体层2和肖特基金属层9接触的区域是肖特基结区域3。
在肖特基结区域3最外周，设置包围肖特基结区域3的沟道5。沟道5贯通n-型半导体层2达到n+型半导体衬底1。
沟道5根据耐压不同可设置为比n-型半导体层2更深，但作为一例，若n-型半导体层2为5μm～6μm，则沟道5设为7μm～8μm。
在沟道5的至少内壁上设置绝缘膜6。图中表示沟道5内埋设有绝缘膜6的情况。绝缘膜6在本实施例中采用了氧化膜，但也可以取代氧化膜而采用氮化膜等绝缘膜。
由此，在施加反向电压时耗尽层的衬底水平方向的扩展在沟道5(绝缘膜6)形成终端。另外，此时也可以仅在沟道5内壁覆盖绝缘膜6，而在内部埋设肖特基金属层9的一部分等金属，可得到同样的效果。
在肖特基金属层9上设置由Al等的金属层形成的阳极电极10，在衬底背面也蒸镀金属层设置阴极电极11。
图2显示施加反向电压时耗尽层扩展的情况。
如上所述，肖特基金属层9是模拟的p+型区域。而且，在肖特基结区域3最外周设有直至n+型衬底的绝缘化区域，该绝缘化区域在沟道5的至少内壁设有绝缘膜。
在肖特基势垒二极管D1施加反向电压时，利用肖特基金属层9和n-型半导体层2的肖特基结，耗尽层50在n-型半导体层2扩展。
此时，耗尽层50如虚线所示，在沟道5(氧化膜6)形成终端，耗尽层50仅向半导体衬底的深度方向扩展。也就是说，耗尽层50的端部不形成曲面，不存在曲率。
由此，图5所示的肖特基势垒二极管D2中，不会产生扩展到护圈周围(具体地说护圈底部和护圈外侧)的耗尽层，故可降低这一部分的电容成分，实现低电容化。
由于不再需要构成护圈的p+型区域，故在施加正向电压时不进行空穴的注入。即不存在载流子的蓄积，故不需要进行空穴的流出或再结合。因此，不会发生反向恢复时间(Trr)，可提高开关动作速度，具体地说，可将目前数百ns的开关动作速度提高到数十ns左右。另外可消除开关时的损耗，故可提高装置的效率
另外，在本实施例中，不再需要考虑耗尽层50向衬底水平方向的扩展。也就是说，耐压设计中只要控制n-型半导体层的厚度和比电阻即可，耐压稳定。而且由于护圈附近不存在曲率，可得到稳定的耐压，故可通过降低n-型半导体层2的比电阻ρ降低正向电压VF。或可通过减薄n-型半导体层2的厚度t来降低正向电压VF。
下面采用图3说明本发明肖特基势垒二极管的制造方法的一例。如图3(A)所示，在n+型半导体衬底1上层积例如由外延成长等形成的n-型半导体层2。然后，设置掩模M，该掩模M仅在与构成肖特基结区域的肖特基金属层接触的接触区域3a的最外周开口。然后，形成贯通n-型半导体层2并到达n+型半导体衬底1的沟道5。即沟道5包围接触区域3a并设置在其最外周。
如图3(B)，沟道5内部形成氧化膜(或氮化膜)等绝缘膜6。也就是说，在除去掩模M后，在整个面上形成氧化膜6。仅在沟道5上部设置抗蚀剂掩模进行蚀刻，在沟道5埋设氧化膜6。这样，在本实施例中，说明了在沟道5内埋设氧化膜6的方法，但也可以仅将氧化膜6设于沟道5内壁，而内部在其后的工序中埋设肖特基金属层等的金属。由此，在施加反向电压时可确保稳定的耐压。
在图3(C)中，蒸镀和接触区域3a及在沟道5开口部露出的氧化膜6的一部分接触的肖特基金属层9(例如Mo等)。由此，接触区域3a构成肖特基金属层9和n-型半导体层2的肖特基结区域3。在构图为至少覆盖肖特基结区域3的所需形状后，为硅化物化而在500～600℃进行退火处理。在此，在不能得到例如规定的VF的情况下，替换Mo使用Bn低的Ni、Cr、Ti等。
然后，整个面蒸镀构成阳极电极10的Al层，并构图为所需的形状，在背面形成例如Ti/Ni/Au等的阴极电极11，得到图1所示的最终结构。

Claims (5)

1、一种半导体装置，其特征在于，其包括：一导电型半导体衬底；设置在该衬底上的一导电型半导体层；与该半导体层表面形成肖特基结的金属层；设置在所述半导体层和所述金属层的肖特基结区域外周并贯通所述半导体层到达所述一导电型半导体衬底的沟道；至少覆盖所述沟道内壁的绝缘膜。
2、如权利要求1所述的半导体装置，其特征在于，所述沟道内部由所述绝缘膜埋设。
3、如权利要求1所述的半导体装置，其特征在于，所述沟道内部由所述绝缘膜覆盖且埋设所述金属层的一部分。
4、如权利要求1所述的半导体装置，其特征在于，在向所述金属层和所述半导体层施加反向电压时，在所述半导体层扩展的耗尽层于所述衬底水平方向的扩展由所述沟道终结。
5、如权利要求1所述的半导体装置，其特征在于，在所述金属层和所述半导体层施加反向电压时，在所述半导体层扩展的耗尽层仅向所述半导体衬底的深度方向扩展。
CN2005100062507A 2004-02-24 2005-02-02 半导体装置 Pending CN1661808A (zh)

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