CN1643677A - 用于制造半导体衬底的方法和所得结构 - Google Patents
用于制造半导体衬底的方法和所得结构 Download PDFInfo
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- CN1643677A CN1643677A CNA038060140A CN03806014A CN1643677A CN 1643677 A CN1643677 A CN 1643677A CN A038060140 A CNA038060140 A CN A038060140A CN 03806014 A CN03806014 A CN 03806014A CN 1643677 A CN1643677 A CN 1643677A
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Abstract
本发明公开了用作制备半导体芯片、尤其是化合物半导体器件的基础的半导体晶片复合件。有利的是,半导体晶片复合件包括金属衬底(210)和结合到金属衬底(210)表面上的多个半导体块(220)。半导体晶片复合件有效地用作大量制备的单个大的半导体晶片,并且可用来以类似方式制备半导体器件。
Description
相关申请的交叉引用
本申请要求共同转让的、2002年3月14日提交的澳大利亚临时专利申请No.PS 1122的优先权,并且这里以参考文献的方式引用了其内容。
技术领域
本发明一般地涉及制造衬底。更具体地,本发明提供了用于形成高级半导体器件的改进型半导体衬底的方法和器件。仅仅作为实例,本发明已应用于用来制造高级半导体器件的金属衬底,这种衬底包括结合到衬底上的多个板(panel)和/或块(tile)。但是,应该认识到本发明具有远远更为广泛的应用范围。
背景技术
随着技术发展,半导体生产商一直致力于使用更大的晶片来实现规模经济,从而降低单个半导体器件的成本。通常,硅晶芯棒(boule)可以较容易地长大到足以切片成直径为12英寸的晶片。这种12英寸的晶片已被用来生产具有各种应用的单晶硅材料。虽然这种单晶硅具有许多优点,但它依然存在很多缺点。
许多传统产业已经越来越依赖由化合物半导体所制得的化合物半导体器件,所述化合物半导体例如是砷化镓、磷化铟和氮化镓。不幸的是,与硅半导体所制得的电路相比,由这些半导电的化合物所制得的集成电路仍然相对昂贵。这种成本差异主要可归因于各个材料成本和晶片加工成本。化合物半导体材料还存在其他限制。
化合物半导体晶片更易于损坏。例如,它们比传统的单晶硅晶片更易碎。与生长大的单晶硅芯棒相比较,生长大的化合物半导体材料的晶体芯棒极其困难。在常规商业应用中,商业化生产的砷化镓、磷化铟和氮化镓化合物半导体晶片的最大直径分别为6英寸、4英寸和6英寸。
更大的化合物半导体晶片是所期望的。不幸的是,难以高效地制造出更大直径的晶片。即使更大的化合物半导体材料芯棒可以被生产出,但处理所得的大直径化合物半导体晶片一般都存在问题。厚度和直径都合适的化合物半导体晶片极为易碎,并且容易破裂。这里,更大的晶片一般会破裂是由于这些半导体化合物的脆性引起的。因此,某些技术已被建议来利用外延生长层生产更大的化合物半导体晶片。
仅仅作为实例,制备化合物半导体芯片的传统工艺可以概括为以下的步骤(i)-(vii)。
(i)在单晶衬底上生长外延器件层。
(ii)利用光刻技术图案化这些外延层以及其他被沉积的介电层和金属层。
(iii)完成正面工艺之后,将晶片面朝下结合到临时支持衬底上。
(iv)通过机械抛光或磨平背面来减薄晶片。
(v)在衬底中形成“通孔”,所述通孔提供了将背面接地连接到合适的正面接地连接的途径。
(vi)在晶片的背面上沉积金属膜以提供接地面,并涂布通孔的壁,从而与正面接地连接形成接触。
(vii)将晶片切割成单个的芯片。
在以上的传统工艺中,晶片在步骤(i)、(ii)和(iii)过程中通常厚625微米,并且在小心处理的情况下,具有足够的机械强度来避免损坏。晶片在步骤(iv)中厚度通常会被减薄到约50-100微米。减薄的衬底具有许多优点,如:
(i)减小了通孔的深度(和大小),以及与通孔相关的寄生电感;
(ii)将热从正面器件导向背面,而背面通常连接到散热器;以及
(iii)防止了高频下衬底内的电磁共振。
处理变薄的化合物半导体晶片经常较困难,并且化合物半导体晶片通常从步骤(iv)起就会被损坏。由于大部分处理(步骤(i)-(iii))已经完成,所以这种损坏代价很高。化合物半导体材料的脆性还会导致所得芯片器件的损坏,并且限制了使用化合物半导体材料的更大尺寸的实用芯片设计。这样,更大尺寸的化合物半导体材料并不能实际地用于高效的制造。
由于以上的问题,存在对用于生产并处理半导体晶片的改进型技术的需求。具体地,需要适合有助于实际地、成本合算地生产化合物半导体器件的技术。
发明内容
根据本发明,提供了制造衬底的技术。更具体地,本发明提供了用来形成高级半导体器件的改进型半导体衬底的方法和器件。仅仅作为实例,本发明已应用于用来制造高级半导体器件的金属衬底,该衬底包括结合到衬底上的多个板和/或块。但是,应该认识到本发明具有远远更为广泛的应用范围。
这里描述了用来生产可以制备半导体芯片的半导体晶片复合件(composite)的技术。半导体晶片复合件包括金属衬底和结合到金属衬底表面上的一个或多个半导体“块”。如后面所描述的,这些半导体块是通过将半导体晶片切割成所期望的形状而形成的。所述技术在制备化合物半导体器件中发现了具体应用,但它还可更广泛地适用于各种类型的半导体晶片。
多个晶片块在任何正面处理之前被有益地结合到金属衬底上。当复合件被分成单个的芯片时,金属衬底理想的是仍保持与半导体材料的接合。半导体晶片制件被有效地用作单个大的半导体晶片,并且可用来以类似方式制备半导体器件。由于金属衬底的存在,该复合件更耐用、更高效。
有利的是,半导体块是正方形或长方形,或者一种或多种能够方便地镶嵌到金属衬底上以高效地覆盖金属衬底表面的其他形状。这些形状通常是由标准“经剪裁的圆形(clipped-circular)”晶片形状切割而成。
在具体实施例中,本发明提供了封装的化合物半导体集成电路器件。封装的器件包括具有背表面的化合物半导体衬底。该器件具有结合到所述背表面的金属衬底。金属衬底在封装之前为化合物半导体衬底提供了机械支撑。这种金属支撑允许对化合物半导体进行处理。根据优选的实施例,化合物半导体的预定尺寸大于如果没有金属支撑就将被损坏的尺寸。这里,如果没有支撑结构,大尺寸对于高效处理将显得过大。支撑衬底被耦合到金属衬底上,用于封装。
通过使用结合到金属衬底上的半导体块,可获得各种好处。半导体晶片复合件没有半导体块那样易碎,并且这样可以以更大面积来进行处理。结果,通过更大量的制备可实现成本节约。
具体地,通过使用多个半导体块,迄今已由更小直径的晶片生产出的化合物半导体晶片可以任意有效的尺寸来进行处理。结果,现有的用于处理直径为12英寸的硅晶片的制备设备可用来制备使用所述半导体晶片复合件的化合物半导体器件。
附图说明
图1是根据本发明实施例的半导体晶片复合件的俯视图的简化示意性表示,所述复合件包括其上结合有四个正方形半导体块的圆形金属衬底。
图2是对应于图1的简化横截面视图。
图3是根据本发明实施例的由图1和2的半导体晶片复合件制备半导体芯片所涉及方法的简化流程图。
具体实施方式
根据本发明,提供了制造衬底的技术。更具体地,本发明提供了用来形成高级半导体器件的改进型半导体衬底的方法和器件。仅仅作为实例,本发明已应用于用来制造高级半导体器件的金属衬底,该衬底包括结合到衬底上的多个板和/或块。但是,应该认识到本发明具有远远更为广泛的应用范围。
这里将描述半导体晶片复合件。这种复合件非常适合制备化合物半导体器件。而且,该复合件尤其应用在这种器件的大规模生产中。以下将首先描述制备单个半导体器件所用的半导体晶片复合件,接着描述使用所述半导体晶片复合件进行半导体器件的高容量生产的工序。
图1和2分别利用俯视和侧视而示意性地表示了根据本发明实施例的简化半导体晶片复合件。该图仅仅是一实例,不应不恰当地限制这里权利要求的范围。本领域的普通技术人员将认识到许多变化、修改和替换。半导体晶片复合件可有效地替代现有的制备半导体芯片器件所用的半导体晶片。
图1和2所示的所述半导体晶片复合件包括金属衬底210,其上结合有许多半导体块220。
图1示出了呈圆形的金属衬底210,以及四个邻接的长方形半导体块220。用虚线表示的四个长方形代表可在金属衬底210的周边附近结合到金属衬底210上的其他长方形半导体块220,从而更有效地使用金属衬底210的表面。该衬底优选用具有良好的导电性和导热性,并且其热膨胀系数与半导体块的热膨胀系数相匹配的材料制得。例如,CuMo、AlSi和Mo都是合适的材料。优选地,该衬底高度导电,根据具体实施例,其电阻率在1-10微欧姆·厘米(1-10×10-6ohm cm)的范围内。或者,根据其他实施例,这种材料可以是半导体。块220被紧密地放置在一起,但可能并不是直接地邻接。晶片块220之间细微的间隔降低了对块尺寸的精度要求,并且如果需要的话,考虑了轻微的热膨胀空隙。指示性的空隙尺寸例如可以小于5微米。优选地,每个块都应有一轻微空隙来彼此隔开,以解决容限的任何差异。或者,根据其他实施例,这些块彼此邻接来防止或减小杂质(例如光刻胶)进入块间的区域。
图2是对应于图1的侧视图。图1中用虚线绘制的外围半导体块220没有在图2中示出。金属衬底210包括金属基底层240,其上形成有金属结合层250。金属基底层240可以由合适的与化合物半导体材料的热膨胀系数(CTE)相匹配的金属或合金形成。对于砷化镓(GaAs)化合物半导体块220,金属衬底的合适选择是钼化铜(CuMo)。金属结合层250理想地由锡(Sn)或铟(In)和金(Au)、或其他合适的熔点相对低并且一经加热即形成共晶合金的金属形成。在优选的实施例中,共晶合金完全通过压紧形成,并且在块和衬底之间没有相对横向运动。
半导体块220包括化合物半导体材料(例如砷化镓(GaAs))的工作层260和互补结合层270,该结合层270优选由有助于半导体块220粘附到金属衬底210上的材料形成。合适的材料是钛(Ti)和金(Au)的组合。
金属基底层240和金属结合层250的周围是薄的金属涂层290,由贵金属形成。金(Au)或铂(Pt)优选被使用。涂层290将金属衬底210密封,来防止在随后的半导体晶片复合件制备半导体器件的过程中造成损坏。例如,涂层290可以通过蒸发/沉积技术,或通过电镀来涂覆。
以上参照图1和2描述了半导体晶片复合件的组成,而下面将参照制造半导体晶片复合件的工艺来描述半导体晶片复合件的各种其他相关特征和优点。这里参照图3的步骤310-330来描述这种制造工艺。图3的余下步骤340-370描述了由半导体晶片复合件制备半导体器件的后续步骤。
在具体实施例中,每个块都具有具体的大小和形状。金属衬底也具有合适的形状和大小。也就是说,金属衬底的直径是“dm”,这是根据预定晶片处理设备的处理能力选择的。优选地,这一尺寸从一组行业直径中选择,例如2英寸、3英寸、4英寸、5英寸、6英寸、8英寸和12英寸。衬底形成的形状要能在周边的一部分上提供一“平面”来作为对准基准,这一点类似于常规晶片。
而且,衬底可以被图案化来提供孔,这些孔有利于封装操作,或者方便了离开芯片的信号耦合。例如,这些孔可用来形成辐射离开芯片的高频信号的插槽。
这些块由半径为“ds”的圆形化合物半导体晶片切割而成,其中晶片直径“ds”的整数倍等于金属衬底直径“dm”,即dm=n×ds,其中n为最小可能的整数。这种关系确保了在将块切割成合适形状的过程中,块的数目可以最少,并且昂贵化合物半导体材料的浪费可以达到最小。例如,四个对角线尺寸为3英寸的正方形的块可以由3英寸的半导体晶片切割而成,从而以2×2块阵列来覆盖六英寸的金属衬底。如果仅有直径为2英寸的半导体晶片可用,则可准备九个对角线为2英寸的正方形块以3×3阵列来覆盖六英寸的衬底。当然,可以进行各种修改、替换和变化。
虽然上述半导体晶片是利用具体实施例来说明的,但可进行许多变化、替换和修改。例如,金属衬底可以由合金或其他材料、以及其他具有合适的电特性和热特性的多层材料等制得。金属衬底根据具体应用也可以是多层的。此外,衬底上一个或多个块可以由不同材料制成。这些变化和其他变化都可以在本说明书通篇中找到,以下有更具体地说明。
在具体实施例中,总而言之,制备化合物半导体器件的方法涉及以下表1中列出的步骤。图3将这些步骤流程化,这在下面将作更详细地描述。
表1
步骤310 减薄多个半导体晶片220
步骤320 将晶片220切割形成半导体块
步骤330 将半导体块220结合到金属衬底210上
步骤340 使用标准正面处理技术来制备器件
步骤350 从正面向金属衬底210开通孔
步骤360 金属化通孔以形成到金属衬底210的接地连接
步骤370 金属衬底210被切成独立的单个芯片
如上所示,以上步骤仅仅是说明性的。根据实施例,某些步骤可以进一步分解,或者甚至与其他步骤组合。根据实施例还可添加其他步骤。其他步骤可以替代以上的某些步骤。因此,存在许多变化、修改和替换。每个步骤的具体细节都可以在本说明书通篇中找到,以下有更具体地说明。
减薄半导体块一步骤310
各个晶片块220是根据现有的处理技术减薄的。如果晶片在此处损坏,由于半导体块220的正面还没有处理,所以相关成本会相对的低。根据具体实施例,块是利用磨平/磨削和/或抛光操作而被减薄的。根据某些实施例,这些块的厚度可以减薄到约50-100微米。根据具体实施例,这些块是利用磨平/磨削和/或抛光操作而被减薄的。
形成半导体块一步骤320
半导体晶片被切割来形成半导体块220。优选地,每个块都是利用划线和开裂工艺来提供的。更优选地,划线可以通过金刚石刻针、激光切割等来提供。优选地,这些是“标准”晶片,其具有生长在其正面上的外延层,并已准备用于器件制备。半导体块220具有这样的形状,以使这些半导体块220可以以最小的中间间隙覆盖平面。根据具体实施例,每个块沿着晶面形成,这提供了精确的形状和形态。这种精确的形状和形态允许每个块两两之间的对准,以减小每个块两两之间形成间隙的可能性。这样还使得随后能够将所有块以相同的晶向排列在金属衬底上。
将块结合到衬底上一步骤330
选择金属衬底材料以在所要求的处理温度范围内与所选定的半导体的热膨胀系数(CTE)相匹配。这种衬底材料还针对其强度、导热率和导电率以及成本而进行选择。优选地,这种衬底还具有高的导热率,以将来自形成在其上的集成器件的热带走。根据某些实施例,金属衬底的导热率可以为165瓦/米·开或更大。
例如,约80%钼和20%铜的合金的CTE与砷化镓的相匹配,并具有合适的导电率和导热率。使用金属衬底210的好处在于:CTE可以通过改变金属合金的组成来调节。如果使用的是例如硅的晶体衬底,则这种调节是不可能的。
金属衬底210的一个面被抛光,其周边的形状适合大直径晶片处理设备。优选地,抛光步骤减小了在衬底表面和这些块之间形成空气间隙的可能性。在某些实施例中,在整个衬底上,金属衬底的表面粗糙度不大于预定值,均一度小于某个值,以方便结合工艺。根据某些实施例,表面还可以包括一系列图案和/或纹理,这样防止了空气气泡等的形成,并增强了结合处理。这通常意味着金属衬底210是圆形的(如图1和2所示)。较小平面可以在一侧提供,以与现有的晶片处理设备相适应。
优选地,金属衬底210制得尽可能的薄,这样不会增加复合结构的重量或热容。通常厚度可能在200微米-400微米之间。
接着,如果存在衬底210可能被随后的半导体处理化学物质影响的风险,则在金属衬底210上沉积惰性涂层290。例如金或铂的贵金属薄层(厚度通常不到1微米)一般适于此用。优选地,涂层在随后的半导体处理步骤中是非反应性的。其他材料(例如氮化硅)也可以使用,只要这种材料能够足以抵抗在预期晶片处理步骤中使用的处理化学物质和温度。
结合层250沉积在金属衬底210经抛光的表面上。该金属结合层250优选由一经加热即形成共晶合金的两种或多种金属制得。最外层优选是贵金属(例如金),其防止了底下层在结合之前和结合过程中发生氧化。底下层可以由锡或铟形成。如此选择这些金属,以使共晶合金在相对低的温度(例如,200℃)下形成,并且形成后,不会在晶片处理过程中遭遇的高温下熔化。该结合层也可起金属衬底的惰性涂层的作用。
互补结合层270也沉积在每个减薄的半导体晶片块220的背面上。这种互补结合层270也优选为金属,其组成被选择以在随后的处理温度范围内提供对半导体块220的最大粘附。这种优选的层结构是钛/金或钛/铂/金,但是在不偏离本发明的范围和精神的情况下可以是许多其他的金属组合。
许多其他的结合层组成都是可以的,并且可以为满足不同半导体材料的特定处理要求(例如最大温度)来选择。
金属结合层的使用带来了允许结合在相对低的温度(例如,200℃)下发生的优点。这确保了晶片块220的外延层结构不会劣化。例如硅、多晶硅、二氧化硅或氮化硅的非金属互补结合层270也可以被使用。
由于半导体块220之间大的间隙可能会不利地影响到光刻胶的旋涂沉积,所以避免这种间隙是所期望的。半导体块220优选是正方形或长方形。这些形状允许长方形芯片阵列被高效地容纳在半导体块220内,并且还允许沿着通常为长方形的晶体面划线并开裂来切割半导体块220。
但是,其他块形状也可以被使用。例如,六边形的块可以比长方形的块更高效地覆盖圆形衬底210的表面。优选的实施例使用一组不均匀的正方形块或长方形块,如图1所示的。所选择图案的半导体块220取决于可用半导体晶片的大小以及金属衬底210的大小。
半导体块220位于金属衬底210经抛光的表面上,这样使得半导体块220优选地彼此邻接(或者留有紧密的间隔而放置在一起),来形成基本连续的半导体表面。由于上述原因,小的间隙(例如,小于5微米)可能是有益的。半导体块220的排列要能确保共同的晶轴取向。接着,半导体块220和金属衬底210在高温下经受压力,这导致共晶合金的形成,以及将半导体块220永久地结合到金属衬底210上。
复合件的正面处理一步骤340
现在根据标准半导体制备技术来处理复合晶片的正面。考虑到半导体块220之间存在轻微的未对准,在每个块220上都提供有基准对准标记。优选地,单个芯片如此排列在半导体块220上,使得芯片整个容纳在块220内,并且不会跨越半导体块的边界。
开通孔一步骤350
与现有的从晶片的背面向正面形成通孔的半导体工艺不同,可以从正面向金属衬底210开通孔。这样通孔的对准被简化了,因为这种对准是相对于其他可见的正面特征进行的。
金属化通孔一步骤360
金属衬底210的存在允许在通孔工艺中去除大面积的半导体块220,而不会损害复合晶片的结构强度。这意味着通孔“沟槽”可以形成在半导体块220上。这些沟槽能够提供如下特征:
(i)相比较普通的圆形通孔而言相对低电感的接地连接;
(ii)相邻电路之间的电磁屏蔽,所述电磁屏蔽随着电路密度增加变得重要;
(iii)芯片隔开的轮廓;和
(iv)造型(contouring)半导体晶片来实现局部的散热特征。
切割成单个器件一步骤370
根据处理机械的能力,从正面或背面切割金属衬底210来分离出单个的芯片。
由于每个芯片由一部分金属衬底210支持着,所以芯片在处理过程中出现损坏的情况会减小。而且,可以制备出更大的芯片。结果,更多的功能/系统可以集成在单个芯片上。这种芯片通过简化工程和生产要求而大大节约了成本。
每个芯片上金属衬底210的存在还起散热器的作用,这在高功率应用中是有益的。
其他变化
上述制备工序的一种变化是将未减薄的晶片块220结合到金属衬底210上。半导体块220可以在结合到金属衬底210上后被减薄。这种变化提供了在减薄工艺过程中“平坦化”晶片复合件的半导体表面的优点。结果,外延器件层生长在晶片复合件上。
这种改变的工序在某些情况下可以提供经济效益。而且,结合之前对晶片块220的处理要求要宽松一些,因为这个阶段半导体块220更厚。
这里描述了金属结合层250,但是其他技术可用来将半导体块220固定在金属衬底210上。例如,适合半导体制备中所涉及的温度和化学处理条件的粘合剂可用来将半导体块220粘附到金属衬底210上。
这里所述的技术适于制造包括那些使用复合半导体大直径复合金属衬底的半导体器件。除了这里所述的其他好处,所述技术潜在地提高了射频性能,通过规模经济提高了产率并降低了成本。
在不偏离本发明的范围和精神的情况下,根据本公开内容显然可以对这里所述的结构和技术进行各种变化、修改和替换,这些对相关领域的技术人员是明显的。
Claims (50)
1.一种用于制备半导体器件的半导体晶片复合件,所述半导体晶片复合件包括:
金属衬底;和
结合到所述金属衬底上的至少一个半导体块。
2.如权利要求1所述的半导体晶片复合件,其中所述至少一个半导体块依次被(i)切割成预定形状,(ii)减薄,并(iii)结合到所述金属衬底上。
3.如权利要求1所述的半导体晶片复合件,其中所述至少一个半导体块依次被(i)减薄,(ii)切割成预定形状,并(iii)结合到所述金属衬底上。
4.如权利要求1所述的半导体晶片复合件,其中所述至少一个半导体块依次被(i)切割成预定形状,(ii)结合到所述金属衬底上,并(iii)减薄。
5.如权利要求1所述的半导体晶片复合件,其中通过从所述至少一个半导体块的正面在半导体材料内刻蚀出孔,并图案化所得正表面和孔壁上的金属层,从而在所述至少一个半导体块正表面上的半导体器件和所述金属衬底之间形成连接。
6.如权利要求5所述的半导体晶片复合件,其中半导体材料被从所述至少一个半导体块去除来形成细长的沟槽,这些沟槽排列形成围绕所述至少一个半导体块的所述表面的若干部分的周边。
3.如权利要求1所述的半导体晶片复合件,其中所述半导体晶片复合件被切片以形成具有金属衬底的单个集成电路。
4.如权利要求1所述的半导体晶片复合件,其中所述金属衬底包括金属基底层和结合层,所述至少一个半导体块结合到所述结合层上。
5.如权利要求1所述的半导体晶片复合件,其中所述金属衬底还包括基本覆盖所述金属基底层和/或结合层的至少一部分的惰性涂层。
6.如权利要求1所述的半导体晶片复合件,其中所述至少一个半导体块包括化合物半导体。
7.如权利要求10所述的半导体晶片复合件,其中所述至少一个半导体块还包括适合粘附到所述金属衬底的互补结合层。
8.如权利要求11所述的半导体晶片复合件,其中所述互补结合层主要由一种或多种金属形成,所述金属的其中之一是贵金属。
9.如权利要求8所述的半导体晶片复合件,其中所述结合层主要由两种或更多种金属形成,所述金属被加热时形成共晶合金。
10.如权利要求9所述的半导体晶片复合件,其中所述惰性涂层主要由贵金属形成。
11.如权利要求1所述的半导体晶片复合件,其中所述金属衬底和所述至少一个半导体块分别具有基本为相似值的热膨胀系数。
12.如权利要求1所述的半导体晶片复合件,其中所述至少一个半导体块基本为长方形或正方形。
13.一种制造用于制备半导体器件的半导体晶片复合件的方法,所述方法包括:
提供金属衬底;以及
将至少一个半导体块结合到所述金属衬底上。
14.如权利要求17所述的方法,还依次包括(i)将所述至少一个半导体块切割成预定形状,(ii)减薄所述至少一个半导体块,并(iii)将所述至少一个半导体块结合到所述金属衬底上。
15.如权利要求17所述的方法,还依次包括(i)减薄所述至少一个半导体块,(ii)将所述至少一个半导体块切割成预定形状,并(iii)将所述至少一个半导体块结合到所述金属衬底上。
16.如权利要求17所述的方法,还依次包括(i)将所述至少一个半导体块切割成预定形状,(ii)将所述至少一个半导体块结合到所述金属衬底上,并(iii)减薄所述至少一个半导体块。
17.如权利要求17所述的方法,还包括如下步骤:
通过从所述至少一个半导体块的正面在半导体材料内刻蚀出孔,并图案化所得正表面和孔壁上的金属层,从而在所述至少一个半导体块的正表面上的半导体器件和所述金属衬底之间形成连接。
18.如权利要求21所述的方法,还包括从所述至少一个半导体块去除半导体材料来形成细长的沟槽,这些沟槽排列形成围绕所述至少一个半导体块的所述表面的若干部分的周边。
19.如权利要求17所述的方法,还包括将所述半导体晶片复合件切片以形成具有金属衬底的单个集成电路。
20.如权利要求17所述的方法,还包括由金属基底层和结合层形成所述金属衬底,所述至少一个半导体块结合到所述结合层上。
21.如权利要求17所述的方法,还包括用惰性涂层基本覆盖所述金属基底层和/或结合层的至少一部分。
22.如权利要求17所述的方法,还包括形成具有主要是化合物半导体的工作层的所述至少一个半导体块。
23.如权利要求17所述的方法,还包括形成具有互补结合层的所述至少一个半导体块,所述互补结合层适合将所述至少一个半导体块粘附到所述金属衬底上。
24.如权利要求27所述的方法,还包括形成主要是一种或多种金属的所述互补结合层,所述金属的其中之一是贵金属。
25.如权利要求24所述的方法,还包括形成主要是两种或更多种金属的所述结合层,所述金属被加热时形成共晶合金。
26.如权利要求25所述的方法,还包括形成主要是贵金属的所述惰性涂层。
27.如权利要求17所述的方法,还包括将所述至少一个半导体块和所述金属衬底各自的热膨胀系数匹配为基本相似的值。
28.如权利要求17所述的方法,还包括将半导体晶片切成基本为长方形或正方形的形状,来形成所述至少一个半导体块。
29.一种用于制备半导体器件的半导体晶片复合件,所述半导体晶片复合件是由包括如下步骤的工艺制造的:
提供金属衬底;以及
将至少一个半导体块结合到所述金属衬底上。
30.如权利要求33所述的半导体晶片复合件,其中所述工艺还依次包括(i)将所述至少一个半导体块切割成预定形状,(ii)减薄所述至少一个半导体块,并(iii)将所述至少一个半导体块结合到所述金属衬底上。
31.如权利要求33所述的半导体晶片复合件,其中所述工艺还依次包括(i)减薄所述至少一个半导体块,(ii)将所述至少一个半导体块切割成预定形状,并(iii)将所述至少一个半导体块结合到所述金属衬底上。
32.如权利要求33所述的半导体晶片复合件,其中所述工艺还依次包括(i)将所述至少一个半导体块切割成预定形状,(ii)将所述至少一个半导体块结合到所述金属衬底上,并(iii)减薄所述至少一个半导体块。
33.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括如下步骤:
通过从所述至少一个半导体块的正面在半导体材料内刻蚀出孔;并
图案化所得正表面和孔壁上的金属层,从而在所述至少一个半导体块的正表面上的半导体器件和所述金属衬底之间形成连接。
34.如权利要求37所述的半导体晶片复合件,其中所述工艺还包括从所述至少一个半导体块去除半导体材料来形成细长的沟槽,这些沟槽排列形成围绕所述至少一个半导体块的所述表面的若干部分的周边。
35.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括将所述半导体晶片复合件切片以形成具有金属衬底的单个集成电路。
36.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括由金属基底层和结合层形成所述金属衬底,所述至少一个半导体块结合到所述结合层上。
37.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括用惰性涂层基本覆盖所述金属基底层和/或结合层的至少一部分。
38.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括形成具有主要是化合物半导体的工作层的所述至少一个半导体块。
39.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括形成具有互补结合层的所述至少一个半导体块,所述互补结合层适合将所述至少一个半导体块粘附到所述金属衬底上。
40.如权利要求43所述的半导体晶片复合件,其中所述工艺还包括形成主要是一种或多种金属的所述互补结合层,所述金属的其中之一是贵金属。
41.如权利要求40所述的半导体晶片复合件,其中所述工艺还包括形成主要是两种或更多种金属的所述结合层,所述金属被加热时形成共晶合金。
42.如权利要求41所述的半导体晶片复合件,其中所述工艺还包括形成主要是贵金属的所述惰性涂层。
43.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括将所述至少一个半导体块和所述金属衬底各自的热膨胀系数匹配为基本相似的值。
44.如权利要求33所述的半导体晶片复合件,其中所述工艺还包括将半导体晶片切成基本为长方形或正方形的形状,来形成所述至少一个半导体块。
45.一种用于制备半导体器件的半导体晶片复合件,所述半导体晶片复合件包括:
金属衬底,所述金属衬底包括(i)基底金属层,(ii)金属结合层,主要由被加热时形成共晶合金的两种或更多种金属形成,以及(iii)主要由贵金属形成的惰性涂层;和
多个半导体块,所述多个半导体块通过在所述半导体块和所述金属衬底物理接触时,加热所述半导体块和所述金属衬底而结合到所述金属衬底上,以使所述半导体块经过所述惰性涂层而结合到所述金属结合层。
46.一种封装的化合物半导体集成电路器件,包括:
具有背表面的化合物半导体衬底;
结合到所述背表面的金属衬底,在封装前所述金属衬底为所述化合物半导体衬底提供了机械支撑;和
耦合到所述金属衬底的、用于封装的支撑衬底。
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AUPS1122 | 2002-03-14 | ||
AUPS1122A AUPS112202A0 (en) | 2002-03-14 | 2002-03-14 | Semiconductor manufacture |
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US (3) | US6919261B2 (zh) |
EP (1) | EP1483786A1 (zh) |
CN (1) | CN1643677A (zh) |
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-
2002
- 2002-03-14 AU AUPS1122A patent/AUPS112202A0/en not_active Abandoned
-
2003
- 2003-03-13 WO PCT/AU2003/000298 patent/WO2003077311A1/en not_active Application Discontinuation
- 2003-03-13 CN CNA038060140A patent/CN1643677A/zh active Pending
- 2003-03-13 US US10/389,278 patent/US6919261B2/en not_active Expired - Fee Related
- 2003-03-13 EP EP03707901A patent/EP1483786A1/en not_active Withdrawn
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2005
- 2005-02-02 US US11/050,010 patent/US20050160972A1/en not_active Abandoned
- 2005-07-19 US US11/185,238 patent/US20050255672A1/en not_active Abandoned
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CN105522326A (zh) * | 2014-10-21 | 2016-04-27 | 波音公司 | 使用纤维转向的复合层压板的热膨胀调节系数 |
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Also Published As
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US6919261B2 (en) | 2005-07-19 |
US20050255672A1 (en) | 2005-11-17 |
US20040007763A1 (en) | 2004-01-15 |
US20050160972A1 (en) | 2005-07-28 |
EP1483786A1 (en) | 2004-12-08 |
WO2003077311A1 (en) | 2003-09-18 |
AUPS112202A0 (en) | 2002-04-18 |
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