CN1635635A - 直接连结式芯片封装结构 - Google Patents

直接连结式芯片封装结构 Download PDF

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CN1635635A
CN1635635A CNA2004100660953A CN200410066095A CN1635635A CN 1635635 A CN1635635 A CN 1635635A CN A2004100660953 A CNA2004100660953 A CN A2004100660953A CN 200410066095 A CN200410066095 A CN 200410066095A CN 1635635 A CN1635635 A CN 1635635A
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CN1312769C (zh
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梁志忠
刘道明
周正伟
茅礼卿
闻荣福
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Changdian Technology Management Co ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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Abstract

本发明涉及一种直接连结式芯片封装结构，属分立半导体器件及集成电路技术领域。包括芯片1、引线框3和塑封料体5，芯片1置于引线框3的承载基岛3.1上，芯片1背面与承载基岛3.1用胶2粘合，其特点是引线框3的引线脚3.2脚端制成弹簧脚，芯片1正面与引线脚3.2脚端用焊料4直接焊接，塑封料体5将芯片1、引线框3的承载基岛3.1和引线脚3.2脚端封装。本发明能减低电阻抗率、提高电流量和散热能力、降低成本、参数部分可以不用调整、连接牢固。

Description

直接连结式芯片封装结构
技术领域：
本发明涉及一种芯片封装结构，尤其是涉及一种直接连结式芯片封装结构。属分立半导体器件及集成电路技术领域。
背景技术：
传统的芯片封装一般常用间接引线式结构。其封装结构参见图1～2：功能芯片1′置于金属引线框3′的承载基岛上，芯片1′背面与金属引线框3′的承载基岛之间用导电或非导电胶2′连结，芯片1′正面与金属引线框3′的引线脚之间用信号引导金线4′焊接，然后用保护用塑封料体5′将芯片1′、金属引线框3′的承载基岛以及信号引导金线4′封装。其主要存在以下不足：
1、芯片与金属引线框之间采用金丝焊接，有两个焊接点，接触面积小。缺点是：电阻抗率高，电流量限制较大且散热能力较差。
2、基岛与金丝打线脚焊接处均需要镀银。缺点是：镀银成本较高，且因镀银不良的报废率也较高。
3、晶片上焊点方式为金球+热+超声波压在芯片上。缺点是各项作业的参数受限较大，稍有不慎即会造成芯片表面及芯片内部线路受损，且因不同芯片厚度及金丝直径不同即要重新修改参数。
发明内容：
本发明的目的在于克服上述不足，提供一种能减低电阻抗率、提高电流量和散热能力、降低成本、参数部分可以不用调整、连接牢固的直接连结式芯片封装结构。
本发明的目的是这样实现的：一种直接连结式芯片封装结构，包括芯片、引线框和塑封料体，芯片置于引线框的承载基岛上，芯片背面与承载基岛用胶粘合，其特点是引线框的引线脚脚端制成弹簧脚，芯片正面与引线脚脚端用焊料直接焊接，塑封料体将芯片、引线框的承载基岛和引线脚脚端封装。而因为有弹性功能的引线脚，所以可以自动调节封芯片厚薄不均的各种压力。
与传统打线方式相比，本发明具有如下优点：
1、用引线脚直接与芯片正面焊接，只有一个焊接点，接触面积大。优点是：减低电阻抗率，提高电流量，提高散热能力。
2、引线脚焊接处无需镀银。优点是：充分节省镀银及因镀银不良的成本费用。
3、弹簧引线脚轻轻的压在芯片表面，并采用铅锡银或锡膏进行焊接。优点：一是因弹簧的优点可以克服不同芯片厚度，而参数部分几乎可以不用调整；二是接触面积大，连结牢度强，不易被分开。
附图说明：
图1为一般常用间接引线式芯片封装结构正面图。
图2为图1的A-A剖示图。
图3为本发明直接连结式芯片封装结构正面图。
图4为图3的B-B剖示图。
具体实施方式：
如图3～4，本发明为一种直接连结式芯片封装结构。由功能芯片1、芯片与承载基岛连结用导电或非导电胶2、金属引线框3以及保护用塑封料体5组成。
功能芯片1置于金属引线框3的承载基岛3.1上，芯片1背面与承载基岛3.1之间用导电或非导电胶2连结，金属引线框3的信号引导引线脚3.2脚端制成弹簧脚，引线脚3.2脚端开设有连结孔3.2.1，引线脚3.2脚端置于芯片1正面，引线脚3.2脚端与芯片1连结用铅锡银或锡膏4焊接，金属焊料4渗入引线脚3.2脚端连结孔3.2.1内，与引线脚3.2脚端呈铆钉状反扣连接，然后用保护用塑封料体5将芯片1、金属引线框3的承载基岛3.1和引线脚3.2脚端封装。

Claims (2)

1、一种直接连结式芯片封装结构，包括芯片(1)、引线框(3)和塑封料体(5)，芯片(1)置于引线框(3)的承载基岛(3.1)上，芯片(1)背面与承载基岛(3.1)用胶(2)粘合，其特征在于引线框(3)的引线脚(3.2)脚端制成弹簧脚，芯片(1)正面与引线脚(3.2)脚端用焊料(4)直接焊接，塑封料体(5)将芯片(1)、引线框(3)的承载基岛(3.1)和引线脚(3.2)脚端封装。
2、根据权利要求1所述的一种直接连结式芯片封装结构，其特征在于引线脚(3.2)脚端开设有连结孔(3.2.1)，焊料(4)渗入连结孔(3.2.1)内，与引线脚(3.2)脚端呈铆钉状反扣连接。
CNB2004100660953A 2004-12-17 2004-12-17 直接连结式芯片封装结构 Active CN1312769C (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101927669A (zh) * 2010-09-19 2010-12-29 广东省粤晶高科股份有限公司 一种轮胎压力监测装置的封装工艺
CN101958303A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片正装单颗封装结构及其封装方法
CN101958305A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片正装模组封装结构及其封装方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2823066B2 (ja) * 1994-04-25 1998-11-11 日立電線株式会社 Ｂｇａ型半導体装置
JP2891665B2 (ja) * 1996-03-22 1999-05-17 株式会社日立製作所 半導体集積回路装置およびその製造方法
TW414924B (en) * 1998-05-29 2000-12-11 Rohm Co Ltd Semiconductor device of resin package
CN2758976Y (zh) * 2004-12-17 2006-02-15 江苏长电科技股份有限公司 直接连结式芯片封装结构

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958303A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片正装单颗封装结构及其封装方法
CN101958305A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片正装模组封装结构及其封装方法
CN101958303B (zh) * 2010-09-04 2012-09-05 江苏长电科技股份有限公司 双面图形芯片正装单颗封装结构及其封装方法
CN101958305B (zh) * 2010-09-04 2012-09-19 江苏长电科技股份有限公司 双面图形芯片正装模组封装结构及其封装方法
CN101927669A (zh) * 2010-09-19 2010-12-29 广东省粤晶高科股份有限公司 一种轮胎压力监测装置的封装工艺
CN101927669B (zh) * 2010-09-19 2012-08-15 广东省粤晶高科股份有限公司 一种轮胎压力监测装置的封装工艺

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