CN1627489A - Load supporting base plate for semiconductor chip and fabricating method - Google Patents
Load supporting base plate for semiconductor chip and fabricating method Download PDFInfo
- Publication number
- CN1627489A CN1627489A CNA2003101202731A CN200310120273A CN1627489A CN 1627489 A CN1627489 A CN 1627489A CN A2003101202731 A CNA2003101202731 A CN A2003101202731A CN 200310120273 A CN200310120273 A CN 200310120273A CN 1627489 A CN1627489 A CN 1627489A
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- Prior art keywords
- hole
- manufacture method
- conductive layer
- metal substrate
- holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Led Device Packages (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
Multiple first through holes are setup at metal base plate with conducting layers covering its upper and lower faces. Plugging the through holes forms multiple plugs. Second time of drilling holes is carried out for the said plugs in order to form a protection layer on hole wall of each first through hole. Conducting layer of through hole is formed on the protection layer. Thus, upper and lower parts of conducting layer of each through hole are contacted to upper and lower faces of conducting layers. Chips can be installed on the disclosed metal base plate in double sided connection type so as to reach high thermal diffusivity, prolong service life of chips and increase LED brightness.
Description
Technical field
The present invention is the substrate of relevant a kind of semiconductor chip, particularly about a kind of tool high-cooling property and metal substrate structure and manufacture method thereof that can two-sided connection.
Background technology
Along with the height aggregationization of the circuit junction of integrated circuit and the extensive use of semiconductor chip, it is important that the radiator structure of semiconductor element more seems.With light-emitting diode (light-emittingdiode LED) is example since it possess colorful, power saving, the life-span is long and advantage such as fail safe height, has been widely used in the illumination aspect at present; Yet the LED element but generally has the problem of poor heat radiation.
The light-emitting diode assembly of existing tool radiator structure as shown in Figure 1, be that the light-emitting diode 10 that an encapsulation is finished is utilized surface adhering technology (surface mount technology, SMT) adhere on the aluminium sheet 12, with by aluminium sheet 12 as the usefulness of strengthening heat radiation; Yet, this kind mode must be connected led chip 14 earlier and be made into after the complete light-emitting diode 10 with printed circuit board (PCB) (printed circuit board PCB) 16 routings, light-emitting diode 10 is adhered on the single face circuit 20 of aluminium sheet 12 with tin cream 18 again.This mode not only increases cost of manufacture and material cost, and simultaneously must see through behind the printed circuit board (PCB) 16 of plastic cement or ceramic material could be via aluminium sheet 12 heat radiations for the heat dissipation path of led chip 14, and still have the not good disappearance of radiating effect; Moreover, because led chip 14 self-radiatings are bad, so its luminous intensity and just can being affected useful life.Again, this aluminium sheet 12 is only applicable to single face and connects, that is aluminium sheet 12 only can be as the heating panel of light-emitting diode 10, and can't be directly as the substrate of SMD type LED.
Therefore, the present invention proposes a kind of bearing substrate and manufacture method thereof of semiconductor chip promptly at above-mentioned problem.
Summary of the invention
Main purpose of the present invention, provide a kind of bearing substrate of semiconductor chip, the way of utilization secondary drilling on metal substrate, cooperate the control of suitable consent material and boring processing procedure, provide the two-sided connecting-type metal substrate of via with making, and then overcome the disappearance that has the difficulty of on rabbet ink, holing now and single face connecting-type metal substrate only can be provided.
Another object of the present invention, provide a kind of metal substrate, semiconductor chip directly is implanted on the bearing substrate of this metal material, so that chip can directly be dispelled the heat, and must could see through outside metallic plate heat radiation via printed circuit board (PCB) as not needing as having now, and then effectively promote the ability of heat-radiating semiconductor chip.
An order more of the present invention is at the metal substrate that a two-sided connecting-type is provided, so that reach the effect that prolongs the LED life-span and increase brightness.
For reaching above-mentioned purpose; the present invention provides a metal substrate earlier; this metal substrate two relatively the surface respectively be provided with a upper and lower conductive layer; then on this metal substrate, form plural via; wherein each via runs through metal substrate; and be to be covered with a protective layer earlier on the hole wall of each via, form a through hole conductive layer again on protective layer.
1. the manufacture method of a semiconductor chip bearing substrate comprises the following steps:
One metal substrate is provided, and this metal substrate comprises a metallic plate, is covered with on one conductive layer on the applying glue-line and in regular turn at the upper surface of this metallic plate, and is covered with fit a glue-line and a lower conductiving layer in regular turn at the lower surface of this metallic plate;
Carrying out the bore operation first time, is to this metal substrate boring, to form plural first through hole; These first through holes are filled up and form plural stick harness;
Carrying out the bore operation second time, is to the boring of these stick harnesses, and forming plural second through hole, and the aperture of this second through hole is little than this first through hole, makes respectively to be formed with a protective layer on the hole wall of each this first through hole: and
Form plural through hole conductive layer on the hole wall of these second through holes, so that the upper and lower part of each this through hole conductive layer does not contact with this upper and lower conductive layer.
Below cooperate appended graphic explanation in detail by specific embodiment, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 is the light-emitting diode assembly schematic diagram of existing tool radiator structure;
Fig. 2 to Fig. 9 is the present invention's each step structure cutaway view in making semiconductor chip bearing substrate;
Figure 10 is that bearing substrate of the present invention uses the structural representation as the support plate of led chip.
Embodiment
Use the purpose of metal substrate to be to strengthen thermal diffusivity, the thermal conductivity of metal is good than pottery and plastic cement, and when using metal substrate as the support plate of semiconductor wafer such as LED wafer, the heat energy that can be successfully LED be produced when luminous is emitted in the air.Fig. 2 to Fig. 9 is the present invention's each step structure cutaway view in making semiconductor chip bearing substrate, please consult shown in Figure 7 earlier, be structural representation of the present invention, the bearing substrate 30 of semiconductor chip comprises a metal substrate 32, the dust head is an aluminium sheet, its two respectively be provided with on the surface relatively one upper and lower in conjunction with glue-line 34,34 ', two upper and lower conductive layers 36,36 ' are incorporated into respectively on two surfaces of metal substrate 32 in conjunction with glue-line 34,34 ' to see through two, this two conductive layer 36,36 ' normally is the copper layer; In addition; metal substrate 32 is provided with the via 38 that plural number runs through; on the hole wall of each via 38, be covered with a protective layer 40 and a through hole conductive layer 42 in regular turn; protective layer 40 is made up of the resin of epoxy resin; and through hole conductive layer 42 is generally copper plate, and its upper and lower part is to contact with upper and lower conductive layer 36,36 ' respectively.
This semiconductor chip bearing substrate 30 must overcome via 38 behind consent on making, boring and the difficulty that keeps rabbet ink not produce crack (crack) and come off on rabbet ink again, and manufacture method of the present invention can overcome this problem.
After understanding overall structure of the present invention, continue detailed description each layer structure of the present invention and preparation method thereof, see also Fig. 2 to shown in Figure 9.At first, as shown in Figure 2, provide a metal substrate 32, the dust head is an aluminium sheet, and two of this metal substrate 32 is covered with two upper and lower conductive layers 36,36 ' through two in conjunction with glue-line 34,34 ' on the surface relatively, it typically is the copper layer; Then carry out the bore operation first time as shown in Figure 3, this step is to form a plurality of first through holes 38 and location hole 39 to metal substrate 32 borings; Continue and carry out the consent operation as shown in Figure 4, this step is with printing ink these first through holes 38 to be filled up, the filling printing ink after baking-curing and brushing operation, promptly form plural stick harness 44, wherein this printing ink be for the splendid epoxide resin material of metal substrate 32 tacks; Next just carry out the bore operation second time as shown in Figure 5; be to form plural second through hole 46 to these stick harness 44 borings; the aperture of this second through hole 46 is little than first through hole 38; with after boring for the second time, make the protective layer 40 that respectively is formed with a resin material on the hole wall of each first through hole 38.
Wherein, in the step of boring for the second time, because above-mentioned rabbet ink is more than the hardness after the curing is up to 9H, printing ink produces crack (crack) when avoiding holing, so drilling liner plate must use the higher material of hardness, can not use general boring urea plate or FR4 (FR4 be meant be C-Stage contain glue glass cloth general designation), this drilling liner plate is generally the phenolic resins plate; In addition, the feed of boring speed preferably is controlled at 1.4 to 1.6m/s for the second time, and rotating speed is preferably and is controlled at 35 to 45krpm, and withdrawing speed is preferably 24 to 26m/s, borehole conditions cooperates suitable printing ink thus, makes consent post 44 can not produce the crack when boring or comes off.
On first through hole 38, complete after the protective layer 40; continue as shown in Figure 6; soon carry out the electro-coppering operation; and then at the last through hole conductive layer 42 that forms of the hole wall (being protective layer 40) of these second through holes 46; and also form copper plate 47 in the lump on upper and lower conductive layer 36,36 ' surface, the upper and lower part of each through hole conductive layer 42 is contacted with this upper and lower conductive layer 36,36 ' respectively.Because the metal substrate 32 direct copper facing meetings of aluminium matter are made metal substrate 32 oxidation blackening because of aluminium, copper produce chemical cross reaction; therefore between first through hole 38 of metal substrate 32 and through hole conductive layer 42, must be provided with this protective layer 40 earlier, then could be in the operation of metal substrate 32 enterprising electroplating copper.After forming these copper through hole conductive layers 42, promptly as shown in Figure 7, carry out the making operation of circuit moulding, so that on the copper plate 47 of metal substrate 32, produce circuit layout 48.So far, each primary structure of tentatively finishing bearing substrate 30 is made.
Wherein the circuit moulding is to use general print circuit plates making mode, that is uses the press mold machine that universe film is pasted on the plate face, utilizes egative film to cover on universe film again, sees through Exposure mode and makes universe film carry out light polymerization, and successfully circuit is transferred; Utilize developing manufacture process with molten the going of unpolymerized universe film afterwards again,, see through etch process again and remove unwanted copper face partly, utilize the striping processing procedure at last again, remove all universe films on the plate face, to stay required circuit to stay the universe rete of the required circuit of protection.
After finishing that circuit makes, the present invention more can continue and carry out the surface-treated step more as shown in Figure 8, and it utilizes the electronickelling gold or change surface treatment method that nickel soaks gold and forms a surface treatment film 50.Carry out electronickelling gold or change nickel and soak golden surface-treated purpose except being protected the not oxidations of copper face by surface treatment film 50, topmost function provides second solder joint connection of routing (wirebonding) and uses.
At last, cover the hole operation as shown in Figure 9, plural universe film 52 is covered these second through holes 46 respectively, wherein universe film 52 is to be photosensitive polymer, so promptly finishes the making of semiconductor wafer bearing substrate 30.In this step, the resin the when purpose in lid hole is to prevent follow-up led chip encapsulation sees through the weld pad (pad) that second through hole 46 flows to another side and goes up and form insulating barrier, to avoid losing the function of welding conducting.At this, only need to get final product in the single face lid hole of metal substrate 32.
When above-mentioned bearing substrate 30 replaces existing printed circuit board (PCB) as the substrate of semiconductor chip, because the thermal conductivity of metal is good than pottery and plastic cement, so can effectively strengthen the thermal diffusivity of semiconductor chip.Figure 10 is that bearing substrate of the present invention uses the structural representation as the support plate of a led chip, as shown in the figure, on this bearing substrate 30, be provided with a groove 60 according to design requirement, then led chip 54 directly is implanted on the bearing substrate 30 of metal material with elargol 56, then bonding wire and potting resin, finish a LED potted element 58, can dispel the heat, and then prolong the life-span of LED and increase brightness by the aluminum metal of substrate 30 self.
Therefore, the way of utilization of the present invention secondary drilling on metal substrate cooperates the suitable consent material and the control of borehole conditions, provides the two-sided connection substrate of via with making, and the installation semiconductor chip is provided.So the present invention is not only overcoming the disappearance that has the difficulty of holing now and single face connection metallic plate only can be provided on rabbet ink on the manufacture method, and then the substrate of a two-sided connecting-type is provided, more can make the semiconductor chip that is mounted thereon reach the effect of efficiently radiates heat simultaneously.
Claims (10)
1. the manufacture method of a semiconductor chip bearing substrate is characterized in that, comprises the following steps:
One metal substrate is provided, and this metal substrate comprises a metallic plate, is covered with on one conductive layer on the applying glue-line and in regular turn at the upper surface of this metallic plate, and is covered with fit a glue-line and a lower conductiving layer in regular turn at the lower surface of this metallic plate;
Carrying out the bore operation first time, is to this metal substrate boring, to form plural first through hole; These first through holes are filled up and form plural stick harness;
Carrying out the bore operation second time, is to the boring of these stick harnesses, and forming plural second through hole, and the aperture of this second through hole is little than this first through hole, makes respectively to be formed with a protective layer on the hole wall of each this first through hole: and
Form plural through hole conductive layer on the hole wall of these second through holes, so that the upper and lower part of each this through hole conductive layer does not contact with this upper and lower conductive layer.
2, manufacture method as claimed in claim 1 is characterized in that, described this metallic plate is to be aluminium sheet.
3, manufacture method as claimed in claim 1 is characterized in that, described to fill up the employed material of these first through holes be the printing ink that is for epoxy resin.
4, manufacture method as claimed in claim 1 is characterized in that, and is described in the step of carrying out boring for the second time, is to use the drilling liner plate of high rigidity.
5, manufacture method as claimed in claim 4 is characterized in that, described this drilling liner plate is a phenolic resins.
6, manufacture method as claimed in claim 1 is characterized in that, the step of these through hole conductive layers of described formation is to use plating mode.
7, manufacture method as claimed in claim 1 is characterized in that, the material of described this upper and lower conductive layer and this through hole conductive layer is a copper.
8, manufacture method as claimed in claim 1 is characterized in that, describedly more comprises a step after forming these through hole conductive layers, is the operation of this upper and lower conductive layer being carried out the circuit moulding, to produce circuit layout.
9, manufacture method as claimed in claim 1 is characterized in that, and is described after forming these through hole conductive layers, more comprises a surface-treated step.
10, manufacture method as claimed in claim 9 is characterized in that, the employed processing method of described this surface-treated step is to be selected from electronickelling gold and to change nickel and soak gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2003101202731A CN1627489A (en) | 2003-12-10 | 2003-12-10 | Load supporting base plate for semiconductor chip and fabricating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2003101202731A CN1627489A (en) | 2003-12-10 | 2003-12-10 | Load supporting base plate for semiconductor chip and fabricating method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1627489A true CN1627489A (en) | 2005-06-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2003101202731A Pending CN1627489A (en) | 2003-12-10 | 2003-12-10 | Load supporting base plate for semiconductor chip and fabricating method |
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| CN (1) | CN1627489A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359709C (en) * | 2005-06-09 | 2008-01-02 | 宁波雷登照明有限公司 | High power and quick heat radiating light emitting diode in white light |
| CN102076165A (en) * | 2011-01-30 | 2011-05-25 | 乐健线路板（珠海）有限公司 | Double-layer high-heat dissipation sandwich metal base printed circuit board |
| CN103068187A (en) * | 2011-10-19 | 2013-04-24 | 上海嘉捷通信息科技有限公司 | Blind hole plate device capable of preventing the blind hole from lacking glue |
| CN101626000B (en) * | 2008-07-10 | 2014-11-26 | 晶元光电股份有限公司 | Metal array basal plate, photoelectric element, light-emitting element and manufacturing method thereof |
| CN104470209A (en) * | 2012-04-20 | 2015-03-25 | 乾坤科技股份有限公司 | Metal core printed circuit board and electronic packaging structure |
| CN104637902A (en) * | 2013-11-06 | 2015-05-20 | 上海蓝沛新材料科技股份有限公司 | Intelligent card module |
| CN105458628A (en) * | 2015-12-14 | 2016-04-06 | 谢兴龙 | Hole-drilling and automatic-adhesive-tape-wrapping production method of circuit board |
| CN110582157A (en) * | 2018-06-11 | 2019-12-17 | 欣兴电子股份有限公司 | circuit board and manufacturing method thereof |
| CN113286435A (en) * | 2021-05-25 | 2021-08-20 | 胜宏科技（惠州）股份有限公司 | Method for plating copper in aluminum plate hole |
| CN114449744A (en) * | 2022-03-29 | 2022-05-06 | 江西景旺精密电路有限公司 | High-heat-dissipation circuit board manufacturing method and high-heat-dissipation circuit board |
| WO2023236427A1 (en) * | 2022-06-06 | 2023-12-14 | 北京梦之墨科技有限公司 | Electronic structure and manufacturing method therefor |
-
2003
- 2003-12-10 CN CNA2003101202731A patent/CN1627489A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359709C (en) * | 2005-06-09 | 2008-01-02 | 宁波雷登照明有限公司 | High power and quick heat radiating light emitting diode in white light |
| CN101626000B (en) * | 2008-07-10 | 2014-11-26 | 晶元光电股份有限公司 | Metal array basal plate, photoelectric element, light-emitting element and manufacturing method thereof |
| CN102076165A (en) * | 2011-01-30 | 2011-05-25 | 乐健线路板（珠海）有限公司 | Double-layer high-heat dissipation sandwich metal base printed circuit board |
| CN103068187A (en) * | 2011-10-19 | 2013-04-24 | 上海嘉捷通信息科技有限公司 | Blind hole plate device capable of preventing the blind hole from lacking glue |
| CN104470209B (en) * | 2012-04-20 | 2018-11-27 | 乾坤科技股份有限公司 | Metal-core printed circuit board and electron package structure |
| CN104470209A (en) * | 2012-04-20 | 2015-03-25 | 乾坤科技股份有限公司 | Metal core printed circuit board and electronic packaging structure |
| CN104637902A (en) * | 2013-11-06 | 2015-05-20 | 上海蓝沛新材料科技股份有限公司 | Intelligent card module |
| CN105458628A (en) * | 2015-12-14 | 2016-04-06 | 谢兴龙 | Hole-drilling and automatic-adhesive-tape-wrapping production method of circuit board |
| CN110582157A (en) * | 2018-06-11 | 2019-12-17 | 欣兴电子股份有限公司 | circuit board and manufacturing method thereof |
| CN113286435A (en) * | 2021-05-25 | 2021-08-20 | 胜宏科技（惠州）股份有限公司 | Method for plating copper in aluminum plate hole |
| CN114449744A (en) * | 2022-03-29 | 2022-05-06 | 江西景旺精密电路有限公司 | High-heat-dissipation circuit board manufacturing method and high-heat-dissipation circuit board |
| CN114449744B (en) * | 2022-03-29 | 2024-03-22 | 江西景旺精密电路有限公司 | Manufacturing method of high-heat-dissipation circuit board and high-heat-dissipation circuit board |
| WO2023236427A1 (en) * | 2022-06-06 | 2023-12-14 | 北京梦之墨科技有限公司 | Electronic structure and manufacturing method therefor |
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