CN1610113A - A three-dimensional complementary metal oxide semiconductor device structure and its preparation method - Google Patents

Abstract

The invention relates to a three-dimensional complementary metal oxide semiconductor (CMOS) device structure and a preparation method thereof, belonging to the technical field of microelectronics. The present invention is characterized in that it proposes a three-dimensional multi-layer CMOS structure, and the layers are connected by wires. The key to preparing this structure is to be able to prepare multiple layers of single crystal thin films separated by insulating layers. The present invention proposes low-temperature bonding and low-temperature peeling techniques to transfer single crystal thin films to insulating layers and prepare single crystal thin films on this single crystal thin film. device active layer. The three-dimensional CMOS proposed by the present invention does not change the basic structure of CMOS, high-density integration can be realized by adopting conventional CMOS technology and equipment conditions, the process method is simple, and the length and layer number of metal interconnection lines can be reduced, and the speed of devices can be improved.

Description

A three-dimensional complementary metal oxide semiconductor device structure and its preparation method

Background technique

At present, the integrated circuit (IC) industry follows Moore's law, the integration of devices is getting bigger and bigger, the performance doubles every 18 months, and the price drops by half. At present, there are mainly three methods to improve the integration of devices: reducing the feature size of the device, increasing the wafer area, and preparing three-dimensional structure devices. In the past few years, MOS (metal oxide semiconductor) integrated circuits have developed rapidly, from 0.25μm to 0.13μm and even 90nm, which has brought earth-shaking changes to semiconductor technology. However, as the device size reaches the nanometer range, it will face many new problems, such as the traditional exposure technology can no longer meet the requirements, and new low dielectric constant dielectric materials must be sought. Therefore, the emergence of new technical problems and the high cost make it more and more difficult to reduce the feature size of the device to improve the integration of the device. Although the "bottom-up" technology is also proposed, that is, starting from nano-dots, nano-wires and even atoms and molecules to prepare nano-devices, this technology is still a long way from the industry. Wafer technology has been developed from 8 inches to 12 inches, but the increase in wafer size will reduce its yield. Regardless of whether it is to reduce the feature size of the device or increase the wafer area, the equipment and process line need to be replaced every time it is updated, which puts a certain pressure on the depreciation of equipment in semiconductor factories.

The three-dimensional device structure has been proposed as early as the 1980s, and has been applied to technologies such as memory, for example, in order to increase the capacitor area, the capacitor is prepared into a slot shape; in order to improve the static random access memory (SRAM) of 6 transistor units 2 of the transistors are prepared on top of the remaining 4 transistors to achieve the highest level of integration. Because it is difficult to prepare single crystal silicon on an insulator, two thin film transistors are prepared on polycrystalline, and a large commercial profit is obtained in a 0.25μm process, but due to the existence of grain boundaries, the transistor channel carrier mobility and switching The current ratio is relatively low, and when the working voltage is less than 1.8V, it can no longer meet the requirements, and commercial production has been stopped. Therefore, Lee proposed to use an annealing process to convert amorphous silicon into single crystal silicon, thereby preparing single crystal thin film transistors. (Ga Won Lee, patent number: US6,723,589 B2) Although this method can greatly improve the performance of thin film transistors, it still cannot prepare large-area single crystal silicon. SJAbou-Samra et al. proposed a three-dimensional MOS with PMOS stacked on top of NMOS. The upper monocrystalline silicon layer adopts the method of lateral epitaxy. This method also cannot obtain large-area monocrystalline silicon, and the processing temperature is high. Two-layer MOS structure (SJAbou-Samra, et al., Proc. Of the ^8th International Symposium on SOI Technology and Devices, Paris, France, September 1997, PP384-388). There is also a method of vertical CMOS structure, that is, the MOS structure is inverted, and the source and drain are placed in the upper and lower positions. This method can reduce the unit area of CMOS to 1/4 of the original, but the process of this structure is very complicated, and the structure There is parasitic capacitance (Lamb AC, Riley LS, Hall S, Kunz VD, de Groot CH, Ashburn P, ESSDERC 2001 conference proceedings p347; http://drl.ee.ucla.edu ).

In short, from the perspective of current three-dimensional CMOS technology, except for special vertical CMOS, the material for preparing thin film transistors is either polycrystalline silicon or small-area single crystal silicon. The CMP technology and the bonding and stripping technology widely used in SOI technology provide the possibility for large-area single crystal silicon to be transferred to an insulating substrate containing devices. Due to the presence of device layers and metal interconnects, low temperature processing becomes a key issue. The research results of Drago Resnik et al. show that the chemically treated two silicon wafers are bonded and then annealed at 400°C to reach the saturated bond strength (Drago Resnik, et al., Sensors and Actuators 80 (2000) 68-76). Generally speaking, the hydrogen-injected sheet with a dose of 6×10 ¹⁶ cm ^-2 peels off at about 500°C, while the peeling temperature of the samples co-injected with boron and hydrogen is less than 400°C (T.Hochbauer et al., Journal of Applied Physics, 86(1999) 4176-4183; Duo Xinzhong, Ph.D. Dissertation, 2001). In fact, bonded sheets containing hydrogen injection layers or porous silicon layers can be successfully peeled off at room temperature under mechanical action (WGEn, IJ Malik, MA Bryan et al, Proceedings 1998 IEEE International SOI Conference, Oct. 1998: 163). These research works provide a technical basis for low temperature thin film transfer.

Contents of the invention

The object of the present invention is to provide a high-density three-dimensional CMOS structure suitable for large-scale production and a preparation method thereof.

The invention provides a multi-layer one-sided CMOS structure with the number of layers greater than or equal to two. In this structure, CMOS is arranged in three-dimensional layers, and the layers are connected by metal wires.

The CMOS transistors are all prepared on large-area single-crystal semiconductors, and the first layer of CMOS transistors is prepared on bulk silicon, silicon-on-insulator (SOI), silicon germanium or strained silicon and other semiconductor films. The single crystal semiconductor thin film of the second layer and above the second layer includes silicon, silicon germanium, strained silicon and the like.

The multi-layer planar CMOS structure with more than or equal to 2 layers is characterized in that the insulating layer between the layers comprises any one of silicon dioxide, silicon nitride, aluminum nitride, aluminum oxide or diamond-like carbon.

The multilayer planar CMOS structure with multiple layers greater than or equal to 2 is characterized in that copper or tungsten is used for wiring between layers, and the copper wiring is isolated by a low dielectric constant (K) dielectric, and the uppermost ones are more The layer connection is isolated by an ultra-low dielectric constant medium (K<2, such as a polymer), and the rest is isolated by a general low dielectric constant medium (K is between 3 and 2, such as: porous silicon oxide, silicon oxycarbide, etc. ).

In the multi-layer planar CMOS structure with more than or equal to 2 layers, the CMOS on the same layer is still a conventional planar process. This structure can greatly improve the integration of CMOS devices without changing the existing semiconductor process line, and shorten the connection between devices. Each layer of CMOS technology proposed by the present invention is basically the same as the SOI CMOS technology, and is prepared on a single crystal semiconductor thin film substrate. The single crystal thin film substrate is realized by bonding and peeling technology. Its main process steps include: 1. Prepare a layer of CMOS device on bulk silicon or SOI substrate. 2. After the CMOS structure is formed on the bulk silicon or SOI substrate, the first layer is covered with an insulating layer, and the surface of the insulating layer is polished by CMP, and the substrate is combined with another single crystal embedded with a defect layer. Semiconductor substrates are bonded at room temperature. The defect buried layer can be a hydrogen injection layer, a boron-hydrogen co-injection layer, a hydrogen-helium co-injection layer, or a porous layer. After bonding, it is peeled off at a low temperature by heating or applying external force, and the single crystal semiconductor layer is transferred to the on the insulating substrate of the device. 3. Use CMP to polish the surface to remove surface impurities, and then prepare MOS devices on the second layer of SOI structure. 4. Etching lead holes to prepare interlayer connections such as W or copper. 5. Repeat steps 2-4 to prepare multi-layer CMOS. 6. Prepare the final multilayer connection. (see description of drawings and embodiments for details)

In the present invention, hydrogen, boron, and helium plasma in the defect buried layer are introduced by an ion implanter, and the position of the defect buried layer and the thickness of the top semiconductor are determined by the energy of the ion implanter. The doses of hydrogen ions and helium ions are (1-9)×10 ¹⁶ cm ^-2 , respectively, and the doses of boron ions are 5×10 ¹⁴ cm ^-2 to 5×10 ¹⁵ cm ^-2 . The embedding of the porous layer is to firstly prepare porous silicon by electrochemical method, and then epitaxially expand the single crystal semiconductor layer on the porous silicon substrate, and the porous silicon is buried under the single crystal semiconductor layer.

The defect layer in the present invention is porous silicon, and the epitaxial silicon and other single crystal semiconductor thin films are prepared on the porous silicon substrate by electrochemical method, and then the epitaxial wafer is bonded with the insulating layer substrate containing the device.

The single crystal semiconductor thin film of the second layer or more than the second layer in the present invention is formed by bonding and peeling. In order to strengthen the bonding strength at room temperature, the surface of the substrate is chemically or plasma treated before bonding, and the bond is peeled off. Afterwards, it is annealed for a long time below 400°C. The peeling is carried out by low-temperature heating or mechanical methods, and the peeling is carried out at the defect layer.

To sum up, the present invention proposes low-temperature bonding and low-temperature peeling techniques, to transfer a single crystal thin film to an insulating layer, and to prepare an active layer of a device on the single crystal thin film. The three-dimensional CMOS proposed by the present invention does not change the basic structure of CMOS, high-density integration can be realized by adopting conventional CMOS technology and equipment conditions, the process method is simple, and the length and layer number of metal interconnection lines can be reduced, and the speed of devices can be improved.

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional multilayer planar CMOS structure provided by the present invention. CMOS is prepared by a conventional and mature CMOS process, and is distributed on different layers, and the layers are connected by metal wires. 10 is the nth layer CMOS, 11 is the n+1th layer CMOS, 12 is the metal wiring, and 13 is the insulating medium for isolating the device.

FIG. 2 is a schematic diagram of a process flow of a two-layer CMOS structure. Where (A) is a semiconductor sheet into which a release layer 22 has been introduced, 21 is a semiconductor thin film to be transferred, and 23 is a semiconductor substrate. In (B), the semiconductor substrate in the figure (A) is bonded to another substrate containing the nth layer CMOS device, wherein 24 is the metal wiring of the nth layer CMOS, and 25 is covered on the nth layer CMOS insulating medium. In order to improve the bonding strength at low temperature, chemical treatment and plasma treatment are performed on the surfaces of the two substrates before bonding. Figure (C) is to heat-treat or apply mechanical force to the peeling layer in the bonded substrate pair shown in Figure (B), so that the bonding sheet is peeled off at the peeling layer at a low temperature. In this way, the semiconductor thin film 21 is transferred to the insulating layer 25 and becomes the substrate material of the n+1th layer CMOS. In order to improve the bonding strength, it is further annealed at 400°C. After CMP polishing is performed on the semiconductor layer 21, the structure shown in Figure (D) is obtained. Figure (E) shows the formation of p-well 26 and n-well 262 by ion implantation. In Figure (F), the n+1th layer of CMOS 27 is prepared using a conventional CMOS process. In figure (G), the connection 28 between the n+1th layer CMOS and the nth layer CMOS is prepared. In the figure (H), a layer of insulating medium 29 is covered on the n+1th layer of CMOS, and wiring 30 is prepared.

Figure 3 is a three-dimensional planar CMOS structure using copper wiring. 31 is the n-1th layer of insulating layer, 32 is the n-1th layer of copper wiring, 33 is the W connection between the n-th layer of CMOS and the n-1th layer of copper wiring, 34 is the nth layer of CMOS. 35 is the nth insulating layer, because this three-dimensional planar structure greatly reduces the distance between the interlayer wiring, therefore, the interlayer insulating medium such as 31 and 35 does not need a particularly low dielectric constant material, such as silicon oxycarbide and porous silicon dioxide, etc., for the top copper wiring 37, the insulating medium 38 used may be a material with a very low dielectric constant, such as a polymer.

Fig. 4 is the preparation process of the bubble-containing peeling layer in silicon.

FIG. 4A shows the implantation of hydrogen ions and boron ions into a silicon wafer 41 . The defective layer 42 shown in FIG. 4B is formed. After the substrate is bonded to the insulating substrate containing the device, the defect layer can be peeled off, so that the single crystal silicon film 43 is transferred to the insulating substrate containing the device. (as shown in Figure 2A-C)

FIG. 5 is a process for preparing a semiconductor substrate containing a bubble defect layer, wherein the upper part of the bubble defect layer is a non-silicon semiconductor film 52 .

FIG. 5A is an epitaxial semiconductor thin film 52 on a bulk silicon substrate 51;

In FIG. 5B , boron and hydrogen ions are implanted into the semiconductor layer, or the interface between the semiconductor layer and bulk silicon; the defect layer 53 shown in FIG. 5C is formed.

Fig. 6 is a preparation process of a semiconductor substrate containing a porous silicon defect layer.

61 in FIG. 6A is a heavily doped silicon wafer;

The silicon wafer 61 is placed in HF and alcohol solution, and the porous silicon 62 shown in FIG. 6B is formed by anodic oxidation;

6C is an epitaxial semiconductor thin film 63 on porous silicon, thus forming a semiconductor substrate containing a porous silicon layer. After the substrate is bonded to an insulating substrate containing a device, it can be peeled off at the defect layer, so that the semiconductor The layer is transferred to an insulating substrate containing the device. (as shown in Figure 2A-C)

Since the thermal conductivity of the insulating layer is generally much worse than that of silicon, in order to prevent the self-heating effect of the device caused by heat accumulation in the device area, a polycrystalline layer is introduced into the insulating layer as a heat dissipation layer, and the connection with the wiring is oxidized with RTA. FIG. 7 is a three-dimensional planar CMOS structure containing a polysilicon heat sink, where 71 is a polysilicon layer, and 72 is an insulating part between polysilicon and wiring.

Detailed ways

The following examples will help to understand the present invention, but do not limit the content of the present invention.

Example 1:

Three-dimensional planar CMOS is prepared by bonding and ion implantation stripping.

1. Implanting hydrogen ions with a dose of 5×10 ¹⁶ cm ^-2 and boron ions with a dose of 1×10 ¹⁵ cm ^-2 on a silicon wafer. (See Figure 2(A) and Figure 4)

2. Clean the n-th layer CMOS substrate and implant sheet covered with silicon oxide layer in adjusted RCA1 (ammonia, hydrogen peroxide and deionized water) and RCA2 (hydrochloric acid, hydrogen peroxide and deionized water), and then clean the two bonds Oxygen plasma activation is carried out on the combined surface. The conditions of oxygen plasma are: air pressure 15 mbar, plasma power 100 W, oxygen flow rate 80 sccm. After washing in deionized water and drying, the two substrates were face-to-face bonded at room temperature. (See Figure 2(B))

3. Anneal the bonded sheet at 300-400°C for 5 minutes, and the bonded sheet is peeled off at the hydrogen injection layer. To increase bond strength, anneal at 400°C for 4 hours. (See Figure 2(C))

4. Polish the stripped surface with CMP. (See Figure 2(D))

5. CMOS is prepared on the second layer of single crystal silicon, and the steps are the same as the SOI CMOS process. Including: oxidation, silicon nitride deposition, active area photolithography, silicon nitride etching, field implant photolithography, field implantation, field oxidation, silicon nitride removal, gate oxide growth, P channel threshold implantation , N-channel lithography, N-channel threshold implantation, polysilicon deposition and doping, lithographic gate and etching, P ⁺ source-drain lithography, P ⁺ source-drain implantation, N ⁺ source-drain lithography, N ⁺ source-drain implantation, Source and drain re-oxidation, dielectric deposition, contact hole lithography, contact hole opening, metallization, metallization lithography, metal wiring corrosion, alloy.

(See Figure 2(E-F))

6. Etch the lead hole between the two CMOS drains, fill it with tungsten, and remove the tungsten on the surface. (See Figure 2(G))

7. Use PECVD to cover the oxide layer on the CMOS, and use chemical mechanical polishing to planarize the surface. The root mean square roughness of the surface is less than 1nm. (See Figure 2(H))

8. Prepare interlayer connections and final connections.

Example 2:

Fabrication of 3D planar CMOS by transfer of porous silicon epitaxial layer

1. Prepare CMOS on SOI substrate, the specific steps are the same as SOI CMOS:

2. Use PECVD to cover the oxide layer on the CMOS, and use chemical mechanical polishing to planarize. The root mean square roughness of the surface is less than 1nm.

3. Prepare interlayer connections.

4. Use P-type, (100) crystal orientation, silicon wafer with a resistivity of 0.01-0.02Ω·cm, and then anodize it in a 1:1 HF/C ₂ H ₅ COOH solution without light. The current density was 5 mA/cm ² . In order to stabilize the porous silicon structure, it was pre-oxidized under an oxygen atmosphere at 400°C for 1 hour. Before epitaxy, the oxide layer on the surface of porous silicon was removed with HF dilute solution. (See Figure 6(AB))

5. Epitaxy of single crystal silicon on a porous silicon substrate. The vacuum degree of the ultra-high vacuum coating apparatus during epitaxy is 10 ^-9 mbar, the epitaxy rate is 0.02nm/S at the beginning of 10nm, and then 0.04nm/S, and the substrate temperature is 800°C. (See Figure 6(C))

6. Plasma treatment of CMOS substrate and epitaxial wafer covered with silicon oxide layer, then cleaning in adjusted RCA1 and RCA2, bonding in bonding machine.

7. Apply mechanical force at the porous layer of the bonding sheet, such as inserting a wedge or impacting with an ultra-fine high-pressure water column, so that the bonding sheet is peeled off at the porous layer. To increase bond strength, anneal at 400°C for 4 hours.

8. Polish the stripped surface with CMP.

9. CMOS is prepared on the second layer of single crystal silicon, and the steps are the same as the SOI CMOS process.

10. Etch the lead hole between the two CMOS drains, fill it with tungsten, and remove the tungsten on the surface.

11. Photolithographic aluminum lead holes, aluminum deposition.

12. Anti-engraved aluminum, alloyed.

Example 3:

A three-dimensional planar CMOS process for preparing copper wiring. (see Figure 3)

1. Prepare CMOS on SOI substrate, the specific steps are the same as SOI CMOS:

2. Use PECVD or LPCVD to cover the fluorine-containing silicon oxide layer on the CMOS, and use chemical mechanical polishing to planarize the surface. The root mean square roughness of the surface is less than 1nm.

3. Carve out the lead hole, fill in W, and then remove the W on the surface with CMP.

4. Prepare a Cu electrode on the W lead, then cover it with fluorine-containing silicon oxide low-k dielectric material, and polish it;

5. Prepare a Cu electrode on the low-k dielectric material and connect it to the underlying Cu electrode;

6. Cover with fluorine-containing silicon oxide low-k dielectric and polish it;

7. Implanting hydrogen ions with a dose of 5×10 ¹⁶ cm ^-2 and boron ions with a dose of 1×10 ¹⁵ cm ^-2 on the silicon wafer.

8. Plasma treatment of the CMOS substrate covered with fluorine-containing silicon oxide layer and the injection chip, and then cleaning in the adjusted RCA1 and RCA2, and then bonding in the bonding machine.

9. Anneal the bonded sheet at 300-400°C for 5 minutes, and the bonded sheet is peeled off at the hydrogen injection layer. To increase bond strength, anneal at 400°C for 4 hours.

10. CMP to smooth the stripped surface.

11. CMOS is prepared on the second layer of single crystal silicon, and the steps are the same as the SOI CMOS process.

12. Etch the lead hole between the two CMOS drains, fill it with tungsten, and remove the tungsten on the surface.

13. Shen is active in polymers with low k value, using Damascus process to prepare copper wiring

Example 4:

A process for preparing a three-dimensional planar CMOS with a polysilicon heat dissipation layer. (see Figure 7)

1. Prepare CMOS on SOI substrate, the specific steps are the same as SOI CMOS:

2. Use PECVD or LPCVD to cover the silicon oxide layer on the CMOS, and use chemical mechanical polishing to planarize the surface. The root mean square roughness of the surface is less than 1nm.

3. Carve out the lead hole, fill in W, and then remove the W on the surface with CMP.

4. Prepare a W electrode with a larger area on the W plug, then cover the silicon oxide dielectric material, and polish it;

5. Using PECVD or LPCVD to cover a polysilicon layer on silicon oxide;

6. Cover a thin silicon oxide layer on the polysilicon layer;

7. Carve out the lead hole with the W electrode below;

8. Use RTA to oxidize the polysilicon around the hole in an oxygen atmosphere;

9. Prepare the W electrode, which is connected to the lower W electrode on the one hand, and connected to the upper W electrode on the other hand;

10. Covering the silicon dioxide layer;

11. Implanting hydrogen ions with a dose of 5×10 ¹⁶ cm ^-2 and boron ions with a dose of 1×10 ¹⁵ cm ^-2 on the silicon wafer.

12. Plasma treatment of the CMOS substrate covered with a silicon oxide layer and the injection piece, and then cleaning in the adjusted RCA1 and RCA2, and then bonding in the bonding machine.

13. Anneal the bonding sheet at 300-400°C for 5 minutes, and the bonding sheet is peeled off at the hydrogen injection layer. To increase bond strength, anneal at 400°C for 4 hours.

14. CMP to smooth the stripped surface.

15. CMOS is prepared on the second layer of single crystal silicon, and the steps are the same as the SOI CMOS process.

16. Etch the lead hole between the two CMOS drains, fill it with tungsten, and remove the tungsten on the surface.

17. Lithographically etches aluminum lead holes, deposits aluminum, etches aluminum back, alloys, and prepares Al wiring.

Claims (10)

1. A three-dimensional complementary metal-oxide-semiconductor device structure, characterized in that it consists of a multi-layer planar structure with a number of layers greater than or equal to 2, in which CMOS is arranged in three-dimensional layers, and the layers are arranged by metal Wired connection. 2. The CMOS device structure according to claim 1, wherein the insulating layer between the layers is any one of silicon dioxide, silicon nitride, aluminum nitride, aluminum oxide or diamond-like carbon kind. 3. The three-dimensional complementary metal-oxide-semiconductor device structure according to claim 2, characterized in that a polysilicon layer is introduced into each insulating layer as a heat dissipation layer to reduce the self-heating effect of the device. 4. The three-dimensional complementary metal-oxide-semiconductor device structure according to claim 1, characterized in that the wiring between the layers is one of tungsten or copper, and the copper wiring is isolated by a low dielectric constant medium. 5. According to the three-dimensional complementary metal-oxide-semiconductor device structure according to claim 4, the uppermost multilayer wiring is isolated by a dielectric with a dielectric constant <2, and the rest are separated by a dielectric with a dielectric constant between 2 and 2. 3 Dielectric isolation with low dielectric constant. 6. The three-dimensional complementary metal oxide semiconductor device structure according to claim 1, characterized in that the first layer of complementary metal oxide semiconductor devices is made of one of bulk silicon, silicon on insulating layer, silicon germanium or strained silicon; The CMOS device of the second layer or above is fabricated in one of silicon-on-insulator, silicon-germanium-on-insulator, or strained silicon-on-insulator. 7. The method for preparing a three-dimensional complementary metal oxide semiconductor device structure according to claim 1, wherein the specific preparation steps include: (a) Prepare a layer of complementary metal oxide semiconductor devices on any substrate of bulk silicon, silicon on insulator, silicon germanium or strained silicon by conventional methods; (b) Cover the upper insulating layer after the formation of the first complementary metal oxide semiconductor device, use chemical mechanical polishing to polish the surface of the insulating layer, and then combine the substrate with another single crystal semiconductor substrate embedded with a defect layer The wafers are bonded at room temperature; after bonding, they are peeled off, and the single crystal semiconductor layer is transferred to the insulating substrate containing the device; (c) polishing the surface by a chemical mechanical polishing method to remove surface impurities, and then preparing a complementary metal oxide semiconductor device on the second layer; (d) Etching out lead holes to prepare tungsten or copper interlayer connections; (e) Steps (b), (c) and (d) are repeated to prepare a multilayer complementary metal oxide semiconductor device; (f) Prepare the final multilayer wiring. 8. The method for preparing a three-dimensional complementary metal oxide semiconductor device according to claim 7, wherein the defect layer is one of a hydrogen injection layer, a boron-hydrogen co-injection layer, a hydrogen-helium co-injection layer or porous silicon; wherein, (a) The hydrogen ion dose is (1~9)×10 ¹⁶ cm ^-2 ; (b) The dose of helium ions is (1~9)×10 ¹⁶ cm ^-2 ; (c) The dose of boron ions is 5×10 ¹⁴ cm ^-2 to 5×10 ¹⁵ cm ^-2 ; d The porous silicon buried layer is epitaxial silicon on a porous silicon substrate prepared by an electrochemical method, and the epitaxial wafer is bonded to the insulating layer substrate containing the device. 9. The method for preparing a CMOS device according to claim 7, wherein the method for peeling off the defect layer is one of heating or mechanical; the bonded sheet after peeling is annealed at 400° C. for more than 4 hours, Improve bond strength. 10. The preparation method according to claim 8, characterized in that monocrystalline silicon is epitaxially grown on a porous silicon substrate, the degree of vacuum is 10 ^-9 mbar, the epitaxy rate is 0.02nm/S at the beginning of 10nm, and then 0.04nm/S, The substrate temperature was 800°C.

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