CN102623406B - Method for producing two layers of semiconductor devices with half empty structure - Google Patents

Method for producing two layers of semiconductor devices with half empty structure Download PDF

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CN102623406B
CN102623406B CN201210090430.8A CN201210090430A CN102623406B CN 102623406 B CN102623406 B CN 102623406B CN 201210090430 A CN201210090430 A CN 201210090430A CN 102623406 B CN102623406 B CN 102623406B
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layer
silicon
upper strata
support sheet
amorphous carbon
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黄晓橹
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Shanghai Huali Microelectronics Corp
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Abstract

According to the invention, the methods of low-temperature bonding and low-temperature exfoliation are utilized to achieve the layer transfer of an upper semiconductor layer above a lower semiconductor device layer, then an upper semiconductor device is produced in the upper semiconductor layer, and finally, the processes for an upper contact hole and a lower contact hole are completed in one time to realize isolation in production of the upper and the lower layers of semiconductor devices. The method provided by the invention has the advantage of simple process. The integration level of the semiconductor devices is increased effectively. Additionally, a half empty isolation structure of an empty layer and the lower contact hole is produced between the upper and the lower layers of the semiconductor devices to effectively reduce the capacitance coupling effect between the upper and the lower layers of the semiconductor devices.

Description

With the preparation method of the two-layer semiconductor device of half empty structure
Technical field
The present invention relates to a kind of preparation method of semiconductor device, relate in particular to a kind of preparation method of the upper and lower two-layer semiconductor device with half empty isolation structure.
Background technology
SOI(Silicon On Insulator) because of its unique structure and a series of premium properties, can realize the insulation isolation of components and parts in integrated circuit manufacture, eliminate the parasitic latch-up in Bulk CMOS; Meanwhile, CMOS/SOI circuit also has the series of advantages such as parasitic capacitance is little, integrated level is high, speed is fast, low in energy consumption, working temperature is high (300 DEG C), anti-irradiation.Therefore, SOI material will be more hachure (0.1 μ is one of the main material of integrated circuit m), estimates will mainly use above-mentioned material in the time that integrated level reaches 1Gb use Φ 300mm silicon chip.In recent years, SOI Materials is rapid, more and more causes people's great attention, and is considered to most important silicon integrated circuit technology of 21st century.
At present, layer transfer technology is the mainstream technology of preparation SOI material, and in layer transfer technology, a thin surface silicon layer, after a silicon substrate is peeled off, is transferred on a silicon substrate after oxidation, forms a slice SOI material.Owing to being substrate preparation, in preparation technology, there is no the restriction of temperature, therefore, bonding and stripping process in preparation SOI silicon substrate mostly adopt high-temperature technology, and to increase bond strength, to make to peel off easier simultaneously.At present, business-like layer transfer technology mainly comprises smart peeling technology (Smart-Cut), epitaxial loayer transfer techniques (ELTRAN) and note oxygen bonding techniques (Simbond).
But the support chip in layer shifts is while being prepared with the device sheet of semiconductor device, due to the existence of semiconductor device in support chip and semiconductor metal alloy (as nickel silicon alloy, cobalt silicon alloy, tungsten silicon alloy, alusil alloy etc.), just can not adopt high temperature bonding and the high temperature lift-off technology of conventional SOI silicon substrate, and must adopt cryogenic technique (400 DEG C of General Requirements are following).
Chinese patent CN1610114A discloses a kind of three-dimensional complementary metal oxide semiconductor device (CMOS) structure and preparation method thereof, it adopts low-temperature bonding and low temperature lift-off technology, can realize the multiple-level stack of CMOS, improve device integration density, but there is following defect: need between layers to add layer of metal layer, its upper and lower two layer devices are connected with it by through hole; This has increased the complexity of technique.
Chinese patent CN100440513C discloses a kind of three-dimensional complementary metal oxide semiconductor (CMOS) device architecture and preparation method thereof, it adopts low-temperature bonding and low temperature lift-off technology, can realize the multiple-level stack of CMOS, improve device integration density, although it does not need to increase the articulamentum of layer of metal layer as upper and lower device layer between two-layer device layer, but it still needs to prepare connecting through hole between each layer device layer, as the connecting line of upper and lower two-layer device layer, this has increased the complexity of technique equally.
What above-mentioned two patented technologies realized is all multiple-level stacks of CMOS, and multiple-level stack must increase the parasitic capacitance between semiconductor device, thereby Circuit responce speed is restricted.
Summary of the invention
For the problems referred to above, the invention provides a kind of preparation method of the upper and lower two-layer semiconductor device with half empty structure.
A first aspect of the present invention is to provide a kind of preparation method of the two-layer semiconductor device with half empty structure, and step comprises:
Step 1, provides patterned lower layer support sheet (lower layer device), and in lower layer support sheet, the ILD layer of device is amorphous carbon layer (AC layer), on the ILD of lower layer support sheet layer, deposits silica film layer; Upper strata silicon is provided, and wherein, described upper strata silicon comprises boron-rich, hydrogen layer, and comprises and be positioned at surperficial silicon dioxide layer; The silicon dioxide layer of the silicon dioxide layer to upper strata silicon and lower layer support sheet carries out activation processing and hydrophilic treated, to increase the silanol key for the treatment of surface;
Step 2, is fitted in the silicon dioxide layer of upper strata silicon on lower layer support sheet surface silica dioxide layer after treatment, and by low-temperature bonding, upper strata silicon is fixed on to lower layer support sheet surface;
Step 3, by low temperature lift-off technology, peels off upper strata silicon from boron-rich, the fracture of hydrogen layer, part boron-rich, hydrogen layer below is connected as a single entity with lower layer support sheet surface bond;
Preferably, when in the less situation of upper strata silicon layer bonding segment thickness, in the part of upper strata silicon and lower layer support sheet bonding, carry out growing epitaxial silicon, increase the thickness of upper strata silicon;
Step 4 is prepared upper strata semiconductor device in the silicon of upper strata; On the upper strata semiconductor device obtaining, form upper strata ILD layer, then prepare upper strata contact hole and lower floor's contact hole.Upper strata contact hole and lower floor's contact hole can be disposable or successively form;
Step 5, then prepares amorphous carbon ashing through hole at upper layer device, and described amorphous carbon ashing through hole runs through the ILD layer of layer device to lower layer support sheet;
Step 6, carries out ashing processing by described amorphous carbon ashing through hole to the ILD layer in lower layer support sheet, forms cavity layer in the ILD position of lower layer support sheet;
Step 7, upwards deposits dielectric in the amorphous carbon ashing through hole in layer device, by the shutoff of amorphous carbon ashing through hole.
In a kind of preferred implementation of the present invention, described amorphous carbon ashing through hole is prepared above the sti structure of upper layer device, and amorphous carbon ashing through hole runs through the ILD layer of layer device and STI layer until the ILD layer of lower layer support sheet.
In another kind of preferred implementation of the present invention, described in step 7, dielectric is preferably SiO 2.
In another kind of preferred implementation of the present invention, upper layer device MOS district and lower layer device MOS district also do not line up, thereby are lower floor's device contacts hole slot milling.
In the above-mentioned preparation method of the present invention, described lower layer support sheet can be body silicon silicon chip, can be also soi wafer, or other semiconductor chip, as germanium wafer, germanium silicon chip, strain silicon chip etc.
Wherein, in order to ensure a layer transfer mass, must ensure the ILD of lower floor enough little surface roughness CMP after, preferably, can adopt FACMP(Fixed Abrasive CMP) processing, make surface roughness be less than 10nm.
Second aspect of the present invention is to provide two-layer semiconductor device prepared by a kind of said method, comprises lower layer device and upper layer device, and upper layer device and lower layer device are connected to a fixed by low-temperature bonding technology.
Wherein, in above-mentioned steps 4, epitaxial growth temperature is controlled at≤and 650 DEG C.
In order to ensure before lower floor's half cavity preparation that AC layer can ashing, in step 1, lower layer support sheet after AC layer deposition to thin layer SiO 2between having deposited, can not occur that dry method is removed photoresist and cineration technics, can only adopt wet processing.In addition, the EBR(Edge Bead Removal of deposition AC layer) must come than the EBR of deposition SiO2 layer large, to ensure that AC on wafer limit is by SiO 2wrap.
The present invention is by the method that adopts low-temperature bonding, low temperature to peel off, the layer of realizing the upper strata semiconductor layer in lower floor's semiconductor device layer shifts, then in the semiconductor layer of upper strata, prepare upper strata semiconductor device, last property completes upper strata contact hole and lower floor's contact hole technique, realize upper and lower two-layer semiconductor device isolation preparation method, technique is simple, has effectively improved the integrated level of semiconductor device.
The present invention is owing to only having upper and lower two-layer semiconductor device layer, and therefore upper strata contact hole and lower floor's contact hole can once complete, than existing multi-lager semiconductor technology, simply many in technique.Because contact hole technique had been prepared before the ashing of amorphous carbon ILD layer processed, lower floor's contact hole while is the use of the supporting construction between the upper and lower semiconductor device layer of conduct also.Like this, in levels semiconductor device layer, be prepared with half empty isolation structure of cavity layer+lower floor contact hole supporting construction, effectively reduce the capacitance coupling effect between upper and lower device layer.
Brief description of the drawings
Fig. 1 is in an embodiment of the present invention, lower layer support sheet and upper strata silicon structure schematic diagram;
Fig. 2 is attaching process schematic diagram in embodiment described in Fig. 1;
Fig. 3 is structural representation after low-temperature bonding in embodiment described in Fig. 1;
Fig. 4 be described in Fig. 1 in embodiment low temperature peel off rear structural representation;
Fig. 5 is structural representation after epitaxial growth in embodiment described in Fig. 1;
Fig. 6 prepares upper strata semiconductor device structure schematic diagram in embodiment described in Fig. 1;
Fig. 7 forms ILD layer structural representation in embodiment described in Fig. 1;
Fig. 8 prepares contact hole structure schematic diagram in embodiment described in Fig. 1;
Fig. 9 prepares amorphous carbon through-hole structure schematic diagram in embodiment described in Fig. 1;
Figure 10 be described in Fig. 1 in embodiment by the structural representation after the ashing of AC layer;
Figure 11 is the two-layer semiconductor device structure schematic diagram of preparing in above-described embodiment.
Embodiment
The invention provides a kind of preparation method of two-layer semiconductor device and semiconductor device prepared by described method, Fig. 1 ~ Figure 11 has provided the schematic flow sheet of preparing two-layer semiconductor device in one embodiment of the invention; With reference to the accompanying drawings, by specific embodiment, the present invention is described in detail and is described, so that better understand content of the present invention, but should be understood that, following embodiment does not limit the scope of the invention.
In the present embodiment, taking plane CMOS FET structure as example, but can be also various semiconductor device.
Step 1
With reference to Fig. 1, lower layer support sheet 1 is graphical, and support chip 1 selective body silicon silicon chip, can be also soi wafer, or other semiconductor chips be as germanium wafer, germanium silicon chip, strain silicon chip etc.
The ILD layer 11 of lower layer support sheet 1 is amorphous carbon layer 11, in order to ensure a layer transfer mass, must ensure the ILD of lower floor enough little surface roughness CMP after, employing FACMP(Fixed Abrasive CMP), make surface roughness be less than 10nm.
For the needs of follow-up bonding, stringer SiO on ILD layer 11 2layer 12.
In upper strata silicon 2, contain boron-rich, hydrogen layer 21, wherein for the part of lower layer support sheet 1 bonding be SiO 2layer 22.
Always there is oxide layer in silicon chip surface, some silica covalent bond in surperficial silicon dioxide molecules can rupture, and makes silicon atom form dangling bonds.The aobvious electropositive of silicon atom hanging, can regard silicon face one deck charge layer as.During through hydrophilic treated, silicon face absorption OH-group forms silanol key.Two silicon chips that form silanol keys near time, between silanol key, hydrone and silanol key, can attract each other by formation hydrogen bond.The laminating period of Here it is bonding.What silicon chip interface existed is (Si-OH) and hydrone.In the time that temperature raises, there is following reaction:
2SiOH→Si-O-Si+H 2O
Be that silanol key transforms to silicon oxygen bond.This reaction is reversible reaction, and temperature is higher, and the Direction of Reaction more carries out to the right.Here it is, and why high annealing can strengthen bond strength.Process annealing is exactly to require at lower temperature, and reaction can be carried out to the right more fully.This just has following two requirements: (1) silicon chip surface multiform of will trying one's best becomes silanol key, make silicon chip in the time of laminating in conjunction with closely and have enough reactants; (2) the process annealing time will be grown, and is beneficial to hydrone and escapes and spread, and reaction is constantly carried out to positive direction.For above second point, extend annealing time.And the first point requires silicon chip to have as far as possible many dangling bonds before hydrophilic treated, to adsorb a large amount of (OH) groups.Taking oxygen plasma Activiation method as example, it can have on oxide layer surface following reaction:
Si-O+O +→(Si) ++O 2
Thereby reach the object that forms a large amount of silicon dangling bonds, this is the main cause that process annealing can strengthen bonded interface intensity.
Therefore, first the silicon dioxide layer 22 of the bonding surface to lower layer support sheet 1 and upper strata silicon chip carries out activation processing (as chemistry or plasma treatment), hydrophilic treated, so that bonding face forms a large amount of silanol keys.
Step 2
With reference to Fig. 2, the SiO by the silicon dioxide layer of upper strata silicon 2 22 with lower layer support sheet 1 2layer 12 laminating (arrow is laminating direction), this step can at room temperature be carried out.
With reference to Fig. 3, low-temperature bonding, reinforces upper strata silicon 2 on lower layer support sheet 1.
This step can be carried out with reference to prior art.
Step 3
With reference to Fig. 4, by low-temperature bonding technology, upper strata silicon is ruptured from boron-rich, hydrogen layer, thereby boron-rich in figure, more than hydrogen layer part is peeled off, and lower part (bonding part) is bonded to and is integrated with lower layer support sheet.
This step can be carried out with reference to prior art.Also there is now several different methods, if dosage is 5E16cm -2to 9E16cm -2note hydrogen sheet or hydrogen helium note altogether sheet and can peel off 500 DEG C of left and right, and boron, hydrogen are noted altogether sheet exfoliation temperature and can be less than 400 DEG C.Even, bonding pad containing note hydrogen layer or porous silicon layer can just can at room temperature successfully be peeled off under mechanism, and these technology are all for the support chip in layer transfer is that while being prepared with the device sheet of semiconductor device, required low temperature is peeled off technical foundation is provided.
Low Temperature Solid-Phase (or liquid phase) growing epitaxial silicon, key and part form upper strata silicon layer 3, as the basis of preparation upper strata semiconductor device, as shown in Figure 5.This epitaxial growth steps is optional step, the upper strata silicon layer after bonding is enough thick, can omit.
Step 4
In the upper strata silicon layer 3 obtaining, prepare upper strata semiconductor device in step 4, as shown in Figure 6.
On the upper strata semiconductor device obtaining, deposit ILD layer 23, as shown in Figure 7, and prepare upper strata contact hole 20 and lower floor's contact hole 10 simultaneously, (in subsequent figures, omit contact hole) as shown in Figure 8.
In this step 5, can adjust upper strata device position, for example will between upper layer device MOS district and lower layer device MOS district, be offset certain distance, thereby be the reserved enough spaces of preparation lower floor contact hole.
Step 5
In upper layer device, prepare amorphous carbon ashing through hole 24, amorphous carbon ashing through hole 24 connects upper layer device until the ILD layer in lower layer device.Amorphous carbon ashing through hole can be through hole and the position that can arrive arbitrarily lower layer device ILD layer, is chosen in the preparation of layer device sti structure top in the present embodiment, amorphous carbon ashing through hole 24 is connected to upper layer device ILD layer and sti structure, as shown in Figure 9.
Step 6
With reference to Figure 10, by the ILD layer ashing in lower layer device, form cavity layer 15, preferably ashing completely of the ILD layer in lower layer device by amorphous carbon ashing through hole 24, but also allow a small amount of amorphous carbon of residue, as long as can form and the cavity layer of upper strata device isolation.Because contact hole technique had been prepared before the ashing of amorphous carbon ILD layer processed, lower floor's contact hole while is the use of the supporting construction between the upper and lower semiconductor device layer of conduct also.
Step 7
Above upper layer device, deposit dielectric (for example SiO 2), amorphous carbon through hole should be enough little, so that in dielectric deposition process, can not enter in the cavity layer forming in step 6; But the dielectric of deposition preferably can be packed in amorphous carbon ashing through hole, by the shutoff of amorphous carbon ashing through hole.
Because amorphous carbon ashing through hole in the present embodiment is in the preparation of the STI position of upper layer device, therefore, be positioned at the part of STI even without by shutoff completely, also can not impact device.
Finally remove unnecessary dielectric, obtain two-layer semiconductor device, as shown in figure 11.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the amendment done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.

Claims (6)

1. the preparation method with the two-layer semiconductor device of half empty structure, it is characterized in that, step comprises: step 1, provides patterned lower layer support sheet, in lower layer support sheet, the ILD layer of device is amorphous carbon layer, on the ILD of lower layer support sheet layer, deposits silica film layer; Upper strata silicon is provided, and wherein, described upper strata silicon comprises boron-rich, hydrogen layer, and comprises and be positioned at surperficial silicon dioxide layer; The silicon dioxide layer of the silicon dioxide layer to upper strata silicon and lower layer support sheet carries out activation processing and hydrophilic treated, to increase the silanol key for the treatment of surface; Step 2, is fitted in the silicon dioxide layer of upper strata silicon on lower layer support sheet surface silica dioxide layer after treatment, and by low-temperature bonding, upper strata silicon is fixed on to lower layer support sheet surface;
Step 3, by low temperature lift-off technology, peels off upper strata silicon from boron-rich, the fracture of hydrogen layer, part boron-rich, hydrogen layer below is connected as a single entity with lower layer support sheet surface bond;
Step 4 is prepared upper strata semiconductor device in the silicon of upper strata; On the upper strata semiconductor device obtaining, form upper strata ILD layer, then prepare upper strata contact hole and lower floor's contact hole,
Upper strata contact hole and lower floor's contact hole are disposable or successively form;
Step 5, then prepares amorphous carbon ashing through hole at upper layer device, and described amorphous carbon ashing through hole runs through the ILD layer of layer device to lower layer support sheet;
Step 6, carries out ashing processing by described amorphous carbon ashing through hole to the ILD layer in lower layer support sheet, forms cavity layer in the ILD position of lower layer support sheet;
Step 7, upwards deposits dielectric in the amorphous carbon ashing through hole in layer device, by the shutoff of amorphous carbon ashing through hole.
2. preparation method according to claim 1, is characterized in that, described amorphous carbon ashing through hole is prepared above the sti structure of upper layer device, and amorphous carbon ashing through hole runs through the ILD layer of layer device and STI layer until the ILD layer of lower layer support sheet.
3. preparation method according to claim 1, is characterized in that, dielectric described in step 7 is SiO 2.
4. preparation method according to claim 1, is characterized in that, also comprises: in the part of upper strata silicon and lower layer support sheet bonding, carry out growing epitaxial silicon after step 3; Epitaxial growth temperature is controlled at≤and 650 DEG C.
5. preparation method according to claim 1, is characterized in that, described lower layer support sheet is selected from body silicon silicon chip, soi wafer, germanium wafer, germanium silicon chip, strain silicon chip.
6. the two-layer semiconductor device that as claimed in claim 1 prepared by method.
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US6528388B2 (en) * 2000-02-21 2003-03-04 Rohm Co., Ltd. Method for manufacturing semiconductor device and ultrathin semiconductor device
US6821826B1 (en) * 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
CN1610113A (en) * 2004-10-15 2005-04-27 中国科学院上海微系统与信息技术研究所 Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof

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Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US6528388B2 (en) * 2000-02-21 2003-03-04 Rohm Co., Ltd. Method for manufacturing semiconductor device and ultrathin semiconductor device
US6821826B1 (en) * 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
CN1610113A (en) * 2004-10-15 2005-04-27 中国科学院上海微系统与信息技术研究所 Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof

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