CN100440513C - Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof - Google Patents
Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof Download PDFInfo
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- CN100440513C CN100440513C CNB2004100672170A CN200410067217A CN100440513C CN 100440513 C CN100440513 C CN 100440513C CN B2004100672170 A CNB2004100672170 A CN B2004100672170A CN 200410067217 A CN200410067217 A CN 200410067217A CN 100440513 C CN100440513 C CN 100440513C
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Abstract
The present invention relates to a three-dimensional complementary metal oxide semiconductor (CMOS) component structure and a preparation method thereof, which belongs to the technical field of microelectronics. The present invention is characterized in that a three-dimensional multilayer CMOS structure is provided, and layers are connected by connecting lines. The key point of preparing the structure is formed in the mode that a plurality of layers of monocrystal films which are separated by insulating layers can be prepared. The present invention provides a technique of low temperature bonding and low temperature stripping. The monocrystal films are diverted on the insulating layers, and component active layers are prepared on the monocrystal films. The three-dimensional CMOS provided by the present invention does not change a basic structure of the CMOS, and can realize high density integration by adopting conventional CMOS technique and device conditions. The present invention has simple technical methods, and can reduce the length and the layer number of the metal connecting lines. The present invention improves the component speed.
Description
Background technology
Integrated circuit (IC) industry is followed More (Moor) law at present, and the integrated level of device is increasing, and performance doubled the price drop by half in per 18 months.Mainly contain three kinds of methods that improve the device integrated level at present: the characteristic size, increase wafer area, the preparation three-dimensional structure device that reduce device.MOS (metal-oxide semiconductor (MOS)) integrated circuit develop rapidly over the years to 0.13 μ m and even 90nm, has brought earth-shaking variation to semiconductor technology from 0.25 μ m technological development.But will be faced with many new problems again along with device size reaches nanometer range, and can not meet the demands, must seek new medium with low dielectric constant material or the like as traditional exposure technique.The appearance of therefore new technical problem and high cost make will become more and more difficult from reducing the approach that device feature size improves the device integrated level.Though the technology of " from bottom to top " is also proposed at present, promptly from nano dot, nano wire even atom, molecule, the preparation nano-device, this technology is had got long long way to go from industry.The wafer technology develops into 12 inches from 8 inches, but the increase of wafer size can make its rate of finished products reduce.No matter reduce the characteristic size or the increase wafer area of device, every renewal once all needs more exchange device and processing line, and this equipment depreciation to semiconductor factory all causes certain pressure.
The three-dimension device structure just proposed as far back as the 1980s, and was applied in the technology of aspects such as memory, for example in order to increase capacity area electric capacity was prepared into flute profile; For the integrated level of the static random access memory (SRAM) that improves 6 transistor units will be wherein 2 transistor preparations all the other 4 transistorized above.Owing to be difficult on insulator, prepare monocrystalline silicon, 2 thin-film transistor preparations are on polycrystalline, and when 0.25 μ m technology, obtain bigger commercial profit, but because the existence of crystal boundary makes transistor channel carrier mobility and switch current ratio all lower, when the operating voltage commodity production that can not meet the demands, and stopped during less than 1.8V.So Lee proposes to adopt annealing process that amorphous silicon is converted into monocrystalline silicon, thus preparation monocrystal thin films transistor.(Ga Won Lee, the patent No.: US6,723,589 B2) though this method can improve the performance of thin-film transistor greatly, but still can not prepare large-area monocrystalline silicon.Proposition PMOS such as S.J.Abou-Samra overlay the three-dimensional MOS on the NMOS, its upper strata monocrystalline silicon layer adopts the method for epitaxial lateral overgrowth, this method can not obtain large-area monocrystalline silicon equally, and treatment temperature is higher, can only obtain two-layer MOS structure (S.J.Abou-Samra, et al., Proc.Of the 8
ThInternational Symposium on SOITechnology and Devices, Paris, France, September 1997, PP384-388).Also having a kind of method is the vertical CMOS structure, be about to the MOS structure and stand upside down, source and leakage are placed on upper-lower position, and this method can be decreased to the cellar area of CMOS original 1/4, but the technology of this structure is very complicated, and this structure exists parasitic capacitance (Lamb AC, Riley LS, Hall S, Kunz VD, de Groot CH, Ashburn P, ESSDERC 2001 conference proceedings p347;
Http:// drl.ee.ucla.edu).
In a word, from current 3D CMOS technique, except that special vertical CMOS, the material of preparation thin-film transistor or be polysilicon or be small size monocrystalline silicon.And the CMP technology and be widely used in the technical bonding of SOI and lift-off technology transfer to for large tracts of land monocrystalline silicon provide on the insulating substrate that contains device may.Because the existence of device layer and metal connecting line, K cryogenic treatment becomes a key issue.People's such as Drago Resnik result of study shows that chemically treated two wafer bondings of process are bond strength (Drago Resnik, et al., Sensors andActuators 80 (2000) 68-76) after 400 ℃ of annealing can reach capacity.In general, dosage is 6 * 10
16Cm
-2Notes hydrogen sheet about 500 ℃, produce and peel off, and the sample exfoliation temperature that boron, hydrogen are annotated altogether is less than 400 ℃ of (T.Hochbauer et al., Journal of Applied Physics, 86 (1999) 4176-4183; In many new, thesis for the doctorate, calendar year 2001).In fact, contain the bonding pad of annotating hydrogen layer or porous silicon layer and under mechanism, can successfully peel off (W.G.En, I.J.Malik, M.A.Bryan etal in room temperature, Proceedings 1998 IEEE International SOI Conference, Oct.1998:163).These research work provide technical foundation for low temperature thin film shifts.
Summary of the invention
The purpose of this invention is to provide density three-dimensional CMOS structure of a kind of suitable large-scale production and preparation method thereof.
The invention provides a kind of number of plies more than or equal to 2 the unilateral CMOS structure of multilayer.In this structure, CMOS is three-layer laminated arrangement, the layer with layer between be connected by metal connecting line.
Described CMOS transistor all prepares on the large tracts of land single crystal semiconductor, ground floor CMOS transistor or the preparation on the body silicon, the preparation on semiconductive thin films such as silicon on the insulating barrier (SOI), germanium silicon or strained silicon.The above single-crystal semiconductor thin film of the second layer and the second layer comprises silicon, germanium silicon, strained silicon etc.
Described multilayer is more than or equal to 2 multilayer planar CMOS structure, it is characterized in that layer with layer between insulating barrier comprise in silicon dioxide, silicon nitride, aluminium nitride, aluminium oxide or the diamond like carbon any one.
Described multilayer is more than or equal to 2 multilayer planar CMOS structure, it is characterized in that layer with layer between line with copper or tungsten, for copper connecting lines low-k (K) dielectric isolation, uppermost multilayer interconnection is by dielectric isolation (K＜2 of ultralow dielectric, as polymer), all the other dielectric isolation by general low-k (K is between 3 ~ 2, as: porous silica, silicon oxide carbide etc.).
Described multilayer is still conventional planar technique more than or equal to 2 multilayer planar CMOS structure with the CMOS on one deck.This structure can improve the integrated level of cmos device greatly on the basis that does not change existing semiconductor process line, shorten the line between the device.Each layer CMOS technology and SOI CMOS technology that the present invention proposes are basic identical, all prepare on the single-crystal semiconductor thin film substrate.And the monocrystal thin films substrate is realized by bonding and lift-off technology.Its main processing step comprises: 1, preparation one deck cmos device on body silicon or SOI substrate.2, in ground floor preparation after the CMOS structure on body silicon or the SOI substrate forms, insulating barrier coverings in is put down the surface of insulating layer throwing with CMP, with the single crystal semiconductor substrate of this substrate and another potting defectiveness layer bonding at room temperature.The defective buried regions can be to annotate that hydrogen layer, boron hydrogen are annotated layer altogether, hydrogen helium is annotated layer altogether, can be porous layer also, peels off at low temperatures by heating or the mode that applies external force behind the bonding, and single-crystal semiconductor layer is transferred on the insulating substrate that contains device.3, with CMP that the surface throwing is flat, remove surface impurity, then preparation MOS device on second layer soi structure.4, etch fairlead, interlayer connecting lines such as preparation W or copper.5, the step that repeats 2-4 can be prepared multi-layer C MOS.6, the last multilayer interconnection of preparation.(seeing description of drawings and embodiment for details)
Among the present invention, the hydrogen in the defective buried regions, boron, helium plasma are introduced by ion implantor, and the semi-conductive thickness of the position of defective buried regions and top layer is by the energy decision of ion implantor.The dosage of hydrogen ion and helium ion is respectively (1-9) * 10
16Cm
-2, the dosage of boron ion is 5 * 10
14Cm
-2～5 * 10
15Cm
-2Imbedding of porous layer is to adopt earlier electrochemical method to prepare porous silicon, below the epitaxy single-crystal semiconductor layer on the porous silicon substrate again, such single-crystal semiconductor layer with regard to potting porous silicon.
Defect layer of the present invention is a porous silicon, adopts on the porous silicon substrate of electrochemical production single-crystal semiconductor thin films such as epitaxial silicon, again with this epitaxial wafer and the insulating barrier substrate bonding that contains device.
Single-crystal semiconductor thin film more than the 2nd layer or the 2nd layer of the present invention is formed with peeling off by bonding, for adding the strong room temperature bond strength, before bonding substrate surface is carried out chemistry or plasma treatment, and bonding is peeled off the back at long term annealing below 400 ℃.Peel off with low-temperature heat or mechanical means and implement, peel off at the place at defect layer.
In sum, the present invention proposes the technology that low-temperature bonding and low temperature are peeled off, monocrystal thin films is transferred on the insulating barrier, and on this monocrystal thin films the fabricate devices active layer.The three-dimensional CMOS that the present invention proposes does not change the basic structure of CMOS, adopts conventional CMOS technology and appointed condition just can realize that high density is integrated, and process is simple, and can reduce the length and the number of plies of metal interconnecting wires, improves the speed of device.
Description of drawings
Fig. 1 is a three-dimensional multilayer planar CMOS structural representation provided by the invention.CMOS is formed by the mature C MOS prepared of routine, and is distributed on the different aspects, is connected by metal connecting line between each layer.Wherein 10 is n layer CMOS, and 11 is n+1 layer CMOS, the 12nd, and metal connecting line, the 13rd, the dielectric of isolating device.
Fig. 2 is the process flow diagram of two-layer CMOS structure.Wherein (A) is the semiconductor chip of having introduced peel ply 22, the 21st, and the semiconductive thin film that shift, the 23rd, Semiconductor substrate.(B) will scheme semiconductor chip in (A) in and another contains the substrate bonding of n layer cmos device, wherein 24 is metal connecting lines of n layer CMOS, the 25th, cover the dielectric on the n layer CMOS.In order to improve low-temperature bonding intensity, before bonding, earlier two substrate surfaces are carried out chemical treatment and plasma treatment.Figure (C) heat-treats or applies mechanical force with the peel ply of the bonding substrate centering shown in the figure (B), and bonding pad is peeled off at the peel ply place under the situation of low temperature.Semiconductive thin film 21 has just been transferred on the insulating barrier 25 like this, becomes the backing material of n+1 layer CMOS.Make a concerted effort in order to improve bonding junction, 400 ℃ of further annealing down.After semiconductor layer 21 carried out CMP polishing, obtain the structure shown in the figure (D).Figure (E) is that ion injects formation p trap 26 and n trap 262.Adopt conventional CMOS prepared n+1 layer CMOS 27 among the figure (F).It among the figure (G) line 28 between preparation n+1 layer CMOS and the n layer CMOS.Figure (H) covers one deck dielectric 29 on n+1 layer CMOS, and preparation line 30.
Fig. 3 is the three-dimensional planar CMOS structure that adopts copper connecting lines.31 is n-1 layer insulatings, and 32 is n-1 layer copper connecting lines, and 33 is the W lines between n layer CMOS and the n-1 layer copper connecting lines, and 34 is n layer CMOS.35 is n layer insulatings, because this three-dimensional planar structure has reduced the distance of interlayer connecting line greatly, therefore, the dielectric of interlayer is as 31 and 35 materials that do not need special low-k, as silicon oxide carbide and porous silica etc., for top layer copper connecting lines 37, the dielectric 38 of employing can be the material of utmost point low-k, as polymer.
Fig. 4 is the preparation technology who contains the bubble peel ply in the silicon.
Fig. 4 A is injected into hydrogen ion and boron ion in the silicon chip 41.Form the defect layer 42 shown in Fig. 4 B.This substrate with contain the insulating substrate bonding of device after, can produce at the defect layer place and peel off, thereby monocrystalline silicon thin film 43 is transferred to the insulating substrate that contains device.(shown in Fig. 2 A-C)
Fig. 5 is the preparation technology who contains the semiconductor chip of bubble defect layer, and wherein, air blister defect layer top is non-Si semiconductor film 52.
Fig. 5 A is an epitaxial semiconductor film 52 on body silicon substrate 51;
Fig. 5 B is injected into semiconductor layer with boron, hydrogen ion, or semiconductor layer and body silicon are at the interface; Form the defect layer 53 shown in Fig. 5 C.
Fig. 6 is the preparation technology who contains the semiconductor chip of porous silicon defect layer.
61 is heavy mixed silicon slices among Fig. 6 A;
Fig. 6 C is an epitaxial semiconductor film 63 on porous silicon, has so just formed the semiconductor chip that contains porous silicon layer, this substrate with contain the insulating substrate bonding of device after, can produce at the defect layer place and peel off, thereby semiconductor layer is transferred to the insulating substrate that contains device.(shown in Fig. 2 A-C)
Because the heat conductivility of insulating barrier is generally all very different than silicon, accumulate the self-heating effect that causes device in order to prevent heat at device region, in insulating barrier, introduce a polycrystal layer as heat dissipating layer, with the RTA oxidation of line junction.Fig. 7 contains the heat sink three-dimensional planar CMOS structure of polysilicon, and wherein 71 is polysilicon layers, and the 72nd, the insulated part between polysilicon and the line.
Embodiment
Following examples will help to understand the present invention, but not limit content of the present invention.
Embodiment 1:
Adopt bonding and ion to inject the method for peeling off and prepare three-dimensional planar CMOS.
1. implantation dosage is 5 * 10 on silicon chip
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion.(and Fig. 4) referring to Fig. 2 (A)
2. n layer CMOS substrate and the injection sheet that is coated with silicon oxide layer cleaned at the RCA1 (ammoniacal liquor, hydrogen peroxide and deionized water) and the RCA2 (hydrochloric acid, hydrogen peroxide and deionized water) that adjust, then oxygen plasma is carried out on two bonding pad surfaces and activate.The condition of oxygen plasma is: 15 millibars of air pressure, plasma power are 100W, and oxygen flow is 80sccm.After cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.(referring to Fig. 2 (B))
3. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.(referring to Fig. 2 (C))
4. stripper surface is thrown flat with CMP.(referring to Fig. 2 (D))
5. prepare CMOS on second layer monocrystalline silicon, its step is identical with SOI CMOS technology.Comprise: photoetching, place injection, place oxidation, silicon nitride removal, growth of gate oxide layer, the injection of P ditch threshold value, the photoetching of N ditch, the injection of N ditch threshold value, polysilicon deposit doping, photoetching grid and etching, P are injected in oxidation, silicon nitride deposition, active area photoetching, silicon nitride etch, place
+The source light leak is carved, P
+The source is leaked and is injected, N
+The source light leak is carved, N
+The source leak to be injected, the source leak reoxidize, dielectric deposition, contact hole photoetching, opening contact hole, metallization, metallization photoetching, metal line burn into alloy.
(referring to Fig. 2 (E-F))
6. etch the fairlead between the two CMOS drain electrode, insert tungsten after, the tungsten on surface is removed.(referring to Fig. 2 (G))
7. adopt PECVD capping oxidation on CMOS to carry out planarization with the method for chemico-mechanical polishing layer by layer, surperficial r.m.s. roughness is less than 1nm.(referring to Fig. 2 (H))
8. preparation interlayer connecting line and finally line.
Embodiment 2:
The method that adopts the porous epitaxial silicon layer to shift prepares three-dimensional planar CMOS
1. prepare CMOS on the SOI substrate, concrete steps are identical with SOI CMOS:
2. adopt PECVD capping oxidation on CMOS to carry out planarization with the method for chemico-mechanical polishing layer by layer, surperficial r.m.s. roughness is less than 1nm.
3. preparation interlayer connecting line.
4. adopting P type, (100) crystal orientation, resistivity is the silicon chip of 0.01-0.02 Ω cm, then at 1: 1 HF/C
2H
5Anodic oxidation under the condition of COOH solution, unglazed photograph, anodised current density are 5mA/cm
2For stablizing the pre-oxidation 1 hour under 400 ℃ oxygen atmosphere of porous silicon structure.Remove the porous silicon surface oxide layer with the HF weak solution before the extension.(referring to Fig. 6 (A-B))
5. epitaxial monocrystalline silicon on the porous silicon substrate.The vacuum degree of outer time-delay ultra high vacuum plated film instrument is 10
- 9Mbar, beginning 10nm extension speed is 0.02nm/S, is 0.04nm/S afterwards, underlayer temperature is 800 ℃.(referring to Fig. 6 (C))
6. CMOS substrate and the epitaxial wafer that is coated with silicon oxide layer carried out plasma treatment, after in RCA1 that adjusts and RCA2, cleaning then, bonding in the bonding machine.
7. apply mechanical force at bonding pad porous layer place,, bonding pad is peeled off at the porous layer place as inserting with wedge or the impact of ultra-fine water jets under high pressure.In order to improve bond strength, annealed 4 hours down at 400 ℃.
8. stripper surface is thrown flat with CMP.
9. prepare CMOS on second layer monocrystalline silicon, its step is identical with SOI CMOS technology.
10. etch the fairlead between the two CMOS drain electrode, insert tungsten after, the tungsten on surface is removed.
11. photoetching aluminum lead hole, deposit aluminium.
12. anti-carve aluminium, alloying.
Embodiment 3:
The three-dimensional planar CMOS technology of preparation copper connecting lines.(referring to Fig. 3)
1. prepare CMOS on the SOI substrate, concrete steps are identical with SOI CMOS:
2. adopt PECVD or LPCVD to cover siof layer on CMOS, carry out planarization with the method for chemico-mechanical polishing, surperficial r.m.s. roughness is less than 1nm.
3. carve fairlead, insert W, the W with the surface removes with CMP again.
4. preparation Cu electrode on the W lead-in wire covers fluorinated silicon oxide low k dielectric material again, throws flat;
5. on the low k dielectric material, prepare the Cu electrode, and link to each other with following Cu electrode;
6. cover the fluorinated silicon oxide low k dielectric, throw flat;
7. implantation dosage is 5 * 10 on silicon chip
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion.
8. CMOS substrate and the injection sheet that is coated with siof layer carried out plasma treatment, after in RCA1 that adjusts and RCA2, cleaning then, bonding in the bonding machine.
9. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.
10. stripper surface is thrown flat with CMP.
11. prepare CMOS on second layer monocrystalline silicon, its step is identical with SOI CMOS technology.
12. etch the fairlead between the two CMOS drain electrode, insert tungsten after, the tungsten on surface is removed.
13. the polymer of the extremely low k value of deposition adopts Damascus technics to prepare copper connecting lines
Embodiment 4:
Preparation contains the technology of the three-dimensional planar CMOS of polysilicon heat dissipating layer.(referring to Fig. 7)
1. prepare CMOS on the SOI substrate, concrete steps are identical with SOI CMOS:
2. adopt PECVD or LPCVD capping oxidation silicon layer on CMOS, carry out planarization with the method for chemico-mechanical polishing, surperficial r.m.s. roughness is less than 1nm.
3. carve fairlead, insert W, the W with the surface removes with CMP again.
4. prepare the area W electrode of some greatly on the W embolism, capping oxidation silicon dielectric material is thrown flat again;
5. adopt PECVD or LPCVD on silica, to cover one deck polysilicon layer;
6. on polysilicon layer, cover the skim silicon oxide layer again;
7. carve fairlead with following W electrode;
8. adopt RTA under oxygen atmosphere with the polysilicon oxidation around the hole;
9. preparation W electrode links to each other with following W electrode on the one hand, links to each other with top W on the other hand;
10. covering silicon dioxide layer;
11. implantation dosage is 5 * 10 on silicon chip
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion.
12. CMOS substrate and the injection sheet that is coated with silicon oxide layer carried out plasma treatment, after in RCA1 that adjusts and RCA2, cleaning then, bonding in the bonding machine.
13. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.
14. stripper surface is thrown flat with CMP.
15. prepare CMOS on second layer monocrystalline silicon, its step is identical with SOI CMOS technology.
16. etch the fairlead between the two CMOS drain electrode, insert tungsten after, the tungsten on surface is removed.
17. photoetching aluminum lead hole, deposit aluminium, and anti-carve aluminium, alloying is prepared the Al line.
Claims (3)
1, a kind of preparation method of three-dimensional complementary metal oxide semiconductor device structure is characterized in that preparation process is:
(1) on the SOI substrate, prepares CMOS;
(2) adopt PECVD or LPCVD capping oxidation silicon layer on CMOS, carry out planarization with the method for chemico-mechanical polishing;
(3) carve fairlead, insert W, the W with the surface removes with CMP again;
(4) prepare the W electrode on the W embolism, capping oxidation silicon dielectric material is thrown flat again;
(5) adopt PECVD or LPCVD on silica, to cover one deck polysilicon layer;
(6) on polysilicon layer, cover the skim silicon oxide layer again;
(7) carve fairlead with following W electrode;
(8) adopt RTA under oxygen atmosphere with the polysilicon oxidation around the hole;
(9) preparation W electrode links to each other with following W electrode on the one hand, links to each other with top W on the other hand;
(10) cover silicon dioxide layer;
(11) implantation dosage is 5 * 10 on silicon chip
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion;
(12) CMOS substrate and the injection sheet that is coated with silicon oxide layer carried out plasma treatment, after in RCA1 and RCA2, cleaning then, bonding in the bonding machine;
(13) bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place;
(14) stripper surface is thrown flat with CMP;
(15) on second layer monocrystalline silicon, prepare CMOS;
(16) etch fairlead between the two CMOS drain electrode, insert W after, the W on surface is removed;
(17) photoetching aluminum lead hole, deposit aluminium, and anti-carve aluminium, alloying is prepared the aluminium line.
2,, it is characterized in that the surperficial r.m.s. roughness after the planarization of usefulness cmp method is less than 1nm in the step (2) by the preparation method of the described three-dimensional complementary metal oxide semiconductor device structure of claim 1.
3,, it is characterized in that the condition that the bonding switch closes in the step (12) is to anneal 4 hours under 400 ℃ by the preparation method of the described three-dimensional complementary metal oxide semiconductor device structure of claim 1.
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| CN102610567A (en) * | 2012-03-31 | 2012-07-25 | 上海华力微电子有限公司 | Method for producing double-layer semiconductor device |
| CN102610572B (en) * | 2012-03-31 | 2014-03-12 | 上海华力微电子有限公司 | Preparation method of dual-layer semiconductor apparatus with semi-cavity structure |
| CN102623406B (en) * | 2012-03-31 | 2014-09-03 | 上海华力微电子有限公司 | Method for producing two layers of semiconductor devices with half empty structure |
| CN104347364A (en) * | 2014-09-23 | 2015-02-11 | 武汉新芯集成电路制造有限公司 | Preparation method of three-dimensional stacked device |
| CN109712961B (en) * | 2017-10-25 | 2021-11-02 | 上海新微技术研发中心有限公司 | Three-dimensional integrated circuit and method of manufacturing the same |
| CN109817536B (en) * | 2019-02-15 | 2021-03-30 | 长江存储科技有限责任公司 | Method for forming bonding structure |
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