CN109817536B - Method for forming bonding structure - Google Patents
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- CN109817536B CN109817536B CN201910116443.XA CN201910116443A CN109817536B CN 109817536 B CN109817536 B CN 109817536B CN 201910116443 A CN201910116443 A CN 201910116443A CN 109817536 B CN109817536 B CN 109817536B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
The invention relates to a forming method of a bonding structure, which comprises the following steps: providing a first substrate, wherein an electric contact part is formed in the first substrate, the first substrate is provided with a first surface and a second surface which are opposite, the surface of the electric contact part is flush with the first surface of the first substrate, the surface of the first substrate is bonded with a second substrate through a bonding medium layer, and a semiconductor device and an interlayer medium layer which covers the semiconductor device and the surface of the second substrate are formed on the surface of the other side, opposite to the bonding surface, of the second substrate; and forming a penetrating contact part penetrating through the interlayer dielectric layer, the second substrate and the bonding dielectric layer, wherein the penetrating contact part is electrically connected with the electric contact part.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a bonding structure.
Background
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed.
In a 3D NAND flash memory structure, including a memory array structure and a CMOS circuit structure located above the memory array structure, the memory array structure and the CMOS circuit structure are usually formed on two different wafers respectively, and then the CMOS circuit wafer is bonded above the memory array structure by hybrid bonding. And the metal through holes of the storage array structure are bonded and connected with the metal through holes in the CMOS circuit structure.
The hybrid bonding method requires strict alignment of two wafers, and the connection failure yield is reduced if the wafers are misaligned. And, since the memory array wafer has a complicated thin film stack structure. The problems of bubbles, peeling, even fragments and the like are easily caused in the bonding process of the CMOS circuit wafer and the storage array wafer, the quality of a contact interface of the wafer is extremely high, and the dislocation problem is easily caused by different deformation and stress between two sides.
How to improve the bonding quality between wafers is a problem to be solved urgently at present.
Disclosure of Invention
The invention aims to provide a method for forming a bonding structure, which improves the bonding quality.
The invention provides a forming method of a bonding structure, which comprises the following steps: providing a first substrate, wherein an electric contact part is formed in the first substrate, the first substrate is provided with a first surface and a second surface which are opposite, the surface of the electric contact part is flush with the first surface of the first substrate, the surface of the first substrate is bonded with a second substrate through a bonding medium layer, and a semiconductor device and an interlayer medium layer which covers the semiconductor device and the surface of the second substrate are formed on the surface of the other side, opposite to the bonding surface, of the second substrate; and forming a penetrating contact part penetrating through the interlayer dielectric layer, the second substrate and the bonding dielectric layer, wherein the penetrating contact part is electrically connected with the electric contact part.
Optionally, the method further includes: and forming an interconnection structure on the surface of the interlayer dielectric layer, wherein the interconnection structure is connected with the semiconductor device and the through contact part.
Optionally, the second substrate includes a single crystal semiconductor layer, and the bonding medium layer is located between the single crystal semiconductor layer and the first substrate.
Optionally, the bonding dielectric layer is a silicon oxide layer.
Optionally, the semiconductor device includes at least a MOS transistor.
Optionally, a storage structure is formed in the first substrate, and an electrical connection is formed between the electrical contact and the storage structure.
Optionally, the storage structure is a 3D NAND storage structure.
The technical scheme of the invention also provides a forming method of the bonding structure, which comprises the following steps: providing a first substrate having electrical contacts formed therein, the first substrate having opposing first and second surfaces, the electrical contact surfaces being flush with the first surface of the first substrate; providing a second base, wherein the second base comprises a device substrate, a semiconductor device formed on one side surface of the device substrate, an interlayer dielectric layer covering the surface of the device substrate and the semiconductor device, and a control substrate bonded on the surface of the interlayer dielectric layer; bonding the other side surface of the device substrate with the first surface of the first base through a bonding dielectric layer; and removing the control substrate.
Optionally, the method further includes: and forming a through contact part penetrating through the interlayer dielectric layer, the device substrate and the bonding dielectric layer, wherein the through contact part is electrically connected with the electric contact part.
Optionally, the method further includes: and forming an interconnection structure on the surface of the interlayer dielectric layer, wherein the interconnection structure is connected with the semiconductor device and the through contact part.
Optionally, the semiconductor device includes at least a MOS transistor.
Optionally, a storage structure is formed in the first substrate, and an electrical connection is formed between the electrical contact and the storage structure.
Optionally, the storage structure is a 3D NAND storage structure.
Optionally, after the bonding dielectric layer is formed on the other side surface of the device substrate, the bonding dielectric layer is bonded to the first surface of the first base.
Optionally, before the bonding dielectric layer is formed, thinning is performed on the other side surface of the device substrate.
Optionally, the method for forming the second substrate includes: providing a device substrate; forming a semiconductor device on one side surface of the device substrate; forming an interlayer dielectric layer covering the semiconductor device and the surface of the device substrate; and bonding the control substrate on the surface of the interlayer dielectric layer.
According to the forming method of the bonding structure, the first substrate and the second substrate are bonded through the bonding medium layer without performing mixed bonding, so that the requirement of wafer alignment is reduced, the bonding quality is improved, and the product yield is improved.
Further, in the method for forming a bonding structure of the present invention, after the first substrate and the second substrate are bonded, the electrical connection between the semiconductor devices in the first substrate and the second substrate is realized by forming the through contact portion penetrating the second substrate to the first substrate, and therefore, it is not necessary to consider the electrical connection performance of the bonding interface. Meanwhile, a bonding interconnection structure is not required to be formed on a bonding interface of the second substrate and the first substrate, so that a photomask for forming the bonding interconnection structure can be saved, and the process cost is reduced.
Drawings
Fig. 1 to 12 are schematic structural views illustrating a process of forming a bonding structure according to an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a method for forming a bonding structure according to the present invention with reference to the drawings.
Fig. 1 to 8 are schematic structural diagrams illustrating a forming process of a bonding structure according to an embodiment of the invention.
Referring to fig. 1, a first substrate 100 is provided, in which an electrical contact is formed in the first substrate 100, the first substrate has a first surface and a second surface opposite to the first surface, and the surface of the electrical contact is flush with the first surface of the first substrate.
The first substrate 100 may be a semiconductor substrate, and a dielectric layer, a semiconductor device formed in the dielectric layer, an interconnection structure, and the like may also be formed on the semiconductor substrate.
In this embodiment, the first substrate 100 includes: the device comprises a substrate 101, a device layer 102 formed on the substrate 101, and an interconnect layer 103 formed on the device layer 102. The substrate 101 may be a silicon wafer, and a memory structure including a plurality of memory strings is formed in the device layer 102; the interconnect layer 103 includes multiple dielectric layers and electrical contacts. In this embodiment, the electrical contact includes: a conductive plug 1031 connected to at least the memory string, a first metal layer 1032 located on top of the conductive plug 1031, a first conductive via 1033 located on top of the first metal layer 1032, and a second metal layer 1034 located on top of the first conductive via 1033, wherein a surface of the second metal layer 1034 is flush with the first surface of the first substrate.
The storage structure may be a 3D NAND storage structure. In other embodiments, other semiconductor devices may be formed within the device layer 102.
Referring to fig. 2, a second substrate 200 is provided, and a bonding dielectric layer 210 is formed on a surface of one side of the second substrate 200.
In some embodiments, the second substrate 200 includes a single-crystal semiconductor layer, and the bonding medium layer 210 is formed on a surface of the single-crystal semiconductor layer.
The second base 200 may be a semiconductor-on-insulator substrate, including: a bulk silicon layer 201, a silicon oxide layer 202 on one side surface of the bulk silicon layer 201, and a single crystal silicon layer 203 on the surface of the silicon oxide layer 202. The bonding medium layer 210 is formed on the surface of the single crystal silicon layer 203.
The bonding dielectric layer 210 may be formed using a chemical vapor deposition process or an oxidation process. In this embodiment, the bonding dielectric layer 210 is made of silicon oxide, and is formed by performing thermal oxidation or chemical vapor deposition on a furnace platform, so that the bonding dielectric layer 210 is formed on the surface of the single crystal silicon layer 203, and a similar silicon oxide layer 220 is formed on the other surface of the bulk silicon layer 201.
Referring to fig. 3, the second substrate 200 is bonded to the first surface of the first substrate 100 through the bonding dielectric layer 210.
During bonding, the surface of the second substrate 200 is the bonding dielectric layer 210, and the alignment problem during bonding with the first surface of the first substrate does not need to be considered, so that the bonding process is simple.
The bonding dielectric layer 210 may also serve as an isolation layer between the first substrate 100 and the second substrate 200 to ensure isolation performance and bonding effect.
Referring to fig. 4, the second substrate 200 is thinned to expose the surface of the single crystal silicon layer 203.
The second substrate 200 may be thinned by wet etching, chemical mechanical polishing, or the like until the single crystal silicon layer 203 is exposed.
Referring to fig. 5, a semiconductor device 502 is formed on the second surface of the second substrate.
The semiconductor device includes at least MOS transistors to form CMOS peripheral circuits for controlling semiconductor devices, such as memory structures, within the first substrate 100.
This embodiment includes forming shallow trench isolation structures 501 and semiconductor devices 502 within the single crystal silicon layer 203.
Referring to fig. 6, an interlayer dielectric layer 600 is formed to cover the surface of the single crystal silicon layer 203 and the semiconductor device 502, and the surface of the interlayer dielectric layer 600 is flat.
Depositing a dielectric material layer on the surface of the monocrystalline silicon layer 203 by using a chemical vapor deposition process, wherein the dielectric material layer is higher than the surface of the semiconductor device 502; the dielectric material layers are then planarized to form planar surface interlevel dielectric layers A.S. 600.
Referring to fig. 7, a through contact 701 penetrating the interlayer dielectric layer 600, the single crystal silicon layer 203 and the bonding dielectric layer 210 is formed, and the through contact 701 is electrically connected to an electrical contact in the first substrate 100.
In this embodiment, the bottom of the through contact 701 is located at least on a portion of the surface of the second metal layer 1034, and is connected to the semiconductor device in the device layer 102 through the electrical contact in the interconnect layer 103.
The method for forming the through contact 701 includes: etching the interlayer dielectric layer 600, the monocrystalline silicon layer 203 and the bonding dielectric layer 210 to the surface of the second metal layer 1034 in the first substrate 100 to form a through hole; the through via hole is filled with a conductive material and planarized to form the through contact 701.
In this embodiment, the plurality of conductive contacts 702 connecting the semiconductor device 502 are formed in the interlayer dielectric layer 600 at the same time as the through contact 701 is formed. In some embodiments, the plurality of conductive contacts 702 are connected to the source, drain, and gate of the MOS transistor, respectively.
Referring to fig. 8, an interconnection structure 800 is formed on the surface of the interlayer dielectric layer 600, and the interconnection structure 800 connects the semiconductor device 502 and the through contact 701.
The interconnect structure 800 is formed in a dielectric layer (not shown) on the surface of the interlayer dielectric layer 600, and includes: the conductive contact structure comprises a first metal layer 801 connected with the through contact part 701 and the conductive contact part 702, a first conductive through hole 802 located on the upper layer of the first metal layer 801 and connected with the first metal layer 801, a second metal layer 803 located on the upper layer of the first conductive through hole 802 and connected with the first conductive through hole 802, a top layer conductive through hole 804 located on the upper layer of the second metal layer 803 and connected with the second metal layer 803, and a top layer metal layer 805 located on the upper layer of the top layer conductive through hole 804 and connected with the top layer conductive through hole 804.
The interconnect structure 800 connects the through contact 701 and the conductive contact 701, thus enabling a connection between the semiconductor devices within the device layer 102 of the first substrate and the semiconductor devices 502 on the single crystal silicon layer 203.
In the forming method of the bonding structure, the first substrate and the second substrate are bonded and connected through the bonding medium layer, the alignment problem does not need to be considered, the product yield cannot be influenced even if the first substrate and the second substrate are slightly staggered, and the difficulty of bonding alignment is reduced.
Furthermore, after the second substrate is bonded with the first substrate, a semiconductor device is formed on the second substrate, and a through contact part penetrating through the second substrate to the surface of the first substrate is formed to connect the device in the first substrate out and form electrical connection with the semiconductor device on the second substrate, so that the electrical connection between the device in the first substrate and the device in the second substrate is realized without a bonding process, therefore, the requirement of bonding alignment can be reduced, and a bonding connection structure is not required to be formed on a bonding surface of the second substrate, so that a photomask for forming the bonding connection structure can be reduced, and the cost is reduced.
The invention further provides a forming method of the bonding structure.
Referring to fig. 9, a second substrate 900 is provided, the second substrate 900 including: the device comprises a device substrate 901, a semiconductor device 9011 formed on the surface of the device substrate 901, an interlayer dielectric layer 902 covering the surface of the device substrate 901 and the semiconductor device 9011, and a control substrate 903 bonded on the surface of the interlayer dielectric layer 902.
The method of forming the second substrate 900 includes: providing a device substrate 901; forming a semiconductor device 9011 on the surface of one side of the device substrate 901; forming an interlayer dielectric layer 902 covering the surfaces of the semiconductor device 9011 and the device substrate 901; and bonding the control substrate 903 on the surface of the interlayer dielectric layer 902.
The device substrate 901 is a semiconductor substrate, and in this embodiment, the device substrate is a monocrystalline silicon substrate. A semiconductor device 9011 is formed on the device substrate 901, and the semiconductor device 9011 at least includes a MOS transistor to form a CMOS circuit. The method further includes forming a shallow trench isolation structure 9012 in the device substrate 901, and using the shallow trench isolation structure as an isolation structure between adjacent MOS transistors.
The interlayer dielectric layer 902 may be made of insulating dielectric materials such as silicon oxide, boron-doped silicon oxide, and phosphorous-doped silicon oxide.
The control substrate 903 may also be a semiconductor substrate, such as a monocrystalline silicon substrate. And the surface of the interlayer dielectric layer 902 is bonded to serve as a base for subsequently bonding the second base 900 by turning over, so as to prevent the device substrate 901 and the interlayer dielectric layer 902 from being damaged.
Referring to fig. 10, the other side surface of the device substrate 901 is bonded to the first surface of the first base 100 through a bonding dielectric layer 1001.
After the bonding dielectric layer 1001 is formed on the other side surface of the device substrate 901, it is bonded to the first surface of the first base 100 (see fig. 1).
In this embodiment, before the bonding dielectric layer 1001 is formed, the other side surface of the device substrate 901 is thinned to reduce the thickness of the device substrate 901, so as to reduce the height of a through contact to be formed subsequently and reduce the difficulty in forming the through contact.
The device substrate 901 may be thinned by a wet etching process or a chemical mechanical polishing process.
Referring to fig. 11, the control substrate 903 is removed; and forming a through contact part 1101 penetrating through the interlayer dielectric layer 902, the device substrate 901 and the bonding dielectric layer 1001, wherein the through contact part 1101 is electrically connected with an electric contact part in the first base 100.
The control substrate 903 is removed by any one or more of grinding, stripping, wet etching and dry etching, and the surface of the interlayer dielectric layer 902 is exposed.
Etching the interlayer dielectric layer 902, the device substrate 901 and the bonding dielectric layer 1001 to form a through hole; the through via is filled with a conductive material and planarized to form a through contact 1101.
In this embodiment, the plurality of conductive contacts 1102 connected to the semiconductor device 9011 are formed in the interlayer dielectric layer 902 at the same time as the through contact 1101 is formed. In some embodiments, the conductive contacts 1102 are connected to a source, a drain, and a gate of a MOS transistor, respectively.
Referring to fig. 12, an interconnection structure 1200 is formed on the surface of the interlayer dielectric layer 902, and the interconnection structure 1200 connects the semiconductor device 9011 formed in the device substrate 901 and the through contact 1101.
The interconnect structure 1200 is formed in a dielectric layer (not shown) on the surface of the interlayer dielectric layer 902, and includes: a first metal layer 1201 connecting the through contact 1101 and the conductive contact 1102, a first conductive via 1202 located on top of the first metal layer 1201 and connected to the first metal layer 1201, a second metal layer 1203 located on top of the first conductive via 1202 and connected to the first conductive via 1202, a top conductive via 1204 located on top of the second metal layer 1203 and connected to the second metal layer 1203, and a top metal layer 1205 located on top of the top conductive via 1204 and connected to the top conductive via 1204.
The interconnect structure 1200 connects the through contact 1101 and the conductive contact 1102, thus enabling a connection between the semiconductor devices in the device layer 102 of the first base and the semiconductor devices 9011 on the device substrate 901.
The specific embodiment of the invention also provides a bonding structure.
Fig. 8 is a schematic diagram of a bonding structure according to an embodiment of the invention.
The bonding structure includes:
a first substrate 100 having electrical contacts formed within the first substrate 100, the first substrate having opposing first and second surfaces, the electrical contact surfaces being flush with the first surface of the first substrate.
The first substrate 100 may be a semiconductor substrate, and a dielectric layer, a semiconductor device formed in the dielectric layer, an interconnection structure, and the like may also be formed on the semiconductor substrate.
In this embodiment, the first substrate 100 includes: the device comprises a substrate 101, a device layer 102 formed on the substrate 101, and an interconnect layer 103 formed on the device layer 102. The substrate 101 may be a silicon wafer, and a memory structure including a plurality of memory strings is formed in the device layer 102; the interconnect layer 103 includes multiple dielectric layers and electrical contacts. In this embodiment, there is an electrical connection between the electrical contact and the storage structure, and the electrical contact includes: a conductive plug 1031 connected to at least the memory string, a first metal layer 1032 located on top of the conductive plug 1031, a first conductive via 1033 located on top of the first metal layer 1032, and a second metal layer 1034 located on top of the first conductive via 1033, wherein a surface of the second metal layer 1034 is flush with the first surface of the first substrate.
The storage structure may be a 3D NAND storage structure. In other embodiments, other semiconductor devices may be formed within the device layer 102.
And a second substrate comprising a single crystal semiconductor layer, wherein the second substrate is bonded and connected with the first surface of the first substrate 100 through a bonding medium layer 210. In this embodiment, the second substrate includes a single crystal silicon layer 203, and the bonding medium layer 210 is formed on a surface of the single crystal silicon layer 203. The bonding dielectric layer 210 is made of silicon oxide. During bonding, the surface of the second substrate 200 is the bonding dielectric layer 210, and the alignment problem during bonding with the first surface of the first substrate does not need to be considered, so that the bonding process is simple.
The bonding structure further includes: and a semiconductor device 502 formed on the second substrate surface. The semiconductor device 502 includes at least MOS transistors to form CMOS peripheral circuits for controlling semiconductor devices, such as memory structures, within the first substrate 100. This embodiment includes forming shallow trench isolation structures 501 and semiconductor devices 502 within the single crystal silicon layer 203.
The bonding structure further includes: further comprising: covering the second surface of the single crystal silicon layer 203 and the interlayer dielectric layer 600 of the semiconductor device 502, wherein the surface of the interlayer dielectric layer 600 is flat; a through contact 701 penetrating the interlayer dielectric layer 600, the single-crystal silicon layer 203, and the bonding dielectric layer 210, the through contact 701 being electrically connected to an electrical contact in the first substrate 100.
In this embodiment, the bottom of the through contact 701 is located at least on a portion of the surface of the second metal layer 1034, and is connected to the semiconductor device in the device layer 102 through the electrical contact in the interconnect layer 103.
In this embodiment, a plurality of conductive contacts 702 connected to the semiconductor device 502 are further formed in the interlayer dielectric layer 600 and located in the interlayer dielectric layer 600. In some embodiments, the plurality of conductive contacts 702 are connected to the source, drain, and gate of the MOS transistor, respectively.
The bonding structure further includes: an interconnect structure 800 located on the surface of the interlevel dielectric layer 600, the interconnect structure 800 connecting the semiconductor device 502 and the through contact 702. In this embodiment, the interconnect structure 800 includes: the conductive contact structure comprises a first metal layer 801 connected with the through contact part 701 and the conductive contact part 702, a first conductive through hole 802 located on the upper layer of the first metal layer 801 and connected with the first metal layer 801, a second metal layer 803 located on the upper layer of the first conductive through hole 802 and connected with the first conductive through hole 802, a top layer conductive through hole 804 located on the upper layer of the second metal layer 803 and connected with the second metal layer 803, and a top layer metal layer 805 located on the upper layer of the top layer conductive through hole 804 and connected with the top layer conductive through hole 804.
The interconnect structure 800 connects the through contact 701 and the conductive contact 701, thus enabling a connection between the semiconductor devices within the device layer 102 of the first substrate and the semiconductor devices 502 on the single crystal silicon layer 203.
In the bonding structure, the first substrate and the second substrate are bonded and connected through the bonding medium layer, the alignment problem does not need to be considered, the product yield cannot be influenced even if the first substrate and the second substrate are slightly staggered, and the difficulty of bonding alignment is reduced.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (15)
1. A method of forming a bonded structure, comprising:
providing a first substrate comprising: the semiconductor device comprises a substrate, a device layer formed on the substrate and an interconnection layer formed on the device layer, wherein the interconnection layer comprises a multi-layer dielectric layer and an electric contact part positioned in the multi-layer dielectric layer, the first base is provided with a first surface and a second surface which are opposite, the electric contact part is exposed on the first surface, and the surface of the electric contact part is flush with the first surface of the first base;
providing a second substrate, wherein a bonding dielectric layer is formed on one side surface of the second substrate;
bonding the second substrate with the first surface of the first substrate through the bonding medium layer to reduce the alignment requirement without forming a bonding connection structure on the bonding surface of the second substrate;
forming a semiconductor device and an interlayer dielectric layer covering the semiconductor device and the surface of the second substrate on the other side surface of the second substrate opposite to the bonding surface;
and forming a penetrating contact part penetrating through the interlayer dielectric layer, the second substrate and the bonding dielectric layer, wherein the penetrating contact part is electrically connected with the electric contact part.
2. The method of forming a bonded structure according to claim 1, further comprising: and forming an interconnection structure on the surface of the interlayer dielectric layer, wherein the interconnection structure is connected with the semiconductor device and the through contact part.
3. The method of claim 1, wherein the second substrate comprises a single crystal semiconductor layer, and the bonding medium layer is located between the single crystal semiconductor layer and the first substrate.
4. The method of claim 1, wherein the bonding dielectric layer is a silicon oxide layer.
5. The method of claim 1, wherein the semiconductor device comprises at least a MOS transistor.
6. The method as claimed in claim 1, wherein a storage structure is formed in the first substrate, and the electrical contact is electrically connected to the storage structure.
7. The method for forming the bonding structure according to claim 6, wherein the memory structure is a 3D NAND memory structure.
8. A method of forming a bonded structure, comprising:
providing a first substrate comprising: the semiconductor device comprises a substrate, a device layer formed on the substrate and an interconnection layer formed on the device layer, wherein the interconnection layer comprises a multi-layer dielectric layer and an electric contact part positioned in the multi-layer dielectric layer, the first base is provided with a first surface and a second surface which are opposite, the electric contact part is exposed on the first surface, and the surface of the electric contact part is flush with the first surface of the first base;
providing a second base, wherein the second base comprises a device substrate, a semiconductor device formed on one side surface of the device substrate, an interlayer dielectric layer covering the surface of the device substrate and the semiconductor device, and a control substrate bonded on the surface of the interlayer dielectric layer;
forming a bonding medium layer on the surface of the other side of the device substrate;
after the bonding medium layer is formed on the other side surface of the device substrate, the other side surface of the device substrate is bonded with the first surface of the first base through the bonding medium layer so as to reduce the alignment requirement, and a bonding connection structure is not required to be formed on the bonding surface of the second base;
and removing the control substrate.
9. The method of forming a bonded structure according to claim 8, further comprising: and forming a through contact part penetrating through the interlayer dielectric layer, the device substrate and the bonding dielectric layer, wherein the through contact part is electrically connected with the electric contact part.
10. The method of forming a bonded structure according to claim 9, further comprising: and forming an interconnection structure on the surface of the interlayer dielectric layer, wherein the interconnection structure is connected with the semiconductor device and the through contact part.
11. The method of claim 8, wherein the semiconductor device comprises at least a MOS transistor.
12. The method as claimed in claim 8, wherein a storage structure is formed in the first substrate, and the electrical contact is electrically connected to the storage structure.
13. The method for forming a bonding structure according to claim 12, wherein the memory structure is a 3D NAND memory structure.
14. The method of claim 8, wherein the other side surface of the device substrate is thinned before the bonding dielectric layer is formed.
15. The method of forming a bonding structure according to claim 8, wherein the method of forming the second substrate includes: providing a device substrate; forming a semiconductor device on one side surface of the device substrate; forming an interlayer dielectric layer covering the semiconductor device and the surface of the device substrate; and bonding the control substrate on the surface of the interlayer dielectric layer.
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| CN1610113A (en) * | 2004-10-15 | 2005-04-27 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof |
| CN104576417A (en) * | 2013-10-23 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Packaging structure and packaging method |
| CN109192721A (en) * | 2018-09-05 | 2019-01-11 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1610113A (en) * | 2004-10-15 | 2005-04-27 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof |
| CN104576417A (en) * | 2013-10-23 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Packaging structure and packaging method |
| CN109192721A (en) * | 2018-09-05 | 2019-01-11 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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