CN109817536A - The forming method of bonding structure - Google Patents
The forming method of bonding structure Download PDFInfo
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- CN109817536A CN109817536A CN201910116443.XA CN201910116443A CN109817536A CN 109817536 A CN109817536 A CN 109817536A CN 201910116443 A CN201910116443 A CN 201910116443A CN 109817536 A CN109817536 A CN 109817536A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
The present invention relates to a kind of forming methods of bonding structure, it include: that the first substrate is provided, electrical contacts are formed in first substrate, first substrate has opposite first surface and second surface, the electrical contacts surface is flushed with the first surface of first substrate, first substrate surface is bonded with one second substrate by a bonding medium layer, and the second substrate another side surface opposite with bonding face is formed with the interlayer dielectric layer of semiconductor devices and the covering semiconductor devices and the second substrate surface；The contact portion that runs through through the interlayer dielectric layer, second substrate and the bonding medium layer is formed, it is described to be electrically connected through contact portion with the electrical contacts.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of forming methods of bonding structure.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
CMOS electricity in 3D NAND flash memory structure, including memory array structure and above memory array structure
Line structure, the storage array knot and cmos circuit structure are usually respectively formed on two different wafers, then by mixed
Bonding pattern is closed, by cmos circuit wafer bonding to storage permutation superstructure.The metal throuth hole and CMOS of memory array structure
Metal throuth hole in circuit structure is bonded connection.
Hybrid bonded mode needs two wafers to be strictly aligned, and will lead to the reduction of connection failure yield once having dislocation.And
And since storage array wafer has complicated pellicular cascade structure.Cmos circuit wafer and storage array wafer bonding process
In be also easy to occur bubble, removing even fragmentation the problems such as, have high requirement, both sides for the contact interface quality of wafer
Between deformation be easy to cause problem of misalignment with stress difference.
The bonding quality between wafer how is improved, is current urgent problem to be solved.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of forming methods of bonding structure, improve bonding quality.
The present invention provides a kind of forming method of bonding structure, comprising: provides the first substrate, is formed in first substrate
There are an electrical contacts, first substrate has an opposite first surface and second surface, the electrical contacts surface and described the
The first surface of one substrate flushes, and first substrate surface is bonded with one second substrate by a bonding medium layer, and described
The two substrates another side surface opposite with bonding face is formed with semiconductor devices and the covering semiconductor devices and the second base
The interlayer dielectric layer of bottom surface；Form running through through the interlayer dielectric layer, second substrate and the bonding medium layer
Contact portion, it is described to be electrically connected through contact portion with the electrical contacts.
Optionally, further includes: form interconnection structure, the interconnection structure connection described half in the inter-level dielectric layer surface
Conductor device and it is described run through contact portion.
Optionally, second substrate includes a single-crystal semiconductor layer, and the bonding medium layer, which is located at the monocrystalline, partly leads
Between body layer and first substrate.
Optionally, the bonding medium layer is silicon oxide layer.
Optionally, the semiconductor devices includes at least MOS transistor.
Optionally, it is formed with storage organization in first substrate, had between the electrical contacts and the storage organization
There is electrical connection.
Optionally, the storage organization is 3D NAND storage organization.
Technical solution of the present invention also provides a kind of forming method of bonding structure, comprising: the first substrate is provided, described the
Electrical contacts are formed in one substrate, first substrate has opposite first surface and second surface, the electrical contacts
Surface is flushed with the first surface of first substrate；The second substrate is provided, second substrate includes device substrate, is formed in
The semiconductor devices of one side surface of device substrate, interlayer Jie for covering the device substrate surface and the semiconductor devices
Matter layer, the control substrate for being bonded to the inter-level dielectric layer surface；By a bonding medium layer, by the another of the device substrate
Side surface is bonded with the first surface of first substrate；Remove the control substrate.
Optionally, further includes: formed and connect through running through for the interlayer dielectric layer, device substrate and the bonding medium layer
Contact portion, it is described to be electrically connected through contact portion with the electrical contacts.
Optionally, further includes: form interconnection structure, the interconnection structure connection described half in the inter-level dielectric layer surface
Conductor device and it is described run through contact portion.
Optionally, the semiconductor devices includes at least MOS transistor.
Optionally, it is formed with storage organization in first substrate, had between the electrical contacts and the storage organization
There is electrical connection.
Optionally, the storage organization is 3D NAND storage organization.
Optionally, after another side surface of the device substrate forms the bonding medium layer, then with first base
The first surface at bottom is bonded.
Optionally, before forming the bonding medium layer, another side surface of the device substrate is carried out place is thinned
Reason.
Optionally, the forming method of second substrate includes: to provide a device substrate；In the side of the device substrate
Surface forms semiconductor devices；Form the interlayer dielectric layer for covering the semiconductor devices and the device substrate surface；Institute
It states and controls substrate described in interlayer dielectric layer surface bond.
First substrate and the second substrate are carried out key by a bonding medium layer by the forming method of bonding structure of the invention
It closes, it is hybrid bonded without carrying out, to reduce the requirement of wafer alignment, to improve bonding quality, improve product yield.
Further, in the forming method of bonding structure of the invention, after the first substrate and the bonding of the second substrate, pass through
It is formed and runs through contact portion through second substrate to the first substrate, realize that first substrate and second intrabasement is partly led
Electrical connection between body device, there is no need to consider bonded interface electrical connection properties.Meanwhile without the second substrate and first again
Bonding interconnection structure is formed on the bonded interface of substrate, so as to save the light shield to form bonding interconnection structure, reduces technique
Cost.
Detailed description of the invention
Fig. 1 to Figure 12 is the structural schematic diagram of the forming process of the bonding structure of the specific embodiment of the invention.
Specific embodiment
It elaborates with reference to the accompanying drawing to the specific embodiment of the forming method of bonding structure provided by the invention.
Fig. 1 to Fig. 8 is please referred to, is the structural representation of the forming process of the bonding structure of the embodiment of the invention
Figure.
Referring to FIG. 1, providing the first substrate 100, electrical contacts, first base are formed in first substrate 100
Bottom has opposite first surface and second surface, and the electrical contacts surface is flushed with the first surface of first substrate.
First substrate 100 can be semiconductor substrate, can also be formed with dielectric layer in the semiconductor substrate, with
And it is formed in semiconductor devices and interconnection structure etc. in the dielectric layer.
The device that in the specific embodiment, first substrate 100 includes: substrate 101, is formed on the substrate 101
Part layer 102 and the interconnection layer 103 being formed on the device layer 102.The substrate 101 can be Silicon Wafer, the device
Storage organization, including multiple storage strings are formed in layer 102；The interconnection layer 103 includes multilayer dielectric layer and electrical contacts.
In the specific embodiment, the electrical contacts include: the conductive plunger 1031 for being at least connected with the storage string, lead positioned at described
The first metal layer 1032 on 1031 upper layer of electric plug, positioned at 1032 upper layer of the first metal layer the first conductive through hole 1033 with
And the second metal layer 1034 positioned at 1033 upper layer of the first conductive through hole, the surface of the second metal layer 1034 with it is described
The first surface of first substrate flushes.
The storage organization can be 3D NAND storage organization.In other specific embodiments, the device layer 102
It is interior to be formed with other semiconductor devices.
Referring to FIG. 2, providing the second substrate 200, a side surface of second substrate 200 is formed with bonding medium layer
210。
In some embodiments, second substrate 200 includes a single-crystal semiconductor layer, the bonding medium layer
210 are formed in the single crystal semiconductor layer surface.
Second substrate 200 can be semiconductor-on-insulator substrate, comprising: body silicon layer 201 is located at the body silicon layer
The silicon oxide layer 202 of 201 1 side surfaces and monocrystalline silicon layer 203 positioned at 202 surface of silicon oxide layer.The bonding medium layer
210 are formed in 203 surface of monocrystalline silicon layer.
The bonding medium layer 210 can be formed using chemical vapor deposition process or oxidation technology.The specific embodiment party
In formula, the material of the bonding medium layer 210 is silica, carries out thermal oxide or chemical vapor deposition process using boiler tube board
It is formed, therefore, not only can form the bonding medium layer 210 on 203 surface of monocrystalline silicon layer, it can also be in the body silicon layer
201 another side surface formed one just as silicon oxide layer 220.
Referring to FIG. 3, second substrate 200 is passed through the bonding medium layer 210 and first substrate 100 the
One surface bond.
When due to bonding, 200 surface of the second substrate is bonding medium layer 210, without considering the with the first substrate
Alignment issues when one surface bond, therefore, bonding process is relatively simple.
The bonding medium layer 210 is also used as the separation layer between the first substrate 100 and the second substrate 200, with true
Protect isolation performance and bonding effect.
Referring to FIG. 4, second substrate 200 is thinned, the surface of the monocrystalline silicon layer 203 is exposed.
Can by techniques such as wet etching, chemical mechanical grindings, second substrate 200 is carried out it is thinned, until sudden and violent
Expose the monocrystalline silicon layer 203.
Referring to FIG. 5, the second surface in second substrate forms semiconductor devices 502.
The semiconductor devices includes at least MOS transistor, to form CMOS peripheral circuit, for controlling first base
Semiconductor devices in bottom 100, such as memory construction.
In the specific embodiment, including fleet plough groove isolation structure 501 is formed in the monocrystalline silicon layer 203 and is partly led
Body device 502.
Referring to FIG. 6, forming the interlayer dielectric layer for covering 203 surface of monocrystalline silicon layer and the semiconductor devices 502
600, the surface of the interlayer dielectric layer 600 is flat.
Using chemical vapor deposition process in the 203 surface deposits dielectric materials layer of monocrystalline silicon layer, the dielectric material
Layer is higher than the surface of the semiconductor devices 502；Then the layer of dielectric material is planarized, forms the flat layer in surface
Between Jie Zhi Ceng Eng 600.
Run through the interlayer dielectric layer 600, the monocrystalline silicon layer 203 and the bonding medium layer referring to FIG. 7, being formed
210 run through contact portion 701, described to be electrically connected with the electrical contacts in first substrate 100 through contact portion 701.
It is described to be located at least in 1034 surface of part second metal layer through 701 bottom of contact portion in the specific embodiment,
It is connect by the electrical contacts in the interconnection layer 103 with the semiconductor devices in the device layer 102.
The forming method through contact portion 701 include: the etching interlayer dielectric layer 600, monocrystalline silicon layer 203 and
1034 surface of second metal layer in bonding medium layer 210 to first substrate 100 forms and runs through through-hole；Run through described
Conductive material is filled in through-hole, and is planarized, and is formed described through contact portion 701.
In the specific embodiment, formed it is described run through contact portion 701 while, also formed and be located at the inter-level dielectric
Multiple electrically conducting contacts 702 of the connection semiconductor devices 502 in layer 600.In some embodiments, described more
A electrically conducting contact 702 is separately connected source electrode, drain electrode and the grid of MOS transistor.
Referring to FIG. 8, forming interconnection structure 800 on 600 surface of interlayer dielectric layer, the interconnection structure 800 is connected
The semiconductor devices 502 and it is described run through contact portion 701.
The interconnection structure 800 is formed in the dielectric layer (not shown) on 600 surface of interlayer dielectric layer, packet
Include: connection is described to run through contact portion 701, the first metal layer 801 of the electrically conducting contact 702, positioned at the first metal layer
First conductive through hole 802 of 801 upper layers and the connection the first metal layer 801, be located at 802 upper layer of the first conductive through hole and
The second metal layer 803 of first conductive through hole 802 is connected, 803 upper layer of second metal layer and connection described the are located at
The top layer conductive through-hole 804 of two metal layers 803, is located at 804 upper layer of top layer conductive through-hole and the connection top layer conductive is logical
The top layer metallic layer 805 in hole 804.
The interconnection structure 800 runs through contact portion 701 and the electrically conducting contact 701 described in connecting, therefore, described in realization
The company between the semiconductor devices 502 on semiconductor devices and the monocrystalline silicon layer 203 in the device layer 102 of first substrate
It connects.
In the forming method of above-mentioned bonding structure, connected between the first substrate and the second substrate by the bonding of bonding medium layer
It connects, without considering alignment issues, slightly misplaces even if having, product yield will not be influenced, reduce the difficulty of bonding alignment.
Further, it is bonded in the second substrate with the first substrate and then forms semiconductor devices in the second substrate, and
Run through contact portion through second substrate to the first substrate surface by being formed, the first intrabasement device is connected, with
Semiconductor devices in second substrate forms electrical connection, without being realized in the first substrate and the second substrate by bonding technology
Therefore the electrical connection of device can reduce the requirement of bonding alignment, and no longer need to form bonding on the bonding face of the second substrate and connect
Binding structure reduces cost so as to reduce the light shield to form the bonding connection structure.
A specific embodiment of the invention also provides a kind of forming method of bonding structure.
Referring to FIG. 9, providing the second substrate 900, second substrate 900 includes: device substrate 901, the device
901 surface of substrate is formed with semiconductor devices 9011, covers 901 surface of device substrate and the semiconductor devices 9011
Interlayer dielectric layer 902, the control substrate 903 for being bonded to 902 surface of interlayer dielectric layer.
The forming method of second substrate 900 includes: to provide a device substrate 901；The one of the device substrate 901
Side surface forms semiconductor devices 9011；Form the layer for covering the semiconductor devices 9011 and 901 surface of the device substrate
Between dielectric layer 902；Substrate 903 is controlled described in 902 surface bond of interlayer dielectric layer.
The device substrate 901 is semiconductor substrate, and in this specific embodiment, the device substrate is monocrystalline silicon lining
Bottom.Semiconductor devices 9011 is formed in the device substrate 901, the semiconductor devices 9011 includes at least MOS transistor,
Form cmos circuit.It further include the formation fleet plough groove isolation structure 9012 in the device substrate 901, as adjacent mos crystal
Isolation structure between pipe.
The material of the interlayer dielectric layer 902 can be the dielectrics materials such as silica, boron-doping silica, p-doped silica
Material.
The control substrate 903 or semiconductor substrate, such as monocrystalline substrate.It is bonded to the interlayer dielectric layer
902 surfaces, substrate when as the subsequent bonding by 900 turn-over of the second substrate, in order to avoid damage the device substrate 901 and interlayer Jie
Matter layer 902.
Referring to FIG. 10, by a bonding medium layer 1001, by another side surface of the device substrate 901 and described the
The first surface of one substrate 100 is bonded.
After another side surface of the device substrate 901 forms the bonding medium layer 1001, then with first base
The first surface at bottom 100 (please referring to Fig. 1) is bonded.
In the specific embodiment, before forming the bonding medium layer 1001, to the another of the device substrate 901
Side surface carries out reduction processing, to reduce the thickness of the device substrate 901, to reduce subsequent to be formed through contact portion
Height, reduce the formation difficulty for running through contact portion.
The device substrate 901 can be subtracted by modes such as wet-etching technology or chemical mechanical milling tech
It is thin.
Figure 11 is please referred to, the control substrate 903 is removed；It is formed and runs through the interlayer dielectric layer 902, device substrate 901
It is described in contact portion 1101 and first substrate 100 with the bonding medium layer 1001 through contact portion 1101
Electrical contacts electrical connection.
The control lining is removed by any one or a few mode in grinding, removing, wet etching or dry etching
Bottom 903 exposes 902 surface of interlayer dielectric layer.
The interlayer dielectric layer 902, device substrate 901 and bonding medium layer 1001 are etched, is formed and runs through through-hole；Institute
It states the filling conductive material in through-hole and is planarized, formed and run through contact portion 1101.
In the specific embodiment, formed it is described run through contact portion 1101 while, also formed and be located at the interlayer and be situated between
Multiple electrically conducting contacts 1102 of the connection semiconductor devices 9011 in matter layer 902.In some embodiments, institute
State source electrode, drain electrode and grid that multiple electrically conducting contacts 1102 are separately connected MOS transistor.
Figure 12 is please referred to, forms interconnection structure 1200 on 902 surface of interlayer dielectric layer, the interconnection structure 1200 connects
Connect the semiconductor devices 9011 formed in the device substrate 901 and described through contact portion 1101.
The interconnection structure 1200 is formed in the dielectric layer (not shown) on 902 surface of interlayer dielectric layer, packet
Include: connection is described to run through contact portion 1101, the first metal layer 1201 of the electrically conducting contact 1102, positioned at first metal
First conductive through hole 1202 of 1201 upper layer of layer and the connection the first metal layer 1201 is located at first conductive through hole 1202
The second metal layer 1203 of upper layer and connection first conductive through hole 1202, is located at 1203 upper layer of second metal layer and company
The top layer conductive through-hole 1204 of the second metal layer 1203 is connect, is located at described in 1204 upper layer of top layer conductive through-hole and connection
The top layer metallic layer 1205 of top layer conductive through-hole 1204.
The interconnection structure 1200 runs through contact portion 1101 and the electrically conducting contact 1102 described in connecting, and therefore, realizes
Between the semiconductor devices 9011 on semiconductor devices and the device substrate 901 in the device layer 102 of first substrate
Connection.
A specific embodiment of the invention also provides a kind of bonding structure.
Referring to FIG. 8, the schematic diagram of the bonding structure for the embodiment of the invention.
The bonding structure includes:
First substrate 100, is formed with electrical contacts in first substrate 100, and first substrate has opposite the
One surface and second surface, the electrical contacts surface are flushed with the first surface of first substrate.
First substrate 100 can be semiconductor substrate, can also be formed with dielectric layer in the semiconductor substrate, with
And it is formed in semiconductor devices and interconnection structure etc. in the dielectric layer.
The device that in the specific embodiment, first substrate 100 includes: substrate 101, is formed on the substrate 101
Part layer 102 and the interconnection layer 103 being formed on the device layer 102.The substrate 101 can be Silicon Wafer, the device
Storage organization, including multiple storage strings are formed in layer 102；The interconnection layer 103 includes multilayer dielectric layer and electrical contacts.
It in the specific embodiment, is electrically connected between the electrical contacts and the storage organization, the electrical contacts include: at least
Conductive plunger 1031, the first metal layer 1032 positioned at 1031 upper layer of conductive plunger for connecting the storage string are located at institute
State first conductive through hole 1033 on 1032 upper layer of the first metal layer and positioned at the second of 1033 upper layer of the first conductive through hole
Metal layer 1034, the surface of the second metal layer 1034 are flushed with the first surface of first substrate.
The storage organization can be 3D NAND storage organization.In other specific embodiments, the device layer 102
It is interior to be formed with other semiconductor devices.
Second substrate, including single-crystal semiconductor layer, second substrate pass through bonding medium layer 210 and first substrate
100 first surface is bonded connection.In the specific embodiment, second substrate includes monocrystalline silicon layer 203, and the bonding is situated between
Matter layer 210 is formed in 203 surface of monocrystalline silicon layer.The material of the bonding medium layer 210 is silica.When due to bonding,
Second substrate, 200 surface is bonding medium layer 210, without considering that alignment when being bonded with the first surface of the first substrate is asked
Topic, therefore, bonding process is relatively simple.
The bonding structure further include: be formed in the semiconductor devices 502 of second substrate surface.The semiconductor device
Part 502 includes at least MOS transistor, to form CMOS peripheral circuit, for controlling the semiconductor device in first substrate 100
Part, such as memory construction.In the specific embodiment, including in the monocrystalline silicon layer 203 form fleet plough groove isolation structure
501 and semiconductor devices 502.
The bonding structure further include: further include: cover the second surface and the semiconductor device of the monocrystalline silicon layer 203
The surface of the interlayer dielectric layer 600 of part 502, the interlayer dielectric layer 600 is flat；Through the interlayer dielectric layer 600, the list
Crystal silicon layer 203 and bonding medium layer 210 run through contact portion 701, described in contact portion 701 and first substrate 100
Electrical contacts electrical connection.
It is described to be located at least in 1034 surface of part second metal layer through 701 bottom of contact portion in the specific embodiment,
It is connect by the electrical contacts in the interconnection layer 103 with the semiconductor devices in the device layer 102.
It is also formed in the specific embodiment, in the interlayer dielectric layer 600 and is located in the interlayer dielectric layer 600 also shape
At there is the multiple electrically conducting contacts 702 for connecting the semiconductor devices 502.In some embodiments, the multiple to lead
Electrical contacts 702 are separately connected source electrode, drain electrode and the grid of MOS transistor.
The bonding structure further include: the interconnection structure 800 positioned at 600 surface of interlayer dielectric layer, the mutual connection
Structure 800 connects the semiconductor devices 502 and described through contact portion 702.In the specific embodiment, the interconnection structure
800, which include: that connection is described, runs through contact portion 701, the first metal layer 801 of the electrically conducting contact 702, positioned at first gold medal
Belong to first conductive through hole 802 on 801 upper layer of layer and the connection the first metal layer 801, be located on first conductive through hole 802
The second metal layer 803 of layer and connection first conductive through hole 802 is located at 803 upper layer of second metal layer and connection institute
The top layer conductive through-hole 804 for stating second metal layer 803, positioned at 804 upper layer of top layer conductive through-hole and the connection top layer is led
The top layer metallic layer 805 of electric through-hole 804.
The interconnection structure 800 runs through contact portion 701 and the electrically conducting contact 701 described in connecting, therefore, described in realization
The company between the semiconductor devices 502 on semiconductor devices and the monocrystalline silicon layer 203 in the device layer 102 of first substrate
It connects.
In above-mentioned bonding structure, by the bonding connection of bonding medium layer between the first substrate and the second substrate, without considering
Alignment issues slightly misplace even if having, and will not influence product yield, reduce the difficulty of bonding alignment.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (16)
1. a kind of forming method of bonding structure characterized by comprising
First substrate is provided, electrical contacts are formed in first substrate, first substrate has opposite first surface
And second surface, the electrical contacts surface are flushed with the first surface of first substrate, first substrate surface passes through
One bonding medium layer is bonded with one second substrate, and the second substrate another side surface opposite with bonding face is formed with semiconductor
The interlayer dielectric layer of device and the covering semiconductor devices and the second substrate surface；
The contact portion that runs through through the interlayer dielectric layer, second substrate and the bonding medium layer is formed, it is described to run through
Contact portion is electrically connected with the electrical contacts.
2. the forming method of bonding structure according to claim 1, which is characterized in that further include: in the inter-level dielectric
Layer surface forms interconnection structure, and the interconnection structure connects the semiconductor devices and described runs through contact portion.
3. the forming method of bonding structure according to claim 1, which is characterized in that second substrate includes a monocrystalline
Semiconductor layer, the bonding medium layer is between the single-crystal semiconductor layer and first substrate.
4. the forming method of bonding structure according to claim 1, which is characterized in that the bonding medium layer is silica
Layer.
5. the forming method of bonding structure according to claim 1, which is characterized in that the semiconductor devices includes at least
MOS transistor.
6. the forming method of bonding structure according to claim 1, which is characterized in that be formed with and deposit in first substrate
Storage structure has between the electrical contacts and the storage organization and is electrically connected.
7. the forming method of bonding structure according to claim 6, which is characterized in that the storage organization is 3D NAND
Storage organization.
8. a kind of forming method of bonding structure characterized by comprising
First substrate is provided, electrical contacts are formed in first substrate, first substrate has opposite first surface
And second surface, the electrical contacts surface are flushed with the first surface of first substrate；
The second substrate is provided, second substrate includes device substrate, the semiconductor for being formed in one side surface of device substrate
Device, is bonded to the interlayer dielectric layer table at the interlayer dielectric layer for covering the device substrate surface and the semiconductor devices
The control substrate in face；
By a bonding medium layer, another side surface of the device substrate is bonded with the first surface of first substrate；
Remove the control substrate.
9. the forming method of bonding structure according to claim 8, which is characterized in that further include: it is formed and runs through the layer
Between dielectric layer, device substrate and the bonding medium layer run through contact portion, it is described through contact portion and electrical contacts electricity
Connection.
10. the forming method of bonding structure according to claim 9, which is characterized in that further include: in the inter-level dielectric
Layer surface forms interconnection structure, and the interconnection structure connects the semiconductor devices and described runs through contact portion.
11. the forming method of bonding structure according to claim 8, which is characterized in that the semiconductor devices at least wraps
Include MOS transistor.
12. the forming method of bonding structure according to claim 8, which is characterized in that be formed in first substrate
Storage organization has between the electrical contacts and the storage organization and is electrically connected.
13. the forming method of bonding structure according to claim 12, which is characterized in that the storage organization is 3D
NAND storage organization.
14. the forming method of bonding structure according to claim 8, which is characterized in that in the another of the device substrate
After side surface forms the bonding medium layer, then it is bonded with the first surface of first substrate.
15. the forming method of bonding structure according to claim 14, which is characterized in that forming the bonding medium layer
Before, reduction processing is carried out to another side surface of the device substrate.
16. the forming method of bonding structure according to claim 8, which is characterized in that the formation side of second substrate
Method includes: to provide a device substrate；Semiconductor devices is formed in a side surface of the device substrate；Formation covering is described partly to be led
The interlayer dielectric layer of body device and the device substrate surface；Substrate is controlled described in the interlayer dielectric layer surface bond.
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| WO2021007767A1 (en) * | 2019-07-16 | 2021-01-21 | Yangtze Memory Technologies Co., Ltd. | Interconnect structures of three-dimensional memory devices |
| CN112635474A (en) * | 2020-12-11 | 2021-04-09 | 中国科学院微电子研究所 | Three-dimensional NAND memory and preparation method thereof |
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| CN109192721A (en) * | 2018-09-05 | 2019-01-11 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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| WO2021007767A1 (en) * | 2019-07-16 | 2021-01-21 | Yangtze Memory Technologies Co., Ltd. | Interconnect structures of three-dimensional memory devices |
| US11205659B2 (en) | 2019-07-16 | 2021-12-21 | Yangtze Memory Technologies Co., Ltd. | Interconnect structures of three-dimensional memory devices |
| US11521986B2 (en) | 2019-07-16 | 2022-12-06 | Yangtze Memory Technologies Co., Ltd. | Interconnect structures of three-dimensional memory devices |
| CN112635474A (en) * | 2020-12-11 | 2021-04-09 | 中国科学院微电子研究所 | Three-dimensional NAND memory and preparation method thereof |
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