CN209401619U

CN209401619U - Semiconductor devices

Info

Publication number: CN209401619U
Application number: CN201920344077.9U
Authority: CN
Inventors: 张志伟
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-03-15
Filing date: 2019-03-15
Publication date: 2019-09-17
Anticipated expiration: 2029-03-15

Abstract

The disclosure proposes a kind of semiconductor devices.The semiconductor devices includes at least one semiconductor chip；Wherein, at least one described semiconductor chip includes the first semiconductor chip, and the first semiconductor core on piece is equipped at least one silicon perforation；Wherein, at least one described silicon perforation includes the first silicon perforation, around first medium layer around first silicon perforation, first silicon perforation extends to the second surface of the semiconductor substrate from the first surface of semiconductor substrate, and the second surface of the semiconductor substrate is not exposed from the bottom of the first medium layer；The second surface of the semiconductor substrate removes the bottom corresponding to the first medium layer to be externally provided with the first oxide layer；The second surface of the semiconductor substrate of bottom corresponding to the first medium layer and first oxide layer are equipped with second dielectric layer.

Description

Semiconductor device with a plurality of transistors

Technical Field

The disclosure belongs to the technical field of semiconductors, and particularly relates to a semiconductor device.

Background

Chip technology advances day by day, and is advancing toward high speed, high integration, high density, and high performance. The shrinking feature sizes and increasing integration levels of integrated circuits mean a doubling of the number of transistors per unit area, thereby enhancing the functionality of the circuit. However, when dense transistors work, a concentrated heat source is formed, how to dissipate heat, and effective cooling of working devices becomes a key problem, so that heterogeneous integration of hybrid chips with non-logic functions occurs, and the main characteristic of the hybrid chips is the transition from a single-core structure to a multi-core structure. The packaging technology is driven to develop towards a three-dimensional package with higher density, such as a stacked die package (stacked die package).

Through Silicon Vias (TSV) are a technology for realizing interconnection by making vertical via holes between chips and between wafers and then depositing conductive substances in the via holes by electroplating or the like. In the TSV process, metal columns are formed in the wafer and metal bumps are matched, so that direct three-dimensional interconnection between wafers (chips) or between the chips and the substrate can be realized, and the limitation of two-dimensional wiring of the traditional semiconductor chip can be overcome. Compared with the traditional stacking technology (such as bonding technology), the interconnection mode has the advantages of large stacking density in the three-dimensional direction, small outline size after packaging and the like, thereby greatly improving the speed of the chip and reducing the power consumption. Therefore, the TSV technology has been widely considered as a fourth generation packaging technology following bonding, tape bonding, and flip chip, and will gradually become a dc technology in the field of high density packaging.

These advanced packaging techniques require thinner chips, so that ultra-precision grinding is widely used as the main process for thinning the back of the chip. After the circuit on the surface of the wafer is manufactured, the silicon material on the back of the wafer is ground and thinned (backside grinding) to reach the required thickness.

It is to be noted that the information of the utility model in the above background section is only used for enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

It is an object of embodiments of the present disclosure to provide a semiconductor device, thereby achieving backside exposure of through-silicon vias at least to some extent.

Other features and advantages of the invention will be apparent from the following detailed description, or may be learned by practice of the invention in part.

According to an aspect of the present disclosure, there is provided a semiconductor structure forming method, including: forming a through silicon via in a semiconductor substrate, wherein the through silicon via surrounds a first dielectric layer around which an air gap is arranged, the through silicon via extends from a first surface of the semiconductor substrate to the inside of the semiconductor substrate, and the semiconductor substrate has a second surface arranged opposite to the first surface; grinding the second surface of the semiconductor substrate to expose the back surface of the through silicon via and not expose the bottom of the first dielectric layer; forming a first oxidation layer on the second surface of the semiconductor substrate and the back surface of the through silicon via; processing the first oxidation layer to expose the back surface of the through silicon via and the second surface of the semiconductor substrate corresponding to the bottom of the first dielectric layer; forming a second dielectric layer on the first oxide layer, the back surface of the through silicon via and the second surface of the semiconductor substrate corresponding to the bottom of the first dielectric layer; and processing the second dielectric layer to expose the back surface of the through silicon via.

According to an aspect of the present disclosure, there is provided a semiconductor structure forming method, including: forming a through silicon via in a semiconductor substrate, wherein the through silicon via surrounds a first dielectric layer around which an air gap is arranged, the through silicon via extends from a first surface of the semiconductor substrate to the inside of the semiconductor substrate, and the semiconductor substrate has a second surface arranged opposite to the first surface; grinding the second surface of the semiconductor substrate to expose the back surface of the through silicon via and the bottom of the first dielectric layer without exposing the air gap; forming a first oxidation layer on the second surface of the semiconductor substrate, the back surface of the through silicon via and the bottom of the first medium layer; processing the first oxidation layer to expose the back surface of the through silicon via and the bottom of the first dielectric layer; forming a second dielectric layer on the first oxide layer, the back of the through silicon via and the bottom of the first dielectric layer; and processing the second dielectric layer to expose the back surface of the through silicon via.

According to an aspect of the present disclosure, there is provided a semiconductor device including at least one semiconductor chip; wherein the at least one semiconductor chip comprises a first semiconductor chip on which at least one through-silicon-via is provided; the at least one through silicon via comprises a first through silicon via, wherein a first dielectric layer is surrounded around the first through silicon via, the first through silicon via extends from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, and the second surface of the semiconductor substrate does not expose the bottom of the first dielectric layer; a first oxide layer is arranged on the second surface of the semiconductor substrate except the bottom corresponding to the first dielectric layer; and a second dielectric layer is arranged on the second surface of the semiconductor substrate corresponding to the bottom of the first dielectric layer and the first oxidation layer.

According to an aspect of the present disclosure, there is provided a semiconductor device including at least one semiconductor chip; wherein the at least one semiconductor chip comprises a first semiconductor chip on which at least one through-silicon-via is provided; the at least one through silicon via comprises a first through silicon via, wherein a first dielectric layer is surrounded around the first through silicon via, the first through silicon via extends from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, and the second surface of the semiconductor substrate exposes the bottom of the first dielectric layer; a first oxide layer is arranged on the second surface of the semiconductor substrate; and a second dielectric layer is arranged on the bottom of the first dielectric layer and the first oxidation layer.

In the technical solutions provided in some embodiments of the present invention, for a semiconductor structure having an air gap in a first dielectric layer surrounding a through-silicon-via, on one hand, by controlling a grinding process during back grinding, a purpose of exposing a back surface of the through-silicon-via can be achieved, and a purpose of not exposing the air gap in the first dielectric layer can be achieved at the same time; on the other hand, the second dielectric layer is formed on the second surface of the semiconductor substrate at a position opposite to the bottom of the first dielectric layer, so that the air gap in the first dielectric layer can be further protected from being damaged by a subsequent process (for example, a process for generating a bonding pad connected with the through silicon via), and the effect of reducing the influence of parasitic capacitance between the through silicon vias by using the air gap can be achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments thereof, when considered in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, like reference characters designate the same or similar parts throughout the different views. Wherein:

fig. 1 schematically illustrates a flow chart of a method of forming a semiconductor structure in an exemplary embodiment of the disclosure.

FIG. 2 shows a flowchart of one embodiment of step S140 of FIG. 1.

Fig. 3 schematically illustrates a flow chart of another method of forming a semiconductor structure in an exemplary embodiment of the present disclosure.

Fig. 4-13 schematically illustrate a schematic diagram of a method of forming a semiconductor structure in an exemplary embodiment of the disclosure.

Fig. 14 schematically illustrates a flow chart of yet another method of forming a semiconductor structure in an exemplary embodiment of the disclosure.

Fig. 15-23 schematically illustrate a schematic view of a method of forming a semiconductor structure in exemplary embodiments of the present disclosure.

Fig. 24 schematically illustrates a schematic structural diagram of a semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 25 schematically illustrates a structural view of another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 26 schematically illustrates a structural view of still another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 27 schematically illustrates a structural view of still another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 28 schematically illustrates a structure of still another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 29 schematically illustrates a structure of still another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 30 schematically illustrates a structure of still another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 31 schematically illustrates a structure of still another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 32 schematically illustrates a structure of still another semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 33 schematically illustrates a structural view of still another semiconductor device in an exemplary embodiment of the present disclosure.

Detailed Description

Exemplary embodiments that embody features and advantages of the present disclosure are described in detail below in the specification. It is to be understood that the disclosure is capable of various modifications in various embodiments without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized, and structural and functional modifications may be made without departing from the scope of the present disclosure.

In a three-dimensional chip (e.g., 3D DRAM, three-dimensional Dynamic Random Access Memory) process technology, Air Gap (Air Gap) may be used to reduce TSV parasitic capacitance, so that RC delay (RC delay) of the TSV may be reduced, thereby improving TSV interference problem and increasing speed performance of the three-dimensional chip.

Fig. 1 schematically illustrates a flow chart of a method of forming a semiconductor structure in an exemplary embodiment of the disclosure. As shown in fig. 1, a method for forming a semiconductor structure provided by the embodiment of the present disclosure may include the following steps.

In step S110, a through-silicon via (TSV) is formed in a semiconductor substrate, wherein the TSV surrounds a first dielectric layer having an Air Gap (Air Gap) therein, the TSV extends from a first surface of the semiconductor substrate to an interior of the semiconductor substrate, and the semiconductor substrate has a second surface disposed opposite to the first surface thereof.

In the embodiment of the present disclosure, a silicon Substrate (Si Substrate) may be used as the semiconductor Substrate, but the present disclosure is not limited thereto, and in other embodiments, any suitable semiconductor Substrate may be selected.

In the embodiment of the present disclosure, the first dielectric layer surrounding the TSV may be made of a silicon nitride (SiN) material, but the present disclosure is not limited thereto, and the first dielectric layer may be made of any material having an insulating property, for example, silicon oxide may also be used. In the embodiment of the present disclosure, the TSV may be a cylinder filled with a conductive substance (for example, the TSV may be a metal such as copper Cu and/or tungsten Wu, or any other non-metal or metal compound having a conductive property), and the first dielectric layer generated around the TSV may be a circular ring shape, but the shape of the TSV and the first dielectric layer is not limited in the present disclosure, for example, the TSV may also be a cylinder with a regular hexagon or regular octagon cross section, and the first dielectric layer may also be a hollow cylinder with a square, regular hexagon, or regular octagon cross section, and the like, which surrounds the TSV.

In the embodiment of the present disclosure, the insulating first dielectric layer of the TSV outer layer may be formed by using an ALD (Atomic layer Deposition) or CVD (Chemical Vapor Deposition) process, which may provide coverage of deposited silicon oxide or silicon nitride, but the present disclosure is not limited thereto, and any suitable process may be used to form the first dielectric layer.

Among them, ALD is a method that can plate a substance on a substrate surface layer by layer in the form of a monoatomic film. In an atomic layer deposition process, the chemical reaction of a new atomic film is directly related to the previous one in such a way that only one layer of atoms is deposited per reaction. The atomic layer deposition technology adopts successive deposition of monoatomic layers, so that a deposited layer has extremely uniform thickness, excellent consistency and the like.

In an exemplary embodiment, the method may further include: providing an inter-metal dielectric (IMD), wherein the IMD is positioned on the first surface of the substrate, and the top of the through-silicon via is positioned in the IMD; a top metal layer (topmetal) is formed on top of the through-silicon-via and the first dielectric layer.

In the embodiment of the disclosure, the inter-metal dielectric layer may be made of SiO₂The material is made of, but the present disclosure is not limited thereto, and any suitable material having insulating properties may be used.

In an exemplary embodiment, a radius of the top metal layer may be greater than or equal to a sum of a radius of the through-silicon via and a thickness of the first dielectric layer.

In step S120, the second surface of the semiconductor substrate is polished to expose the back surface of the through-silicon via and not expose the bottom of the first dielectric layer; and forming a first oxidation layer on the second surface of the semiconductor substrate and the back surface of the through silicon via.

In the embodiment of the present disclosure, if the TSV is assumed to be filled with Cu, a Cu CMP (chemical mechanical polishing) process may be used to polish the second surface of the semiconductor substrate, but the present disclosure is not limited thereto, and in other embodiments, other polishing methods may be used as long as the second surface of the semiconductor substrate can be thinned.

In the embodiment of the present disclosure, the first oxide layer may be made of any oxide having an insulating property, and the present disclosure does not limit this.

In step S130, the first oxide layer is processed to expose the back surface of the through-silicon-via and the second surface of the semiconductor substrate corresponding to the bottom of the first dielectric layer; and forming a second dielectric layer on the first oxide layer, the back surface of the through silicon via and the second surface of the semiconductor substrate corresponding to the bottom of the first dielectric layer.

In step S140, the second dielectric layer is processed to expose the back surface of the through silicon via.

In an exemplary embodiment, the method may further include: forming a conducting layer on the second medium layer, wherein the conducting layer is connected with the back of the through silicon via; and forming a Bonding pad (Bonding pad) by using copper process chemical mechanical (Cu CMP) grinding on the conductive layer.

According to the semiconductor structure forming method provided by the embodiment of the disclosure, for the semiconductor structure with the air gap in the first dielectric layer surrounding the through silicon via, on one hand, the purpose of exposing the back surface of the through silicon via and the purpose of not exposing the air gap in the first dielectric layer can be achieved by controlling the grinding process during back grinding; on the other hand, the second dielectric layer is formed on the second surface of the semiconductor substrate at a position opposite to the bottom of the first dielectric layer, so that the air gap in the first dielectric layer can be further protected from being damaged by a subsequent process (for example, a process for generating a bonding pad connected with the through silicon via), and the effect of reducing the influence of parasitic capacitance between the through silicon vias by using the air gap can be achieved.

FIG. 2 shows a flowchart of one embodiment of step S140 of FIG. 1.

As shown in fig. 2, step S140 in the embodiment of fig. 1 may further include the following steps.

In step S141, a second oxide layer is formed on the second dielectric layer.

In the embodiment of the present disclosure, the second oxide layer may be made of any oxide having an insulating property, and the present disclosure does not limit this.

In step S142, the second dielectric layer and the second oxide layer are processed to expose the back surface of the through silicon via and at least partially leave the second oxide layer at a position opposite to the bottom of the first dielectric layer.

In the method for forming a semiconductor structure provided by the embodiment of the disclosure, the second dielectric layer is formed on the second surface of the semiconductor substrate at a position corresponding to the bottom of the first dielectric layer, and the second dielectric layer is further formed at a position corresponding to the bottom of the first dielectric layer to form a second oxide layer, which is equivalent to adding two protective layers to an air gap in the first dielectric layer, so that a double guarantee can be formed, and further the air gap in the first dielectric layer can be further prevented from being damaged by a subsequent process.

The method for forming the semiconductor structure provided by the above embodiments is illustrated by fig. 3 to 13, but is not intended to limit the scope of the present disclosure.

Fig. 3 schematically illustrates a flow chart of another method of forming a semiconductor structure in an exemplary embodiment of the present disclosure. The respective steps will be described below with reference to fig. 4 to 13.

As shown in fig. 3, a method for forming a semiconductor structure provided by the embodiment of the present disclosure may include the following steps.

In step S301, TSVs are formed in the silicon substrate and the IMD, and the TSVs surround the first dielectric layer, and the first dielectric layer has an air gap therein.

Referring to fig. 4, TSV20 is formed in silicon substrate 10 and IMD50, TSV20 surrounds first dielectric layer 30, and first dielectric layer 30 has air gap 40 therein. The back surface of the TSV20 is located inside the silicon substrate 10, and a distance between the back surface of the TSV20 and a second surface of the silicon substrate 10 (the second surface of the silicon substrate 10 is assumed to be a lower surface of the silicon substrate 10, and the lower surface may also be referred to as a back surface, and a distance between a first surface of the silicon substrate 10 and the second surface thereof is assumed to be d1, and a distance between a bottom of the first dielectric layer 30 and the second surface of the silicon substrate 10 is assumed to be d2, where d2 may be greater than or equal to d1, and d2 is greater than d1 in the embodiment of fig. 4 is exemplified.

In the embodiment of fig. 4, the top of TSV20 is located within IMD50, wherein the top of TSV20 and the backside of TSV20 are two oppositely disposed surfaces. And the top of TSV20 is a first distance from the first surface of IMD50, a top metal layer (e.g., 61 and 62 as shown) may be further disposed on the top of first dielectric layer 30 and on the top of TSV 20.

Assuming here that TSV20 is a cylinder with radius R and assuming that first dielectric layer 30 is circular and has thickness h1, and assuming that top metal is also a cylinder, in the embodiment shown in fig. 4, two TSVs are shown, where the width w1 of top metal layer 61 on top of the left TSV is equal to the sum of the diameter (2R) of TSV20 and 2 times the thickness 2h1 of first dielectric layer 30, i.e., w1 is 2R +2h 1; the width w2 of the top metal layer 62 at the top of the right TSV is greater than the sum of the diameter (2R) of TSV20 and the 2 times thickness 2h1 of the first dielectric layer 30, i.e., w2>2R +2h 1. The disclosure is not limited thereto, and the semiconductor structure may include one or more TSVs, and if one TSV is included, the width of the top metal layer on the top of the one TSV may be equal to or greater than 2R +2h 1; if a plurality of TSVs are included, the width of the top metal layer of a part of the TSV tops is equal to 2R +2h1, and the width of the top metal layer of another part of the TSV tops is greater than 2R +2h 1; the width of the top metal layer of all the TSV tops is equal to 2R +2h1, and the width of the top metal layer of all the TSV tops is larger than 2R +2h 1.

In step S302, the silicon substrate is back-ground by Cu CMP, exposing the backside of the TSV without exposing the bottom of the first dielectric layer.

As shown in fig. 5, by controlling the polishing thickness during the Cu CMP process, the back surface of the TSV20 can be exposed, and the bottom of the first dielectric layer 30 is not exposed, that is, after the silicon substrate 10 is polished, the first dielectric layer 30 is further away from the second surface of the silicon substrate 10 by a certain distance, so that the air gap 40 is not exposed, for example, if the polishing thickness is controlled to be equal to d1, the first dielectric layer 30 is further away from the second surface of the silicon substrate 10 by a distance of (d2-d1), that is, the polishing thickness is controlled to be greater than or equal to d1 and less than or equal to d 2.

It should be noted that although the first dielectric layer 30 is still spaced from the second surface of the silicon substrate 10 after polishing in the embodiment of fig. 5, in other embodiments, the polishing thickness may be slightly greater than d2 as long as the air gap 40 in the first dielectric layer 30 is not exposed, and the bottom of the first dielectric layer 30 is not exposed.

In step S303, a back oxide deposition (Backside oxide deposition) is performed on the silicon substrate and the TSV to form a first oxide layer.

As shown in fig. 6, a first oxide layer 70 is formed by first depositing an oxide on the second surface of silicon substrate 10 and on the backside of TSV 20.

In step S304, a layer of photoresist is covered on the first oxide layer except for the position where the TSV is opposite to the first dielectric layer.

As shown in fig. 7, a layer of photoresist 80 is coated on the first oxide layer 70 except for the position opposite to the bottom of the first dielectric layer 30 and the backside of TSV 20.

In step S305, the first oxide layer is etched by using the photoresist, and the photoresist is removed, so that a cavity is formed on the first oxide layer at a position corresponding to the TSV and the first dielectric layer, so as to expose the backside of the TSV and the second surface of the silicon substrate corresponding to the bottom of the first dielectric layer.

As shown in fig. 8, after the first oxide layer 70 is etched by the photoresist 80, the photoresist 80 is removed, so that a recess may be formed in the first oxide layer 70 at a corresponding position with respect to the back surface of the TSV20 and the bottom of the first dielectric layer 30, thereby exposing the back surface of the TSV20 and the second surface of the silicon substrate 10 corresponding to the bottom of the first dielectric layer 30.

In step S306, a back side SiC/SiOn deposition is performed to form a second dielectric layer.

As shown in fig. 9, SiC/SiOn is deposited on the first oxide layer 70, the second surface of the silicon substrate 10 corresponding to the bottom of the first dielectric layer 30, and the backside of the TSV20, where n is a positive integer greater than or equal to 1, to form a second dielectric layer 90.

In step S307, a second back oxide deposition is performed to form a second oxide layer.

As shown in fig. 10, an oxide is deposited on the second dielectric layer 90 to form a second oxide layer 100.

In step S308, the backside of the TSV is exposed using a backside oxide dry etching and SiC/SiOn dry etching process, while a second dielectric layer and a second oxide layer are formed on the second surface of the silicon substrate corresponding to the bottom of the first dielectric layer.

As shown in fig. 11, by dry etching (dry etch) the second oxide layer 100, only the second oxide layer 100 opposite to the bottom of the first dielectric layer 30 remains, and the rest of the second oxide layer 100 is etched away. Meanwhile, the second dielectric layer 90 at a position opposite to the back surface of the TSV20 is dry-etched to expose the back surface of the TSV 20.

It should be noted that, in the embodiment shown in fig. 11, the thickness of the remaining second oxide layer 100 may be less than or equal to the thickness of the first oxide layer 70, which is not limited by the present disclosure.

In step S309, a conductive layer is formed using a back Cu sputtering/Cu plating process.

As shown in fig. 12, a Cu shower/Cu plating process may be used to form a conductive layer 110 on the second dielectric layer 90, the second oxide layer 100 and the backside of the TSV 20.

In step S310, the conductive layer is polished using backside Cu CMP to form a pad.

As shown in fig. 13, the pad 111 can be formed by Cu CMP annihilation conductive layer 110, and the pad 111 and the back surface of the TSV20 can be mechanically and electrically connected to each other. In the embodiment of the disclosure, two protective layers, i.e., the second dielectric layer 90 and the second oxide layer 100, are formed on the bottom of the first dielectric layer 30 in advance, so that the air gap 40 in the first dielectric layer 30 is not exposed during the process of forming the pad 111 by Cu CMP, and copper infiltration is prevented.

Fig. 14 schematically illustrates a flow chart of yet another method of forming a semiconductor structure in an exemplary embodiment of the disclosure. As shown in fig. 14, a method for forming a semiconductor structure provided by the embodiment of the present disclosure may include the following steps.

In step S1410, a through-silicon via is formed in a semiconductor substrate, wherein the through-silicon via surrounds a first dielectric layer having an air gap therein, the through-silicon via extends from a first surface of the semiconductor substrate to an interior of the semiconductor substrate, and the semiconductor substrate has a second surface disposed opposite to the first surface.

In step S1420, grinding the second surface of the semiconductor substrate to expose the back surface of the through-silicon-via and the bottom of the first dielectric layer without exposing the air gap; and forming a first oxidation layer on the second surface of the semiconductor substrate, the back surface of the through silicon via and the bottom of the first medium layer.

In step S1430, the first oxide layer is processed to expose the back surface of the through silicon via and the bottom of the first dielectric layer; and forming a second dielectric layer on the first oxide layer, the back surface of the through silicon via and the bottom of the first dielectric layer.

In step S1440, the second dielectric layer is processed to expose the back surface of the through silicon via.

The method shown in fig. 14 is described below with reference to fig. 15 to 23, but the present disclosure is not limited thereto.

As shown in fig. 15, it is assumed that the second surface of silicon substrate 10 in the semiconductor structure shown in fig. 4 is polished (at this time, d2 in fig. 4 may be greater than or equal to d1), and by controlling the polishing thickness, the backside of TSV20 and the bottom of first dielectric layer 30 may be exposed, while ensuring that air gap 40 inside first dielectric layer 30 is not exposed. That is, fig. 15 is different from fig. 5 in that after the back grinding in the embodiment of fig. 5, a layer of silicon substrate is still on the bottom of the first dielectric layer 30, and after the back grinding in the embodiment of fig. 15, the silicon substrate on the bottom of the first dielectric layer 30 is ground away.

As shown in fig. 16, a first oxide layer 70 is formed on the second surface of the silicon substrate 10, the backside of the TSV20, and the bottom of the first dielectric layer 30.

As shown in fig. 17, first oxide layer 70 is covered with a layer of photoresist 80 on the backside except for the bottom corresponding to TSV20 and first dielectric layer 30.

As shown in fig. 18, the first oxide layer 70 on the back surface of the TSV20 and the bottom of the first dielectric layer 30 is etched away by an etching process and removing the photoresist 80, and the first oxide layer 70 on the second surface of the silicon substrate 10 remains.

As shown in fig. 19, a second dielectric layer 90 is formed on the backside of first oxide layer 70, the backside of TSV20, and the bottom of first dielectric layer 30.

As shown in fig. 20, a second oxide layer 100 is deposited on the second dielectric layer 90.

As shown in fig. 21, the second dielectric layer 90 and the second oxide layer 100 on the backside of the TSV20 are etched away by a dry etching process, while the second oxide layer 100 on the second dielectric layer 90 corresponding to the second surface of the silicon substrate 10 is etched away, and the second oxide layer 100 on the second dielectric layer 90 corresponding to the bottom of the first dielectric layer 30 is partially remained.

As shown in fig. 22, Cu sputtering or Cu plating is performed on the second dielectric layer 90, the second oxide layer 100, and the backside of the TSV20 to form a conductive layer 110.

As shown in fig. 23, the pad 111 is formed by back grinding by Cu CMP.

For the content not described in the embodiments of fig. 14 to 23, reference may be made to the content in other embodiments.

Another method for forming a semiconductor structure provided in an embodiment of the present disclosure may include: a plurality of through silicon vias can be formed in the semiconductor substrate, each through silicon via surrounds the first dielectric layer, wherein part or all of the first dielectric layer can have an air gap inside, each through silicon via extends from the first surface of the semiconductor substrate to the inside of the semiconductor substrate, and the semiconductor substrate has a second surface arranged opposite to the first surface; and grinding the second surface of the semiconductor substrate to expose the back surface of all the through silicon vias, expose the bottom of the first dielectric layer of a part of the through silicon vias, not expose the bottom of the first dielectric layer of another part of the through silicon vias and not expose the air gaps in the first dielectric layer of all the through silicon vias. Reference may be made to the embodiments shown in fig. 1-13 for the subsequent process steps of the through-silicon-via that does not expose the bottom of the first dielectric layer. For subsequent process steps to expose the through-silicon-via at the bottom of the first dielectric layer, reference may be made to the embodiments shown in fig. 14-23.

Further, the embodiment of the present disclosure also provides a semiconductor device, which may include at least one semiconductor chip; wherein the at least one semiconductor chip may include a first semiconductor chip on which at least one through-silicon-via may be provided; the at least one through silicon via may include a first through silicon via, a first dielectric layer may be surrounded around the first through silicon via, and the first through silicon via may extend from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, where a bottom of the first dielectric layer is not exposed at the second surface of the semiconductor substrate; the second surface of the semiconductor substrate except the bottom corresponding to the first dielectric layer can be provided with a first oxide layer; a second dielectric layer may be disposed on the second surface of the semiconductor substrate and the first oxide layer corresponding to the bottom of the first dielectric layer.

In an exemplary embodiment, the first dielectric layer may have an air gap therein.

In an exemplary embodiment, a second oxide layer may be disposed on the second dielectric layer at a position opposite to the bottom of the first dielectric layer.

In an exemplary embodiment, the semiconductor device may further include a substrate and/or a second semiconductor chip, and a back surface of the first through-silicon-via is connected with a pad for electrical connection with the substrate and/or the second semiconductor chip adjacent to the first semiconductor chip.

In an exemplary embodiment, the first semiconductor chip may further include an inter-metal dielectric layer, the inter-metal dielectric layer may be disposed on the first surface of the semiconductor substrate, and a top of the through-silicon-via may be located within the inter-metal dielectric layer and have a first distance from the first surface of the inter-metal dielectric layer; a top metal layer may be disposed on top of the through-silicon via and the first dielectric layer, and a thickness of the top metal layer may be equal to the first distance; the first surface of the metal interlayer dielectric layer is far away from the first surface of the semiconductor substrate, and the second surface of the metal interlayer dielectric layer is close to the first surface of the semiconductor substrate.

In an exemplary embodiment, the first semiconductor chip may be a DRAM chip. The semiconductor device may be a 3D DRAM, but the present disclosure is not limited thereto.

In an exemplary embodiment, the first dielectric layer may include silicon oxide and/or silicon nitride.

In an exemplary embodiment, the second dielectric layer may include silicon carbide and/or silicon oxide.

In the embodiment of the present disclosure, a partial structure of a semiconductor device may be as shown in fig. 13, assuming that one semiconductor chip in the semiconductor device has a semiconductor substrate 10, an IMD50 may be disposed on a first surface of the semiconductor substrate 10, at least one TSV (two TSVs are taken as an example, but the number of TSVs is not limited in practice) 20 is disposed inside the semiconductor substrate 10 and the IMD50, a first dielectric layer 30 is surrounded around the TSV20, and an air gap 40 may be disposed in the first dielectric layer 30.

With continued reference to fig. 13, top metal layers 61 and 62 may also be provided on top of TSV20 and on top of first dielectric layer 30, assuming that width w1 of top metal layer 61 is greater than width w2 of 62. Further, a second dielectric layer 90 and a second oxide layer 100 are sequentially disposed on a second surface of the semiconductor substrate 10 opposite to the bottom of the first dielectric layer 30 at the back side connection pad 111 of the TSV 20. Further, a first oxide layer 70 and a second dielectric layer 90 are sequentially disposed on the second surface of the semiconductor substrate 10 except for the bottom of the first dielectric layer 30 and the back surface of the TSV 20.

Fig. 24 schematically illustrates a structural view of another semiconductor device in an exemplary embodiment of the present disclosure.

As shown in fig. 24, it is different from the embodiment shown in fig. 13 in that the widths of the top metal layers 61 and 62 at the top of the two TSVs on the left and right are equal to w1, where w1 is 2R +2h 1.

As shown in fig. 25, it differs from the embodiment shown in fig. 13 in that the top metal layers 61 and 62 on the top of the two TSVs on the left and right have the same width, equal to w2, where w2>2R +2h 1.

As shown in fig. 26, it is different from the embodiment shown in fig. 13 in that there is no air gap in the first dielectric layer 30 of both the left and right TSVs 20.

As shown in fig. 27, it is different from the embodiment shown in fig. 24 in that there is no air gap in the first dielectric layer 30 of both the left and right TSVs 20.

As shown in fig. 28, it is different from the embodiment shown in fig. 25 in that there is no air gap in the first dielectric layer 30 of both the left and right TSVs 20.

As shown in fig. 29, it differs from the embodiment shown in fig. 13 in that there is no air gap in first dielectric layer 30 of TSV20 on the left and an air gap 40 in first dielectric layer 30 of TSV20 on the right.

As shown in fig. 30, it differs from the embodiment shown in fig. 24 in that there is no air gap in first dielectric layer 30 of TSV20 on the left and an air gap 40 in first dielectric layer 30 of TSV20 on the right.

As shown in fig. 31, it differs from the embodiment shown in fig. 25 in that there is no air gap in first dielectric layer 30 of TSV20 on the left and an air gap 40 in first dielectric layer 30 of TSV20 on the right.

As shown in fig. 32, it differs from the embodiment shown in fig. 13 in that there is an air gap 40 in the first dielectric layer 30 of the left TSV20 and no air gap 40 in the first dielectric layer 30 of the right TSV 20.

Further, the embodiment of the present disclosure also provides a semiconductor device, which includes at least one semiconductor chip; wherein the at least one semiconductor chip comprises a first semiconductor chip on which at least one through-silicon-via is provided; the at least one through silicon via comprises a first through silicon via, wherein a first dielectric layer is surrounded around the first through silicon via, the first through silicon via extends from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, and the second surface of the semiconductor substrate exposes the bottom of the first dielectric layer; a first oxide layer is arranged on the second surface of the semiconductor substrate; and a second dielectric layer is arranged on the bottom of the first dielectric layer and the first oxidation layer.

In the embodiment of the present disclosure, a partial structure of a semiconductor device may be as shown in fig. 23, which is different from the embodiment shown in fig. 13 in that a second dielectric layer 90 and a second oxide layer 100 are sequentially disposed on the bottom of the first dielectric layer 30.

As shown in fig. 33, the embodiment of the present disclosure is different from the embodiment of fig. 23 in that, when a plurality of through-silicon vias are included in the semiconductor substrate 10 (two TSVs 20 are exemplified here), a second dielectric layer 90 and a second oxide layer 100 may be sequentially formed on the bottom of the first dielectric layer of a part of the through-silicon vias (for example, the left TSV20 of fig. 33), and a second dielectric layer 90 and a second oxide layer 100 may be sequentially formed on the second surface of the semiconductor substrate 10 corresponding to the bottom of the first dielectric layer of another part of the through-silicon vias (for example, the right TSV20 of fig. 33).

It should be noted that the above embodiments may be combined arbitrarily, and for example, the width of the top metal layer on the through-silicon via in the semiconductor device shown in fig. 33, whether or not the first dielectric layer includes an air gap, and the like may be combined arbitrarily.

Exemplary embodiments of a semiconductor structure forming method and a semiconductor device proposed by the present disclosure are described and/or illustrated in detail above. Embodiments of the disclosure are not limited to the specific embodiments described herein, but rather, components and/or steps of each embodiment may be utilized independently and separately from other components and/or steps described herein. Each component and/or step of one embodiment can also be used in combination with other components and/or steps of other embodiments. When introducing elements/components/etc. described and/or illustrated herein, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements/components/etc. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. Furthermore, the terms "first" and "second" and the like in the claims and the description are used merely as labels, and are not numerical limitations of their objects.

As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or program product. Accordingly, various aspects of the present disclosure may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software may be referred to herein generally as a "circuit," module "or" system.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Claims

1. A semiconductor device, characterized in that the semiconductor device comprises at least one semiconductor chip; wherein,

the at least one semiconductor chip comprises a first semiconductor chip, and at least one through silicon via is arranged on the first semiconductor chip; wherein,

the at least one through silicon via comprises a first through silicon via, wherein a first dielectric layer is surrounded around the first through silicon via, the first through silicon via extends from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, and the second surface of the semiconductor substrate does not expose the bottom of the first dielectric layer;

a first oxide layer is arranged on the second surface of the semiconductor substrate except the bottom corresponding to the first dielectric layer;

and a second dielectric layer is arranged on the second surface of the semiconductor substrate corresponding to the bottom of the first dielectric layer and the first oxidation layer.

2. The semiconductor device of claim 1, wherein the first dielectric layer has an air gap therein.

3. The semiconductor device according to claim 1, wherein a second oxide layer is provided on the second dielectric layer at a position opposite to the bottom of the first dielectric layer.

4. The semiconductor device according to claim 1, further comprising a substrate and/or a second semiconductor chip, wherein a backside of the first through-silicon-via is connected with a pad for making an electrical connection with the substrate and/or the second semiconductor chip adjacent to the first semiconductor chip.

5. The semiconductor device of claim 1, wherein the first semiconductor chip further comprises an inter-metal dielectric layer disposed on the first surface of the semiconductor substrate, wherein a top of the through-silicon-via is located within the inter-metal dielectric layer and has a first distance from the first surface of the inter-metal dielectric layer;

a top metal layer is arranged on the top of the through silicon via and the first dielectric layer, and the thickness of the top metal layer is equal to the first distance;

the first surface of the metal interlayer dielectric layer is far away from the first surface of the semiconductor substrate, and the second surface of the metal interlayer dielectric layer is close to the first surface of the semiconductor substrate.

6. The semiconductor device of claim 5, wherein a radius of the top metal layer is greater than or equal to a sum of a radius of the through-silicon-via and a thickness of the first dielectric layer.

7. The semiconductor device according to claim 5, wherein the first semiconductor chip is a DRAM chip.

8. The semiconductor device of claim 1, wherein the first dielectric layer comprises silicon oxide and/or silicon nitride.

9. The semiconductor device of claim 1, wherein the second dielectric layer comprises silicon carbide and/or silicon oxide.

10. A semiconductor device, characterized in that the semiconductor device comprises at least one semiconductor chip; wherein,

the at least one through silicon via comprises a first through silicon via, wherein a first dielectric layer is surrounded around the first through silicon via, the first through silicon via extends from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, and the second surface of the semiconductor substrate exposes the bottom of the first dielectric layer;

a first oxide layer is arranged on the second surface of the semiconductor substrate;

and a second dielectric layer is arranged on the bottom of the first dielectric layer and the first oxidation layer.