KR20120120776A - Semiconductor package and method for manufacturing the same - Google Patents

Semiconductor package and method for manufacturing the same Download PDF

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KR20120120776A
KR20120120776A KR1020110038537A KR20110038537A KR20120120776A KR 20120120776 A KR20120120776 A KR 20120120776A KR 1020110038537 A KR1020110038537 A KR 1020110038537A KR 20110038537 A KR20110038537 A KR 20110038537A KR 20120120776 A KR20120120776 A KR 20120120776A
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wafer
barrier film
silicon via
silicon
semiconductor package
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KR1020110038537A
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Korean (ko)
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배병욱
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에스케이하이닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A semiconductor package including a through silicon via and a manufacturing method thereof are provided to prevent a bridge between a wafer and a bump by forming a barrier film pattern around a rear part which protrudes from a through silicon via. CONSTITUTION: A wafer(101B) has a front side(A) and a rear side(B). A through silicon via(102) is buried in a through hole(103) passing through the wafer. A bump(107) is connected to the rear part of the through silicon via. A barrier film pattern(106) is formed on the rear of the wafer and includes a first barrier layer(104A) and a second barrier(105A).

Description

관통실리콘비아를 구비한 반도체 패키지 및 그 제조 방법{SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME}Semiconductor package with through silicon vias and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

본 발명은 반도체장치 제조 방법에 관한 것으로서, 특히 관통실리콘비아를 구비한 반도체 패키지 및 그 제조 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor package having a through silicon via and a method of manufacturing the same.

반도체 집적회로(IC)의 패키징 기술 중, 3차원 적층 기술은 전자 소자의 크기를 줄이는 동시에 실장 밀도를 높이며 그 성능을 향상시킬 수 있는 목표를 두고 개발되어 왔다. 이러한 3차원 적층 기술을 이용한 패키지는 동일한 기억 용량의 칩을 복수개 적층한 패키지로서, 통상 스택 패키지(Stack package)라 한다. 스택 패키지는 데이터 기억 용량을 매우 용이하게 증가시킬 수 있다는 장점이 있지만, 적층되는 칩의 수 및 크기 증가에 따라 패키지 내부의 전기적 연결을 위한 배선 공간이 부족하다는 단점이 있다.Among packaging technologies of semiconductor integrated circuits (ICs), three-dimensional lamination technology has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance thereof. The package using the three-dimensional stacking technology is a package in which a plurality of chips having the same storage capacity are stacked, and is generally called a stack package. The stack package has an advantage of increasing data storage capacity very easily, but there is a disadvantage in that wiring space for electrical connection inside the package is insufficient as the number and size of chips stacked are increased.

스택 패키지의 이러한 단점을 해결하기 위하여 최근에는 반도체 칩 내에 도전성 물질로 이루어진 관통전극(Through electrode)을 형성하여, 관통전극을 통해 반도체 칩들 간을 전기적으로 연결시키는 방법이 이용되고 있다. 관통전극은 관통실리콘비아(TSV)라고도 일컫는다.In order to solve this disadvantage of a stack package, a method of forming a through electrode made of a conductive material in a semiconductor chip and electrically connecting the semiconductor chips through the through electrode has been recently used. The through electrode is also referred to as through silicon via (TSV).

관통전극을 이용하면 미세 피치 I/O 패드의 본딩이 가능하여 I/O 패드 수의 증가가 가능하고, 다수의 I/O 패드 형성을 통해 칩들 간의 신호 전달 속도를 향상시킬 수 있으며, 반도체 칩의 3차원 설계가 가능하여 반도체 칩 자체의 성능을 더욱 향상시킬 수 있다. The use of the through electrode enables bonding of fine pitch I / O pads, thereby increasing the number of I / O pads, and improving the signal transfer speed between chips by forming a plurality of I / O pads. Three-dimensional design is possible to further improve the performance of the semiconductor chip itself.

도 1은 종래기술에 따른 관통실리콘비아(TSV)를 갖는 반도체 패키지를 도시한 도면이다. 1 is a diagram illustrating a semiconductor package having a through silicon via (TSV) according to the prior art.

도 1을 참조하면, 웨이퍼(11), 웨이퍼(11)를 관통하는 관통실리콘비아(12), 관통실리콘비아(12)의 일측 단부에 접속된 범프(13)를 포함한다.Referring to FIG. 1, a wafer 11, a through silicon via 12 penetrating through the wafer 11, and a bump 13 connected to one end of the through silicon via 12 may be included.

상기와 같은 종래기술은, 웨이퍼(11)를 패키징하기 위해 웨이퍼 후면(도면부호 'B')을 그라인딩(Wafer Backgrinding)후 관통실리콘비아(TSV, 12)의 프로파일(Profile)이 원래는 원형을 유지하여야 하는데, 마스크 공정시의 PTL 및 백그라인딩시 구리 밀림 등으로 인해 관통실리콘비아(12)의 형태가 찌그러지게 된다.In the prior art as described above, the profile of the through silicon via (TSV, 12) remains original after grinding the wafer backside (B ') to package the wafer 11. It should be, but the shape of the through-silicon via 12 is distorted due to PTL during the mask process and copper rolling during the backgrinding.

이럴 경우, 후속 패키지 공정 진행시 웨이퍼 후면(Wafer Backside)에 드러나 있는 관통실리콘비아(12)와 다른 칩의 범프(13)를 접촉시킬 때, 오버레이 마진 감소 및 웨이퍼(11)와 범프(13)간의 브릿지(도면부호 'S' 참조)가 일어나 칩의 불량을 초래한다.
In this case, when the through silicon via 12 exposed on the wafer backside and the bump 13 of another chip are contacted during the subsequent package process, the overlay margin is reduced and the wafer 11 and the bump 13 are separated. A bridge (see symbol 'S') occurs, resulting in chip failure.

본 발명은 관통실리콘비아를 이용한 패키지 공정시 웨이퍼와 범프간의 브릿지를 방지할 수 있는 반도체 패키지 및 그 제조 방법을 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a method of manufacturing the same, which can prevent a bridge between a wafer and a bump during a package process using through silicon vias.

상기 목적을 달성하기 위한 본 발명의 반도체 패키지는 웨이퍼; 상기 웨이퍼를 관통하며 후면부가 돌출된 관통실리콘비아; 상기 관통실리콘비아의 후면부 표면을 노출시키고 상기 웨이퍼의 후면 상에 형성된 배리어막; 및 상기 관통실리콘비아의 후면부에 연결된 범프를 포함하는 것을 특징으로 한다. 상기 배리어막은 절연막을 포함하며, 산화막과 질화막이 적층된다.The semiconductor package of the present invention for achieving the above object is a wafer; A through silicon via penetrating the wafer and having a rear surface protruding from the wafer; A barrier film formed on the back surface of the wafer to expose a back surface of the through silicon via; And a bump connected to a rear portion of the through silicon via. The barrier film includes an insulating film, and an oxide film and a nitride film are stacked.

그리고, 본 발명의 반도체 패키지 제조 방법은 웨이퍼를 관통하는 복수의 관통실리콘비아를 형성하는 단계; 상기 웨이퍼의 후면을 선택적으로 제거하여 상기 관통실리콘비아의 후면부를 돌출시키는 단계; 상기 관통실리콘비아의 후면부를 포함한 상기 웨이퍼의 후면을 덮는 배리어막을 형성하는 단계; 상기 관통실리콘비아의 후면부 표면이 노출되도록 상기 배리어막을 평탄화하는 단계; 및 상기 관통실리콘비아의 후면부와 연결되는 범프를 형성하는 단계를 포함하는 것을 특징으로 한다. 상기 관통실리콘비아의 후면부를 돌출시키는 단계는 상기 웨이퍼의 후면을 건식식각하는 것을 특징으로 한다. 상기 배리어막을 형성하는 단계에서 상기 배리어막은 절연막을 이용하여 형성하는 것을 특징으로 한다.
In addition, the semiconductor package manufacturing method of the present invention comprises the steps of forming a plurality of through silicon vias penetrating the wafer; Selectively removing the back side of the wafer to project the back side of the through silicon via; Forming a barrier film covering a back surface of the wafer including a back surface of the through silicon via; Planarizing the barrier layer to expose a rear surface of the through silicon via; And forming a bump connected to the rear portion of the through silicon via. Protruding the back side of the through silicon via is characterized in that the dry etching the back side of the wafer. In the forming of the barrier film, the barrier film may be formed using an insulating film.

상술한 본 발명은 관통실리콘비아의 돌출된 후면부 주위에 배리어막패턴이 형성되기 때문에, 관통실리콘비아의 형태가 찌그러지더라도 웨이퍼와 관통실리콘비아간의 브릿지가 발생하는 것을 방지할 수 있다. 이로써, 오버레이마진(O/L Margin)을 개선할 수 있다.Since the barrier film pattern is formed around the protruding backside of the through silicon via, the above-described invention can prevent the bridge between the wafer and the through silicon via from occurring even if the through silicon via is distorted. As a result, overlay margin O / L Margin may be improved.

따라서, 본 발명은 관통실리콘비아(TSV)를 이용한 패키지 공정에서 발생하는 불량을 제거함으로써 수율 개선을 하여 제품생산 단가를 낮출수 있다.
Therefore, the present invention can reduce the production cost by improving the yield by eliminating defects generated in the packaging process using the through-silicon via (TSV).

도 1은 종래기술에 따른 반도체 패키지를 도시한 도면이다.
도 2는 본 발명의 실시예에 따른 반도체 패키지를 도시한 도면이다.
도 3a 내지 도 3f는 본 발명의 실시예에 따른 반도체 패키지 제조 방법을 도시한 도면이다.1 is a view showing a semiconductor package according to the prior art.
2 illustrates a semiconductor package according to an embodiment of the present invention.
3A to 3F illustrate a method of manufacturing a semiconductor package according to an embodiment of the present invention.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

본 발명은 웨이퍼 후면(Wafer Backside)의 실리콘을 일정부분 제거하고 그 위에 절연막을 입혀 관통실리콘비아(TSV)의 형태가 찌그러지더라도 웨이퍼와 범프간의 브릿지(BRG)를 방지함으로써, 오버레이마진(O/L Margin)을 개선하고, 실리콘과 구리의 브릿지를 방지하는 방법이다.The present invention removes a portion of silicon from the wafer backside and coats an insulating film thereon to prevent the bridge (BRG) between the wafer and the bump even if the through silicon via (TSV) is distorted, thereby providing an overlay margin (O / L Margin) and prevent the bridge between silicon and copper.

도 2는 본 발명의 실시예에 따른 반도체 패키지를 도시한 도면이다.2 illustrates a semiconductor package according to an embodiment of the present invention.

도 2에 도시된 바와 같이, 본 발명의 실시예에 따른 반도체 패키지는 전면(A)과 후면(B)을 갖는 웨이퍼(101B), 웨이퍼(101B)를 관통하는 관통홀(103)에 매립된 관통실리콘이바(102), 관통실리콘비아(102)의 일측 단부, 즉 후면부에 접속된 범프(107)를 포함한다. 관통실리콘비아(102)의 후면부(도면부호 'C' 참조)는 웨이퍼(101B)의 표면(즉, 후면)으로부터 일정 높이 돌출되어 있고, 관통실리콘비아(102)의 후면부 사이의 웨이퍼(101B) 후면 상에는 배리어막패턴(106)이 형성되어 있다. 배리어막패턴(106)은 절연막을 이용하여 형성하며, 제1배리어막(104A)과 제2배리어막(105A)을 포함한다. 제1배리어막(104A)은 실리콘산화막 등의 산화막을 포한한다. 제2배리어막(105A)은 실리콘질화막 등의 질화막을 포함한다. 관통실리콘비아(102)는 구리를 이용하여 형성된다. 범프(107)는 구리를 포함하며, 바람직하게 Cu/Ni/Au를 적층하여 형성할 수 있다.As shown in FIG. 2, a semiconductor package according to an exemplary embodiment of the present invention includes a wafer 101B having a front surface A and a rear surface B and a through-hole embedded in a through hole 103 passing through the wafer 101B. The silicon bar 102 includes a bump 107 connected to one end of the through silicon via 102, that is, the rear surface thereof. The rear surface of the through silicon via 102 (see reference numeral 'C') protrudes a certain height from the surface (ie, the rear surface) of the wafer 101B, and the rear surface of the wafer 101B between the rear surfaces of the through silicon via 102. The barrier film pattern 106 is formed on the substrate. The barrier film pattern 106 is formed using an insulating film and includes a first barrier film 104A and a second barrier film 105A. The first barrier film 104A includes an oxide film such as a silicon oxide film. The second barrier film 105A includes a nitride film such as a silicon nitride film. The through silicon vias 102 are formed using copper. The bump 107 includes copper, and preferably, may be formed by stacking Cu / Ni / Au.

도 2에 따르면, 웨이퍼(101B)의 후면에서 돌출된 관통실리콘비아(102)의 주위에 배리어막패턴(106), 즉 제1배리어막(104A)과 제2배리어막(105A)을 포함하는 절연막이 형성되기 때문에, 관통실리콘비아(102)의 형태가 찌그러지더라도 웨이퍼(101B)와 범프(107)간의 브릿지가 발생하지 않는다.According to FIG. 2, an insulating film including a barrier film pattern 106, that is, a first barrier film 104A and a second barrier film 105A around the through silicon via 102 protruding from the back surface of the wafer 101B. Because of this formation, even if the shape of the through-silicon vias 102 is distorted, the bridge between the wafer 101B and the bump 107 does not occur.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 반도체 패키지 제조 방법을 도시한 도면이다.3A to 3F illustrate a method of manufacturing a semiconductor package according to an embodiment of the present invention.

도 3a에 도시된 바와 같이, 전면(A)과 후면(B)을 갖는 웨이퍼(101)의 전면을 관통하는 관통실리콘비아(102)를 형성한다. 관통실리콘비아(102)를 형성하기 위해 웨이퍼(101)의 전면(도면부호 'A' 참조)으로부터 일정 깊이 식각하여 관통홀(103)을 형성한다. 도전층을 이용하여 관통홀(103)을 매립한다. 여기서, 도전층은 금속층을 포함한다. 관통홀(103)에 매립되는 도전층은 관통실리콘비아(102)가 된다. 관통실리콘비아(102)는 구리(Cu)를 이용하여 형성할 수 있다. 관통실리콘비아(102)를 매립시키기 위하여 도전층은 CMP(Chemical Mechanical Polishing) 등을 이용하여 평탄화될 수 있다. 도시하지 않았지만, 관통실리콘비아(102)과 웨이퍼(101)간 절연을 위해 관통홀(103)의 측벽에 실리콘산화막 등의 절연층이 형성될 수 있다.As shown in FIG. 3A, a through-silicon via 102 penetrating the front surface of the wafer 101 having the front surface A and back surface B is formed. In order to form the through silicon vias 102, the through holes 103 are formed by etching a predetermined depth from the entire surface of the wafer 101 (see reference numeral 'A'). The through hole 103 is embedded using the conductive layer. Here, the conductive layer includes a metal layer. The conductive layer embedded in the through hole 103 becomes the through silicon via 102. The through silicon via 102 may be formed using copper (Cu). In order to fill the through silicon vias 102, the conductive layer may be planarized by using chemical mechanical polishing (CMP) or the like. Although not shown, an insulating layer such as a silicon oxide film may be formed on the sidewall of the through hole 103 to insulate the through silicon via 102 and the wafer 101.

도 3b에 도시된 바와 같이, 웨이퍼(101)의 후면(도면부호 'B' 참조)을 백그라인딩한다. 이로써 관통실리콘비아(102)의 전면부 및 후면부가 노출된다. 백그라인딩에 의해 웨이퍼를 도면부호 '101A'와 같이 얇게 한다. 백그라인딩 공정은 화학적기계적연마(CMP) 또는 건식식각을 이용할 수 있다.As shown in FIG. 3B, the backside of the wafer 101 (see reference numeral 'B') is backgrinded. This exposes the front and rear portions of the through silicon via 102. The wafer is thinned by back grinding as shown by reference numeral 101A. The backgrinding process may use chemical mechanical polishing (CMP) or dry etching.

위와 같은 백그라인딩 공정에 의해 관통실리콘비아(102)의 전면부 및 후면부가 노출된다. 여기서, 설명의 편의상 관통실리콘비아(102)의 전면부는 웨이퍼(101A)의 전면(A)에서 노출되는 부분이라 하고, 관통실리콘비아(102)의 후면부는 웨이퍼(101A)의 후면(B)에서 노출되는 부분이라 한다.The front part and the rear part of the through silicon via 102 are exposed by the back grinding process as described above. Here, for convenience of description, the front surface of the through silicon vias 102 is a portion exposed from the front surface A of the wafer 101A, and the rear surface of the through silicon vias 102 is exposed from the rear surface B of the wafer 101A. It is called a part.

도 3c에 도시된 바와 같이, 백그라인딩이 실시된 웨이퍼(101A)의 후면을 선택적으로 제거한다. 이로써, 관통실리콘비아(102)의 후면부가 일정 높이 돌출된다(도면부호 'C' 참조). 웨이퍼(101A)의 후면을 선택적으로 제거하기 위해 마스킹없이 건식식각이 사용된다. 건식식각은 에치백을 포함하며, 건식식각시 관통실리콘비아(102)는 선택비를 가져 식각되지 않는다. 에치백 공정에 의해 웨이퍼는 도면부호 '101B'와 같이 더 얇아진다.As shown in FIG. 3C, the back surface of the wafer 101A subjected to backgrinding is selectively removed. Thus, the rear portion of the through-silicon vias 102 protrudes a certain height (see reference numeral 'C'). Dry etching without masking is used to selectively remove the backside of the wafer 101A. The dry etching includes an etch back, and the through silicon via 102 during the dry etching is not etched due to the selectivity. By the etch back process, the wafer becomes thinner as shown by reference numeral 101B.

도 3d에 도시된 바와 같이, 노출된 관통실리콘비아(102)의 후면부를 포함한 웨이퍼(101B)의 후면에 제1배리어막(104)을 형성한다. 제1배리어막(104)은 실리콘산화막 등의 산화막을 이용한다.As shown in FIG. 3D, the first barrier film 104 is formed on the rear surface of the wafer 101B including the rear surface portion of the exposed through silicon via 102. The first barrier film 104 uses an oxide film such as a silicon oxide film.

이어서, 제1배리어막(104) 상에 웨이퍼(101B)의 후면을 덮는 제2배리어막(105)을 형성한다. 제2배리어막(105)은 제1배리어막(104)을 보호하고 완충 역할 및 측면으로의 구리 마이그레이션(Cu Migration)을 방지하는 물질을 포함한다. 예컨대, 제2배리어막(105)은 실리콘질화막 등의 질화막으로 형성한다. Subsequently, a second barrier film 105 covering the rear surface of the wafer 101B is formed on the first barrier film 104. The second barrier film 105 includes a material that protects the first barrier film 104 and prevents copper migration to the buffer role and side surfaces. For example, the second barrier film 105 is formed of a nitride film such as a silicon nitride film.

위와 같이, 본 발명의 실시예는 웨이퍼 후면의 백그라인딩이 완료된 이후에 에치백을 실시하고, 연속하여 제1배리어막(104) 및 제2배리어막(105)을 형성하므로써 관통실리콘비아(102)의 돌출된 후면부를 커버링한다. As described above, the embodiment of the present invention performs etch back after the backgrinding of the wafer back surface is completed, and subsequently forms the first barrier film 104 and the second barrier film 105 to form the through silicon vias 102. Cover the protruding back of the.

도 3e에 도시된 바와 같이, 제1,2배리어막(104, 105)에 대해 평탄화를 실시한다. 평탄화는 화학적기계적연마(CMP)를 이용하며 관통실리콘비아(102)의 후면부 표면이 노출될때까지 진행한다.As shown in FIG. 3E, planarization is performed on the first and second barrier films 104 and 105. Planarization utilizes chemical mechanical polishing (CMP) and proceeds until the backside surface of through silicon via 102 is exposed.

위와 같은 평탄화 공정에 의해 관통실리콘비아(102)의 후면부(도면부호 'C' 참조) 표면이 노출되고, 관통실리콘비아(102) 사이의 웨이퍼(101B)의 후면 상에는 배리어막패턴(106)이 잔류한다. 배리어막패턴(106)은 제1배리어막(104A)과 제2배리어막(105A)을 포함한다.Through the above planarization process, the surface of the back surface of the through silicon via 102 (see reference numeral 'C') is exposed, and the barrier layer pattern 106 remains on the back surface of the wafer 101B between the through silicon vias 102. do. The barrier film pattern 106 includes a first barrier film 104A and a second barrier film 105A.

배리어막패턴(106)은 관통실리콘비아(102)와 웨이퍼(101B)간의 브릿지를 방지하는 역할을 한다. 이는 배리어막패턴(106)이 산화막 및 질화막 등의 절연물질로 형성되기 때문에 가능하다.The barrier film pattern 106 serves to prevent the bridge between the through silicon vias 102 and the wafer 101B. This is possible because the barrier film pattern 106 is formed of an insulating material such as an oxide film and a nitride film.

도 3f에 도시된 바와 같이, 범프 공정을 진행한다. 이로써 관통실리콘비아(102)의 후면부에 접속되는 범프(107)가 형성된다. 범프(107)는 Cu/Ni/Au를 적층하여 형성할 수 있다. 범프(107)는 다른 반도체칩과 연결하기 위한 구조이다.As shown in FIG. 3F, the bump process is performed. As a result, a bump 107 connected to the rear portion of the through silicon via 102 is formed. The bump 107 may be formed by stacking Cu / Ni / Au. The bump 107 is a structure for connecting with another semiconductor chip.

도시하지 않았지만, 범프 공정 전에는 웨이퍼를 쏘잉하여 개별 반도체칩들로 분리시킨다. 그런 다음 분리된 반도체칩들을 적어도 둘이상 적층한다. 반도체칩들의 적층은 관통실리콘비아를 이용해서 물리적 및 전기적으로 연결된다.이로써, 기존의 와이어링(Wiring)보다 더 많은 양의 멀티칩 패키징(Multi chip pachaging)이 가능하다.Although not shown, the wafer is sawed and separated into individual semiconductor chips before the bump process. Then, at least two separated semiconductor chips are stacked. The stack of semiconductor chips is physically and electrically connected using through-silicon vias, which allows for higher amounts of multi-chip pachaging than conventional wiring.

상술한 실시예에 따르면, 관통실리콘비아(102)의 돌출된 후면부(C) 주위에 배리어막패턴(106), 즉 제1배리어막(104A)과 제2배리어막(105A)을 포함하는 절연층이 형성되기 때문에, 관통실리콘비아(102)의 형태가 찌그러지더라도 웨이퍼(101B)와 관통실리콘비아(102)간의 브릿지가 발생하지 않는다. 아울러, 오버레이마진(O/L Margin)을 개선할 수 있다.According to the above-described embodiment, the insulating layer including the barrier layer pattern 106, that is, the first barrier layer 104A and the second barrier layer 105A, is formed around the protruding rear surface portion C of the through silicon via 102. Because of this formation, even if the shape of the through-silicon vias 102 is distorted, a bridge between the wafer 101B and the through-silicon vias 102 does not occur. In addition, the overlay margin (O / L Margin) can be improved.

전술한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

101, 101A, 101B : 웨이퍼 102 : 관통실리콘비아
103 : 관통홀 104, 104A : 제1배리어막
105, 105A : 제2배리어막 106 : 배리어막패턴
107 : 범프101, 101A, 101B: wafer 102: through silicon via
103: through hole 104, 104A: first barrier film
105, 105A: second barrier film 106: barrier film pattern
107 bump

Claims (10)

웨이퍼;
상기 웨이퍼를 관통하며 후면부가 돌출된 관통실리콘비아;
상기 관통실리콘비아의 후면부 표면을 노출시키고 상기 웨이퍼의 후면 상에 형성된 배리어막; 및
상기 관통실리콘비아의 후면부에 연결된 범프
를 포함하는 반도체 패키지.
wafer;
A through silicon via penetrating the wafer and having a rear surface protruding from the wafer;
A barrier film formed on the back surface of the wafer to expose a back surface of the through silicon via; And
A bump connected to the rear portion of the through silicon via
Semiconductor package comprising a.
제1항에 있어서,
상기 배리어막은,
절연막을 포함하는 반도체 패키지.
The method of claim 1,
The barrier film,
A semiconductor package comprising an insulating film.
제1항에 있어서,
상기 배리어막은 제1배리어막과 제2배리어막을 포함하는 반도체 패키지.
The method of claim 1,
The barrier layer includes a first barrier layer and a second barrier layer.
제1항에 있어서,
상기 배리어막은 산화막과 질화막이 적층된 반도체 패키지.
The method of claim 1,
The barrier film is a semiconductor package in which an oxide film and a nitride film are stacked.
제1항에 있어서,
상기 범프는 구리를 포함하는 반도체 패키지.
The method of claim 1,
The bump includes a semiconductor package.
웨이퍼를 관통하는 복수의 관통실리콘비아를 형성하는 단계;
상기 웨이퍼의 후면을 선택적으로 제거하여 상기 관통실리콘비아의 후면부를 돌출시키는 단계;
상기 관통실리콘비아의 후면부를 포함한 상기 웨이퍼의 후면을 덮는 배리어막을 형성하는 단계;
상기 관통실리콘비아의 후면부 표면이 노출되도록 상기 배리어막을 평탄화하는 단계; 및
상기 관통실리콘비아의 후면부와 연결되는 범프를 형성하는 단계
를 포함하는 반도체 패키지 제조 방법.
Forming a plurality of through silicon vias through the wafer;
Selectively removing the back side of the wafer to project the back side of the through silicon via;
Forming a barrier film covering a back surface of the wafer including a back surface of the through silicon via;
Planarizing the barrier layer to expose a rear surface of the through silicon via; And
Forming a bump connected to a rear portion of the through silicon via
≪ / RTI >
제6항에 있어서,
상기 관통실리콘비아의 후면부를 돌출시키는 단계는,
상기 웨이퍼의 후면을 건식식각하는 반도체 패키지 제조 방법.
The method according to claim 6,
Protruding the rear portion of the through-silicon via,
A semiconductor package manufacturing method for dry etching the back of the wafer.
제6항에 있어서,
상기 배리어막을 형성하는 단계에서,
상기 배리어막은 절연막을 이용하여 형성하는 반도체 패키지 제조 방법.
The method according to claim 6,
In the step of forming the barrier film,
The barrier film is formed using an insulating film.
제6항에 있어서,
상기 배리어막을 형성하는 단계는,
상기 관통실리콘비아의 후면부를 포함한 상기 웨이퍼의 후면 상에 제1배리어막을 형성하는 단계; 및
상기 제1배리어막 상에 상기 관통실리콘비아의 후면부 사이를 갭필하는 제2배리어막을 형성하는 단계
를 포함하는 반도체 패키지 제조 방법.
The method according to claim 6,
Forming the barrier film,
Forming a first barrier film on a back side of the wafer including a back side portion of the through silicon via; And
Forming a second barrier film on the first barrier film, the second barrier film filling a gap between the rear surfaces of the through silicon vias;
≪ / RTI >
제9항에 있어서,
상기 제1배리어막은 산화막을 포함하고, 상기 제2배리어막은 질화막을 포함하는 반도체 패키지 제조 방법.10. The method of claim 9,
The first barrier film includes an oxide film, and the second barrier film includes a nitride film.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10109545B2 (en) 2014-03-19 2018-10-23 SK Hynix Inc. Semiconductor devices having through electrodes and methods of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10109545B2 (en) 2014-03-19 2018-10-23 SK Hynix Inc. Semiconductor devices having through electrodes and methods of manufacturing the same

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