CN116344438A - Packaging method and packaging structure - Google Patents

Packaging method and packaging structure Download PDF

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Publication number
CN116344438A
CN116344438A CN202111604680.4A CN202111604680A CN116344438A CN 116344438 A CN116344438 A CN 116344438A CN 202111604680 A CN202111604680 A CN 202111604680A CN 116344438 A CN116344438 A CN 116344438A
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China
Prior art keywords
wafer
dielectric layer
conductive
interconnection
electrically connected
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CN202111604680.4A
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Chinese (zh)
Inventor
马慧琳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202111604680.4A priority Critical patent/CN116344438A/en
Publication of CN116344438A publication Critical patent/CN116344438A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings

Abstract

A packaging method and a packaging structure, the packaging method comprises: providing a first wafer, wherein the first wafer comprises a first surface to be bonded; forming a plurality of first conductive columns penetrating through the first wafer and metal shielding columns, wherein the metal shielding columns are positioned between adjacent first conductive columns; providing a second wafer, wherein the second wafer comprises a second surface to be bonded, a first interconnection electrode and a second interconnection electrode are formed on the second surface to be bonded, the first interconnection electrode is used for electrically connecting devices in the second wafer, and the second electrode is grounded; and bonding the first wafer and the second wafer, wherein the first surface to be bonded is opposite to the second surface to be bonded, the first conductive column is electrically connected with the first interconnection electrode, and the metal shielding column is electrically connected with the second interconnection electrode. The invention is beneficial to reducing the situations of crosstalk and coupling noise generated when the first conductive column is electrically connected, thereby improving the reliability of the packaging structure.

Description

Packaging method and packaging structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a packaging method and a packaging structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed to have higher integration in order to achieve faster operation speed, larger data storage amount, and more functions. And the higher the integration of the semiconductor chip, the smaller the feature size (CD, critical Dimension) of the semiconductor device. MP3, mobile phones, digital cameras, among other products that are increasingly demanding in terms of storage, are seeking smaller package sizes and higher storage densities. High-end processors also require faster data access to and from memory. To accommodate the demands for performance and storage density, the semiconductor industry has moved from 2D packages to 3D packages with shorter electrical connections.
Through silicon vias (Through Silicon Via, TSVs) and related techniques are establishing 3D packaging processes. TSVs are the latest technology for achieving interconnection between chips by making vertical conduction between chips, between wafers and wafers. Unlike the conventional IC package bonding and stacking technology using bumps, the TSV can maximize the density of chip stacking in three dimensions, minimize the external dimensions, and greatly improve the chip speed and low power consumption performance.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a packaging method and a packaging structure, which are beneficial to improving the reliability of the packaging structure.
In order to solve the above problems, the present invention provides a package structure, comprising: a first wafer including a first bonding surface; a plurality of first conductive pillars penetrating the first wafer; the metal shielding columns are positioned between the adjacent first conductive columns and penetrate through the first wafer; the second wafer bonded on the first wafer comprises a second bonding surface, the second bonding surface is opposite to the first bonding surface, a first interconnection electrode and a second interconnection electrode are formed on the second bonding surface, the first interconnection electrode is electrically connected with a device in the second wafer, the second interconnection electrode is grounded, the first conductive column is electrically connected with the first interconnection electrode, and the metal shielding column is electrically connected with the second interconnection electrode.
Correspondingly, the embodiment of the invention also provides a packaging method, which comprises the following steps: providing a first wafer, wherein the first wafer comprises a first surface to be bonded; forming a plurality of first conductive pillars and metal shielding pillars penetrating through the first wafer, wherein the metal shielding pillars are positioned between adjacent first conductive pillars; providing a second wafer, wherein the second wafer comprises a second surface to be bonded, a first interconnection electrode and a second interconnection electrode are formed on the second surface to be bonded, the first interconnection electrode is used for electrically connecting devices in the second wafer, and the second electrode is grounded; and bonding the first wafer and the second wafer, wherein the first surface to be bonded is opposite to the second surface to be bonded, the first conductive column is electrically connected with the first interconnection electrode, and the metal shielding column is electrically connected with the second interconnection electrode.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a packaging structure, wherein metal shielding columns are positioned between adjacent first conductive columns and penetrate through a first wafer, first interconnection electrodes are electrically connected with devices in a second wafer, and the second electrodes are grounded; the first wafer is bonded with the second wafer, the first conductive columns are electrically connected with the first interconnection electrode, the metal shielding columns are electrically connected with the second interconnection electrode, so that current crosstalk between adjacent first conductive columns can be blocked through the metal shielding columns, moreover, the metal shielding columns are grounded through the second interconnection electrode, the current crosstalk can be led out, the situation that crosstalk and coupling noise occur when the first conductive columns are electrically connected is reduced, and reliability of the packaging structure is improved.
The embodiment of the invention provides a packaging method, which comprises the steps of forming a plurality of first conductive posts and metal shielding posts penetrating through a first wafer, wherein the metal shielding posts are positioned between adjacent first conductive posts, a first interconnection electrode is used for electrically connecting devices in a second wafer, and the second electrode is grounded; after the first wafer and the second wafer are bonded, the first conductive columns are electrically connected with the first interconnection electrode, the metal shielding columns are electrically connected with the second interconnection electrode, so that current crosstalk between adjacent first conductive columns can be blocked through the metal shielding columns, moreover, the metal shielding columns are grounded through the second interconnection electrode, the current crosstalk can be led out, the situation that crosstalk and coupling noise occur when the first conductive columns are electrically connected is reduced, and reliability of the packaging structure is improved.
Drawings
FIG. 1 is a schematic diagram of a package structure;
FIG. 2 is a schematic diagram of an embodiment of a package structure according to the present invention;
fig. 3 to 13 are schematic structural diagrams corresponding to each step in an embodiment of the packaging method of the present invention.
Detailed Description
The reliability of the current package structure needs to be improved. The reasons for the improvement of the reliability of the package structure are analyzed by combining the package structure.
Fig. 1 is a schematic structural diagram of a package structure.
The packaging structure comprises: a first wafer 10 including a first bonding surface 10c; a plurality of conductive pillars 13 penetrating the first wafer 10; the second wafer 70 bonded to the first wafer 10 includes a second bonding surface 70a, the second bonding surface 70a is opposite to the first bonding surface 10c, an interconnection electrode 71 is formed on the second bonding surface 70a, the interconnection electrode 71 is electrically connected to the device in the second wafer 70, and the conductive post 13 is electrically connected to the interconnection electrode 71.
By bonding the first wafer 10 and the second wafer 70 to perform 3D packaging, the conductive columns 13 are electrically connected with the devices of the second wafer 70 through the interconnection electrodes 71, so that current crosstalk is easy to occur between adjacent conductive columns 13 in the working process of the devices, coupling noise is generated, and reliability of the packaging structure is affected.
In order to solve the technical problem, an embodiment of the present invention provides a packaging method, including: providing a first wafer, wherein the first wafer comprises a first surface to be bonded; forming a plurality of first conductive columns penetrating through the first wafer and metal shielding columns, wherein the metal shielding columns are positioned between adjacent first conductive columns; providing a second wafer, wherein the second wafer comprises a second surface to be bonded, a first interconnection electrode and a second interconnection electrode are formed on the second surface to be bonded, the first interconnection electrode is used for electrically connecting devices in the second wafer, and the second electrode is grounded; and bonding the first wafer and the second wafer, wherein the first surface to be bonded is opposite to the second surface to be bonded, the first conductive column is electrically connected with the first interconnection electrode, and the metal shielding column is electrically connected with the second interconnection electrode.
After the first wafer and the second wafer are bonded, the first conductive columns are electrically connected with the first interconnection electrode, the metal shielding columns are electrically connected with the second interconnection electrode, so that current crosstalk between adjacent first conductive columns can be blocked through the metal shielding columns, in addition, the metal shielding columns are grounded through the second interconnection electrode, the current crosstalk can be led out, the situation that crosstalk and coupling noise occur when the first conductive columns are electrically connected can be reduced, and therefore reliability of the packaging structure is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 is a schematic structural diagram of an embodiment of a package structure according to the present invention.
The packaging structure comprises: a first wafer 101 including a first bonding surface 101c; a plurality of first conductive pillars 131 penetrating the first wafer 101; the metal shielding columns 141 are located between adjacent first conductive columns 131 and penetrate through the first wafer 101; the second wafer 701 bonded to the first wafer 101 includes a second bonding surface 701a, the second bonding surface 701a is opposite to the first bonding surface 101c, a first interconnection electrode 711 and a second interconnection electrode 721 are formed on the second bonding surface 701a, the first interconnection electrode 711 is electrically connected to a device in the second wafer 701, the second electrode 721 is grounded, the first conductive pillar 131 is electrically connected to the first interconnection electrode 711, and the metal shielding pillar 141 is electrically connected to the second interconnection electrode 721.
In this embodiment, the package structure is a wafer level package structure, so that the package efficiency and reliability of the obtained package structure are improved.
The first wafer 101 is a wafer for completing device fabrication, and is used for being vertically conducted with the second wafer 701, the first wafer 101 is electrically connected with the second wafer 701, and meanwhile, the electrical property of the device of the second wafer 701 is led out, so that 3D packaging between the wafers is realized.
In this embodiment, the material of the first wafer 101 includes silicon. In other embodiments, the material of the first wafer may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the first wafer may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the first wafer may be a material suitable for process requirements or easy integration.
In this embodiment, the first wafer 101 includes a first bonding surface 101c. The first bonding surface 101c is a surface facing the second wafer 701 after the first wafer 101 is bonded to the second wafer 701.
In this embodiment, the first wafer 101 includes a front wafer surface 101a and a back wafer surface 101b that are opposite, and any one of the front wafer surface 101a and the back wafer surface 101b serves as the first bonding surface 101c. The front surface 101a refers to a surface of the first wafer 101 on which a circuit structure is formed, and the back surface 101b refers to a surface of the first wafer 101 on which a substrate is exposed.
That is, both the wafer front side 101a and the wafer back side 101b of the first wafer 101 may bond with the second wafer 701.
In this embodiment, the wafer back surface 101b is used as the first bonding surface 101c.
The first conductive pillars 131 penetrate the first wafer 101, so that vertical conduction of circuits at both ends of the first wafer 101 can be achieved through the first conductive pillars 131, that is, electrical connection with other circuits can be achieved through the wafer front surface 101a and the wafer back surface 101 b.
In this embodiment, the first conductive pillar 131 is a Through-Silicon-Via (TSV) structure. The TSV structure enables the stacking density of the wafers in the three-dimensional direction to be larger, the overall dimension to be smaller, the chip speed to be greatly improved, and the chip power consumption to be reduced.
In this embodiment, the material of the first conductive pillar 131 includes Cu, co, or W.
The better conductivity of Cu, co or W is advantageous for making the first conductive pillars 131 better electrically connect the two-terminal circuits.
The metal shielding columns 141 are located between the adjacent first conductive columns 131 and penetrate through the first wafer 101, the first wafer 101 is bonded with the second wafer 701, the first conductive columns 131 are electrically connected with the first interconnection electrode 711, so that current crosstalk between the adjacent first conductive columns 131 can be blocked through the metal shielding columns 141, the situation that crosstalk and coupling noise occur when the first conductive columns 131 are electrically connected is reduced, and reliability of the packaging structure is improved.
In this embodiment, the material of the metal shielding pillar 141 includes Cu, co, or W.
Cu, co or W are metal materials, when the adjacent first conductive columns 131 are mutually influenced to generate crosstalk current, the crosstalk current flows away through the metal materials, and the adjacent first conductive columns 131 are not influenced any more, so that the conditions of crosstalk and coupling noise generated when the first conductive columns 131 are electrically connected are reduced.
Also, cu, co, or W is the same as the material of the first conductive pillars 131, the metal shield pillars 141 may be formed in the same step as the first conductive pillars 131, improving process efficiency and also improving process compatibility in forming the metal shield pillars 141.
It should be noted that, the distance between the adjacent first conductive pillars 131 and the metal shielding pillar 141 should not be too large or too small. If the distance between the adjacent first conductive pillars 131 and the metal shielding pillars 141 is too large, the size of the metal shielding pillars 141 located between the adjacent first conductive pillars 131 is easily caused to be too small, which is contrary to the design criteria, and it is difficult to ensure the blocking performance of the metal shielding pillars 141 against the current crosstalk of the adjacent first conductive pillars 131, and the area waste of the first wafer 101 is also easily caused; if the distance between the adjacent first conductive pillars 131 and the metal shielding pillars 141 is too small, the design criteria are not met, and when the first conductive pillars 131 and the metal shielding pillars 141 are formed, the adjacent first conductive pillars 131 and the metal shielding pillars 141 are easily contacted due to too small process windows of photolithography and etching processes, so that the conduction of the circuit structures at the two ends of the first conductive pillars 131 is affected, and the working performance of the package structure is affected. For this reason, in the present embodiment, the pitch between adjacent first conductive pillars 131 and metal shielding pillars 141 is 3 μm to 18 μm.
The second wafer 701 is a wafer for completing device fabrication, and the second wafer 701 may be fabricated by using an integrated circuit fabrication technology, where devices in the second wafer 701 are electrically connected to circuit structures in the first wafer 101, so as to implement normal functions of the package structure.
For convenience of illustration, the devices formed in the second wafer 701 are not shown in this embodiment.
In this embodiment, the second wafer 701 includes a second bonding surface 701a, and the bonding between the first wafer 101 and the second wafer 701 is achieved by the second bonding surface 701a and the first bonding surface 101c being disposed opposite to each other.
In this embodiment, bonding is achieved by hybrid bonding, i.e., silicon oxide-silicon nitride, copper-copper, and copper-silicon nitride hybrid bonding. In other embodiments, bonding may also be accomplished using other bonding means, such as, for example, bonding in the form of a silica-silica fusion bond.
The first interconnect electrode 711 is electrically connected to the devices in the second wafer 701 for electrically extracting the devices in the second wafer 701.
The first conductive pillars 131 are electrically connected to the first interconnect electrodes 711, and the first conductive pillars 131 are electrically connected to devices in the second wafer 701.
In this embodiment, the material of the first interconnect electrode 711 is a conductive material. In this embodiment, the material of the first interconnect electrode 711 includes: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, and has better conductive effect.
The second interconnect electrode 721 is grounded and electrically connected to the metal shield post 141 for achieving the grounding of the metal shield post 141.
In this embodiment, the metal shielding pillar 141 is grounded through the second interconnection electrode 721, so that current crosstalk can be led out, which is further beneficial to reducing the occurrence of crosstalk and coupling noise when the first conductive pillar 131 is electrically connected, thereby improving the reliability of the package structure.
In this embodiment, the material of the second interconnect electrode 721 is a conductive material. In this embodiment, the material of the second interconnect electrode 721 includes: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, and has better conductive effect.
In this embodiment, the package structure further includes: the second dielectric layer 601 covers the first bonding surface 101c.
The second dielectric layer 601 covers the first bonding surface 101c for isolating the bonded first wafer 101 and second wafer 701, and the second dielectric layer 601 is further used as a process platform for forming the third interconnect electrode and the fourth interconnect electrode, and isolating adjacent third interconnect electrode and fourth interconnect electrode.
In this embodiment, the wafer back surface 101b is used as the first bonding surface 101c, and the second dielectric layer 601 covers the wafer back surface 101b.
In this embodiment, the second dielectric layer 601 is made of a dielectric material including SiO 2 One or more of SiN and SiON.
In this embodiment, the package structure further includes: the third interconnection electrode 611 penetrates the second dielectric layer 601 and is electrically connected to the first conductive pillar 131, and the first interconnection electrode 711 is disposed opposite to and electrically connected to the third interconnection electrode.
The third interconnection electrode 611 leads out the electrical property of the first conductive post 131, and serves as an external electrode of the first conductive post 131, thereby electrically connecting the first conductive post 131 and the first interconnection electrode 711.
In this embodiment, the material of the third interconnection electrode 611 is a conductive material. In this embodiment, the material of the third interconnect electrode 611 includes: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, and has better conductive effect.
In this embodiment, the package structure further includes: the fourth interconnect electrode 621 penetrates the second dielectric layer 601 and is electrically connected to the metal shield 141, and the second interconnect electrode 721 is disposed opposite to and electrically connected to the fourth interconnect electrode 621.
The fourth interconnection electrode 621 electrically leads out the metal shielding pillar 141 as an external electrode of the metal shielding pillar 141, and electrically connects the metal shielding pillar 141 and the second interconnection electrode 721.
In this embodiment, the material of the fourth interconnect electrode 621 is a conductive material. In this embodiment, the material of the fourth interconnect electrode 621 includes: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, and has better conductive effect.
In this embodiment, the package structure further includes: the first dielectric layer 201 is located on the wafer front surface 101a of the first wafer 101.
The first dielectric layer 201 is used as a process platform for forming the first interconnect structure and the second interconnect structure, and isolates adjacent first interconnect structures from the second interconnect structures.
In this embodiment, the first dielectric layer 201 is made of dielectric material including SiO 2 One or more of SiN and SiON.
In this embodiment, the package structure further includes: the first interconnection structure 401 penetrates through the first dielectric layer 201, and the first interconnection structure 401 is located on top of the first conductive pillar 131 and is electrically connected with the first conductive pillar 131.
The first interconnection structure 401 leads out the electrical property of the first conductive pillar 131, and realizes the electrical connection between the first conductive pillar 131 and an external circuit.
A second interconnect structure 301 extends through the first dielectric layer 201, and the second interconnect structure 301 is located on top of the metal shield 141 and is electrically connected to the metal shield 141.
The second interconnection structure 301 leads out the electrical property of the metal shielding column 141, and realizes the electrical connection between the metal shielding column 141 and an external circuit.
In this embodiment, the first dielectric layer 201 includes a first bottom dielectric layer 211 covering the front surface 101a of the wafer, and a first top dielectric layer 231 covering the first bottom dielectric layer 211.
The first bottom dielectric layer 211 is used as a process platform for forming the sub-interconnect structure and the second conductive pillars and to isolate adjacent sub-interconnect structures from the second conductive pillars.
The first top dielectric layer 231 is used as a process mesa for forming the fifth interconnect electrode and the sixth interconnect electrode and to isolate adjacent fifth interconnect electrode and sixth interconnect electrode.
Correspondingly, the first bottom dielectric layer 211 is a dielectric material comprising SiO 2 One or more of SiN and SiON, the first top dielectric layer 231 is a dielectric material comprising SiO 2 SiN and SiON.
In this embodiment, the first interconnect structure 401 includes: the second conductive pillar 411 is located at the top of the first conductive pillar 131 and penetrates through the first bottom dielectric layer 211, and the projection of the second conductive pillar 411 on the top surface of the first conductive pillar 131 coincides with the top surface of the first conductive pillar 131.
The second conductive pillars 411 are used for electrically leading out the first conductive pillars 131, so that electrical connection between the first conductive pillars 131 and other wafers can be achieved through the wafer front surface 101a of the first wafer 101, and 3D packaging through the first conductive pillars 131 is achieved.
In this embodiment, the projection of the second conductive post 411 on the top surface of the first conductive post 131 coincides with the top surface of the first conductive post 131, so that the second conductive post 411 and the first conductive post 131 can form an integrated structure, which is beneficial to making the current flow through the first conductive post 131 and the second conductive post 411 relatively uniform when the device works, and is beneficial to ensuring the reliability of the electrical connection of the circuit structures at two ends through the first conductive post 131 and the second conductive post 411.
In this embodiment, the material of the second conductive pillar 411 includes Cu, co, or W.
The better conductivity of Cu, co or W is advantageous for making the second conductive pillars 411 better electrically connect the two-terminal circuit structures.
In this embodiment, the first interconnect structure 401 further includes: the fifth interconnection electrode 421 penetrates the first top dielectric layer 231 and is electrically connected to the second conductive post 411.
The fifth interconnection electrode 421 leads out the electrical property of the second conductive column 411, and is used as an external electrode of the second conductive column 411, so as to realize the electrical connection between the second conductive column 411 and an external circuit.
In this embodiment, the material of the fifth interconnection electrode 421 is a conductive material. In this embodiment, the materials of the fifth interconnection electrode 421 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and has better conductive effect.
In this embodiment, the second interconnect structure 301 includes: the sub-interconnection structure 311 is located on top of the metal shielding pillar 141 and penetrates through the first bottom dielectric layer 211, and the sub-interconnection structure 311 is electrically connected with the metal shielding pillar 141.
The sub-interconnection structure 311 is used for electrically leading out the metal shielding pillar 141, so that the grounding of the metal shielding pillar 141 can be achieved through the wafer front surface 101a of the first wafer 101.
In this embodiment, the circuit structure electrically connected to the devices in the first wafer 101 is also formed on the wafer front surface 101a of the first wafer 101, and the circuit structure may be formed together with the sub-interconnect structure 311, so in this embodiment, the sub-interconnect structure 311 is identical to the circuit structure, which is beneficial to improving the process compatibility of forming the sub-interconnect structure 311.
In this embodiment, the material of the sub-interconnect structure 311 is a conductive material. In this embodiment, the materials of the sub-interconnect structure 311 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, and has better conductive effect.
In this embodiment, the second interconnect structure 301 further includes: the sixth interconnect electrode 431 penetrates the first top dielectric layer 231 and is electrically connected to the sub-interconnect structure 311.
The sixth interconnect electrode 431 leads out the electrical property of the sub-interconnect structure 311, and is used as an external electrode of the sub-interconnect structure 311 to realize the electrical connection between the sub-interconnect structure 311 and an external circuit.
In this embodiment, the material of the sixth interconnect electrode 431 is a conductive material. In this embodiment, the materials of the sixth interconnect electrode 431 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, and has better conductive effect.
Fig. 3 to 13 are schematic structural diagrams corresponding to each step in an embodiment of the packaging method of the present invention.
Referring to fig. 3, a first wafer 100 is provided, the first wafer 100 including a first surface to be bonded 100c.
The first wafer 100 is used for bonding with a wafer to be integrated in a subsequent process.
The first wafer 100 has a circuit structure, after the bonding of the first wafer 100 and the second wafer is realized, the second wafer can be electrically connected with the circuit structure in the first wafer 100, so that the normal function of the packaging structure is realized, the first wafer 100 is also used for realizing vertical conduction with the second wafer, and the electrical property of the device of the second wafer is led out, so that the 3D packaging between the wafers is realized.
In this embodiment, the packaging method is a wafer level packaging structure, so that the packaging efficiency and reliability of the obtained packaging structure are improved.
In this embodiment, the material of the first wafer 100 includes silicon. In other embodiments, the material of the first wafer may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the first wafer may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the first wafer may be a material suitable for process requirements or easy integration.
In this embodiment, the first wafer 100 includes a first bonding surface 100c. The first bonding surface 101c is a surface facing the second wafer after the first wafer 100 is bonded with the second wafer.
In this embodiment, the first wafer 100 includes a front wafer surface 100a and a back wafer surface 100b, which are opposite to each other, and any one of the front wafer surface 100a and the back wafer surface 100b serves as the first bonding surface 100c. The front surface 100a refers to a surface of the first wafer 100 on which a circuit structure is formed, and the back surface 100b refers to a surface of the first wafer 100 on which a substrate is exposed.
That is, both the wafer front side 100a and the wafer back side 100b of the first wafer 100 may bond to the second wafer.
In this embodiment, the wafer back surface 100b is used as the first bonding surface 100c.
Referring to fig. 4 to 10 in combination, a plurality of first conductive pillars 130 and metal shielding pillars 140 penetrating the first wafer 100 are formed, and the metal shielding pillars 140 are located between adjacent first conductive pillars 130.
The first conductive pillars 130 penetrate through the first wafer 100, so that vertical conduction of the circuit structures at both ends of the first wafer 100 can be achieved through the first conductive pillars 130.
In this embodiment, the first conductive pillar 130 is a through-silicon via structure. The TSV structure enables the stacking density of the wafers in the three-dimensional direction to be larger, the overall dimension to be smaller, the chip speed to be greatly improved, and the chip power consumption to be reduced.
In this embodiment, the material of the first conductive pillar 130 includes Cu, co, or W.
The better conductivity of Cu, co or W is advantageous for better electrical connection of the two-terminal circuit structure by the first conductive pillars 130.
After the first wafer 100 is bonded to the second wafer, the first conductive columns 130 are electrically connected to the first interconnection electrode, so that current crosstalk between adjacent first conductive columns 130 can be blocked by the metal shielding columns 140, which is beneficial to reducing the occurrence of crosstalk and coupling noise when the first conductive columns 130 are electrically connected, thereby improving the reliability of the packaging structure.
In this embodiment, the material of the metal shielding pillar 140 includes Cu, co, or W.
Cu, co or W are metal materials, when the adjacent first conductive columns 130 are mutually influenced to generate crosstalk current, the crosstalk current flows away through the metal materials, and the adjacent first conductive columns 130 are not influenced any more, so that the conditions of crosstalk and coupling noise generated when the first conductive columns 130 are electrically connected are reduced.
Also, cu, co, or W is the same as the material of the first conductive pillars 130, the metal shield pillars 140 may be formed in the same step as the first conductive pillars 130, improving process efficiency and process compatibility in forming the metal shield pillars 140.
It should be noted that, the distance between the adjacent first conductive pillars 130 and the metal shielding pillars 140 should not be too large or too small. If the distance between the adjacent first conductive pillars 130 and the metal shielding pillars 140 is too large, the size of the metal shielding pillars 140 located between the adjacent first conductive pillars 130 is easily caused to be too small, which is contrary to the design rule, and it is difficult to ensure the blocking performance of the metal shielding pillars 140 to the current crosstalk of the adjacent first conductive pillars 130, and the area waste of the first wafer 101 is also easily caused; if the distance between the adjacent first conductive pillars 130 and the metal shielding pillars 140 is too small, the design criteria are not met, and when the first conductive pillars 130 and the metal shielding pillars 140 are formed, the adjacent first conductive pillars 130 and the metal shielding pillars 140 are easily contacted due to too small process windows of photolithography and etching, so that the conduction of the circuit structures at the two ends of the first conductive pillars 130 is affected, and the working performance of the package structure is affected. For this reason, in the present embodiment, the pitch between adjacent first conductive pillars 130 and metal shielding pillars 140 is 3 μm to 18 μm.
Specifically, referring to fig. 4, the step of forming a plurality of first conductive pillars 130 and metal shielding pillars 140 throughout the first wafer 100 includes: a plurality of first trenches 110 and second trenches 120 are formed in the wafer front surface 100a in the first wafer 100, the second trenches 120 being located between adjacent first trenches 110.
The first trench 110 is used to provide a spatial location for forming the first conductive post 130 and the second trench 120 is used to provide a spatial location for forming the metal shielding post 140.
In this embodiment, in the same step, the plurality of first trenches 110 and second trenches 120 located in the first wafer 100 are formed, which improves the process efficiency, is also beneficial to improving the process compatibility of forming the second trenches 120, and is also beneficial to forming the first trenches 110 and the second trenches 120 with better depth uniformity, so that the heights of the first conductive pillars 130 and the metal shielding pillars 140 are correspondingly better, and thus, when the back surface of the first wafer 100 is thinned later, the first conductive pillars 130 and the metal shielding pillars 140 are beneficial to be exposed at the same time, and the process of exposing the first conductive pillars 130 and the metal shielding pillars 140 is not excessively complex. In addition, in the same step, the first trenches 110 and the second trenches 120 located in the first wafer 100 are formed, which can be prepared by adopting the same Zhang Guangzhao, so that the process cost is saved, and meanwhile, in the same Zhang Guang cover, the distance between the adjacent first conductive pillars 130 and the metal shielding pillars 140 can be well controlled, which is beneficial to forming the first conductive pillars 130 and the metal shielding pillars 140 with accurate positions.
In this embodiment, the first conductive pillars 130 are formed from the front surface 100a of the wafer, and in other embodiments, the first conductive pillars may be formed from the back surface of the wafer according to actual process requirements.
In this embodiment, an anisotropic etching process is used to form a plurality of first trenches 110 and second trenches 120 in the first wafer 100.
The anisotropic etching process is an anisotropic dry etching process, the anisotropic dry etching process is selected, the longitudinal etching rate is far greater than the transverse etching rate, quite accurate pattern conversion can be obtained, the anisotropic dry etching process is more directional, the shape quality and the dimensional accuracy of the side walls of the formed first groove 110 and the formed second groove 120 are improved, the process parameters can be well controlled by the anisotropic dry etching process, the process controllability is high, and the depth of the formed first groove 110 and second groove 120 is easy to control.
Referring to fig. 5, filling the first trench 110 forms a first conductive pillar 130; filling the second trench 120 forms a metal shield pillar 140.
In this embodiment, in the same step, the first trench 110 and the second trench 120 are filled to form the first conductive pillar 130 and the metal shielding pillar 140, which improves the process efficiency and is also beneficial to improving the process compatibility of forming the second trench 120.
In this embodiment, the first trench 110 and the second trench 120 are filled by a physical vapor deposition process, so as to form the first conductive pillar 130 and the metal shielding pillar 140.
The physical vapor deposition process has a good deposition effect, has a high gap filling capability, can form a film structure with high quality, and can reduce the gaps in the first conductive column 130 and the metal shielding column 140.
Referring to fig. 6 to 8 in combination, after forming the first conductive pillars 130 and the metal shielding pillars 140, before performing the subsequent back-side thinning treatment on the wafer back side 100b, the packaging method further includes: a first dielectric layer 200 covering the front surface 100a of the wafer, and a first interconnect structure 400 and a second interconnect structure 300 located in the first dielectric layer 200 and penetrating the first dielectric layer 200 are formed, the first interconnect structure 400 is located on top of the first conductive pillars 130 and electrically connected to the first conductive pillars 130, and the second interconnect structure 300 is located on top of the metal shield pillars 140 and electrically connected to the metal shield pillars 140.
The first dielectric layer 200 is used to isolate the phase-bonded first wafer 100 from other wafers when other wafers are bonded to the wafer front side 100a of the first wafer 100, and the first dielectric layer 200 is also used as a process platform for forming the first interconnect structure 400 and the second interconnect structure 300, and to isolate adjacent first interconnect structure 400 and second interconnect structure 300.
In this embodiment, the first dielectric layer 200 is made of dielectric material including SiO 2 One or more of SiN and SiON.
The first interconnection structure 400 leads out the electrical property of the first conductive pillar 130, so as to realize the electrical connection between the first conductive pillar 130 and the external circuit.
The second interconnection structure 300 leads out the electrical property of the metal shielding pillar 140, and realizes the electrical connection between the metal shielding pillar 140 and an external circuit.
It should be noted that in the embodiment, in the step of forming the first interconnection structure 400 and the second interconnection structure 200 penetrating through the first dielectric layer 200 in the first dielectric layer 200, a circuit structure for electrically connecting devices in the first wafer 100 is further formed in the first dielectric layer 200, and the forming step of the second interconnection structure 300 may be unified with the forming step of the circuit structure correspondingly, that is, the second interconnection structure 300 is formed simultaneously by using the process of forming the circuit structure, which is favorable for improving the process compatibility of forming the second interconnection structure 300, improving the packaging efficiency and saving the process cost.
Specifically, referring to fig. 6, the step of forming the first dielectric layer 210, and the first and second interconnect structures 400 and 300 includes: a first bottom dielectric layer 210 is formed overlying the wafer front side 100 a.
The first bottom dielectric layer 210 serves as a process platform for forming the second bottom interconnect structure and the second conductive pillars and isolates adjacent second bottom interconnect structures from the second conductive pillars.
Correspondingly, the first bottom dielectric layer 210 is a dielectric material comprising SiO 2 One or more of SiN and SiON.
With continued reference to fig. 6, a second bottom interconnect structure 310 is formed on top of the metal shield 140, electrically connected to the metal shield 140, and extending through the first bottom dielectric layer 210.
The second bottom interconnect structure 310 is used to electrically lead out the metal shield 140.
Accordingly, the second bottom interconnect structure 310 is formed in conjunction with the process of forming the circuit structure in the first bottom dielectric layer 210, and thus, in this embodiment, the second bottom interconnect structure 310 includes stacked sub-interconnect structures including metal plugs and metal lines on top of the metal plugs.
In this embodiment, the material of the second bottom interconnection structure 310 is a conductive material. In this embodiment, the materials of the second bottom interconnect structure 310 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, and has better conductive effect.
Referring to fig. 7, a first middle dielectric layer 220 is formed overlying the first bottom dielectric layer 210 and the second bottom interconnect structure 310.
The first middle dielectric layer 220 serves as a process platform for forming the second top interconnect structure and the second conductive pillars and isolates adjacent second top interconnect structures from the second conductive pillars.
Correspondingly, the first middle dielectric layer 220 is a dielectric material comprising SiO 2 One or more of SiN and SiON.
With continued reference to fig. 7, a second conductive pillar 410 is formed on top of the first conductive pillar 130, extending through the first bottom dielectric layer 210 and the first middle dielectric layer 220, with the projection of the second conductive pillar 410 onto the top surface of the first conductive pillar 130 coinciding with the top surface of the first conductive pillar 130.
The second conductive pillars 410 are used for electrically leading out the first conductive pillars 130, so that electrical connection between the first conductive pillars 130 and other wafers can be achieved through the wafer front surface 100a of the first wafer 100, thereby achieving 3D packaging through the first conductive pillars 130.
In this embodiment, the projection of the second conductive pillar 410 on the top surface of the first conductive pillar 130 coincides with the top surface of the first conductive pillar 130, so that the second conductive pillar 410 and the first conductive pillar 130 may form an integral structure. In other embodiments, the same interconnection structure as the second interconnection structure may also be formed on the top of the first conductive pillar according to actual process requirements.
In this embodiment, the material of the second conductive pillar 410 includes Cu, co, or W.
The better conductivity of Cu, co or W is advantageous for making the second conductive pillars 410 better electrically connect the two-terminal circuit structures.
Referring to fig. 8, a first top dielectric layer 230 is formed overlying the first middle dielectric layer 220 and the second conductive pillars 410.
The first top dielectric layer 230 serves as a process platform for forming the second top interconnect structure and the fifth interconnect electrode and isolates adjacent second top interconnect structures and fifth interconnect electrodes.
Correspondingly, the first top dielectric layer 220 is a dielectric material comprising SiO 2 One or more of SiN and SiON.
With continued reference to fig. 8, a fifth interconnect electrode 420 covering the second conductive pillar 410, and a second top interconnect structure 320 electrically connecting the second bottom interconnect structure 310 are formed in the first top dielectric layer 230, the first top dielectric layer 230 exposing the fifth interconnect electrode 420 and the second top interconnect structure 320, the second conductive pillar 410 and the fifth interconnect electrode 420 constituting the first interconnect structure 400, the second top interconnect structure 320 of the second bottom interconnect structure 310 constituting the second interconnect structure 300.
The fifth interconnection electrode 420 is used for leading out the electrical property of the second conductive pillar 410, and is used as an external electrode of the second conductive pillar 410, so as to realize the electrical connection between the second conductive pillar 410 and an external circuit.
In this embodiment, the material of the fifth interconnection electrode 420 is a conductive material. In this embodiment, the materials of the fifth interconnection electrode 420 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and has better conductive effect.
The second top interconnection structure 320 is used for electrically leading out the second bottom interconnection structure 310, and is used as an external electrode of the second bottom interconnection structure 310 to electrically connect the second bottom interconnection structure 310 and an external circuit.
It should be noted that, the second top interconnection structure 320 is also formed by using the steps of forming the circuit structures in the first middle dielectric layer 220 and the first top dielectric layer 230 together, so that the second top interconnection structure 320 includes a metal plug and a metal line located on top of the metal plug, in this embodiment, after the first middle dielectric layer 220 and the first top dielectric layer 230 are formed, the second top interconnection structure 320 is formed, and a dual damascene process can be used to form the second top interconnection structure 320 in the same step, thereby saving the process time and improving the process efficiency. In other embodiments, after the first middle dielectric layer is formed, a metal plug located in the first middle dielectric layer is formed, then the first top dielectric layer is formed, and then a metal wire located at the top of the metal plug is formed.
In this embodiment, the material of the second top interconnect structure 320 is a conductive material. In this embodiment, the materials of the second top interconnect structure 320 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and has better conductive effect.
Referring to fig. 9, before the subsequent back side thinning process is performed on the wafer back side 100b, the method further includes: a carrier substrate 500 is provided, the carrier substrate 500 comprising a carrier surface 500a.
The back side thinning process is required to be performed on the wafer back side 100b, the carrier substrate 500 is used for providing support during the back side thinning process, and the wafer front side 100a of the first wafer 100 faces the carrier substrate 500, so that the circuit structure of the wafer front side 100a is protected from being polluted during the back side thinning process.
In this embodiment, the carrier substrate 500 is a wafer. In other embodiments, the carrier substrate may also be a glass substrate.
Referring to fig. 9 and 10 in combination, the packaging method further includes: the wafer back side 100b is subjected to a back side thinning process to expose the first conductive pillars 130 and the metal shielding pillars 140.
In this embodiment, the back side 100b of the wafer is subjected to a back side thinning (backside grinding) process and a back side contact hole exposing (backside via reveal, BVR) process, and the redundant material is removed until the first conductive pillars 130 and the metal shielding pillars 140 are exposed, so as to prepare for electrically connecting the first conductive pillars 130 and the metal shielding pillars 140 with the circuit structures in the second wafer after the second wafer is bonded on the back side 100b of the wafer.
Specifically, referring to fig. 9, the step of performing the back side thinning process on the wafer back side 100b includes: the first wafer 100 is bonded to the carrier substrate 500, and the carrier surface 500a is opposite to the wafer front surface 100 a.
The first wafer 100 and the carrier substrate 500 are temporarily bonded, and the carrier substrate 500 faces the wafer front surface 100a, that is, the carrier substrate 500 is bonded to the wafer front surface 100a of the first wafer 100, so that the wafer back surface 100b of the first wafer 100 can be exposed, and the back surface thinning process can be performed.
Referring to fig. 10, after the first wafer 100 is bonded to the carrier substrate 500, the back side thinning process is performed on the first wafer 100 through the wafer back side 100 b.
The carrier substrate 500 is bonded to the front wafer surface 100a of the first wafer 100, so that the back surface of the first wafer 100 is thinned by the back wafer surface 100b, and the carrier substrate 500 protects the circuit structure of the front wafer surface 100a of the first wafer from contamination.
Referring to fig. 11, after forming the first conductive pillars 130 and the metal shielding pillars 140, the packaging method further includes, before subsequently bonding the first wafer 100 with the second wafer: a second dielectric layer 600 is formed overlying the first to-be-bonded face 100 c.
The second dielectric layer 600 covers the first surface to be bonded 100c for isolating the first wafer 100 and the second wafer that are subsequently bonded, and the second dielectric layer 600 is further used as a process platform for forming the third interconnect electrode and the fourth interconnect electrode, and isolates adjacent third interconnect electrode and fourth interconnect electrode.
In this embodiment, the wafer back surface 100b is used as the first surface to be bonded 100c, and the second dielectric layer 600 covers the wafer back surface 100b. Specifically, after the back surface thinning process, the second dielectric layer 600 is formed to cover the first surface to be bonded 100 c.
In this embodiment, the second dielectric layer 600 is made of dielectric material including SiO 2 One or more of SiN and SiON.
With continued reference to fig. 11, a third interconnect electrode 610 covering the first conductive pillars 130 and a fourth interconnect electrode 620 covering the metal shield pillars 140 are formed in the second dielectric layer 600.
The third interconnection electrode 610 leads out the electrical property of the first conductive pillar 130, and is used as an external electrode of the first conductive pillar 130, and then bonds the first wafer 100 with the second wafer, so as to realize the electrical connection of the circuit structures in the first conductive pillar 130 and the second wafer.
In this embodiment, the material of the third interconnection electrode 610 is a conductive material. In this embodiment, the material of the third interconnection electrode 610 includes: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and has better conductive effect.
The fourth interconnection electrode 620 leads out the electrical property of the metal shielding pillar 140, and is used as an external electrode of the metal shielding pillar 140, and then bonds the first wafer 100 with the second wafer, so as to electrically connect the metal shielding pillar 140 and the circuit structure in the second wafer.
In this embodiment, the material of the fourth interconnection electrode 620 is a conductive material. In this embodiment, the materials of the fourth interconnection electrode 620 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and has better conductive effect.
Referring to fig. 12, a second wafer 700 is provided, the second wafer 700 includes a second surface to be bonded 700a, a first interconnection electrode 710 and a second interconnection electrode 720 are formed on the second surface to be bonded 700a, the first interconnection electrode 710 is used for electrically connecting devices in the second wafer 700, and the second interconnection electrode 720 is grounded.
The second wafer 700 is a wafer for completing device fabrication, and the second wafer 700 may be fabricated by using an integrated circuit fabrication technology, where devices in the second wafer 700 are electrically connected to circuit structures in the first wafer 100, so as to implement normal functions of the package structure.
In this embodiment, the structures of the NMOS device, the PMOS device, and the like, and the dielectric layer and the metal interconnect line formed on the devices in the second wafer 700 are formed by deposition, etching, and the like.
For convenience of illustration, the devices formed in the second wafer 700 are not shown in this embodiment.
In this embodiment, the second wafer 700 includes a second surface 700a to be bonded. The second surface 700a to be bonded is a surface facing the first wafer 100 after the second wafer 700 is bonded to the first wafer 100.
The first interconnect electrode 710 is electrically connected to the devices in the second wafer 700 for electrically extracting the devices in the second wafer 700.
In this embodiment, the material of the first interconnection electrode 710 is a conductive material. In this embodiment, the material of the first interconnection electrode 710 includes: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and has better conductive effect.
The second interconnect electrode 720 is grounded for subsequent electrical connection with the metal shield 140, thereby achieving grounding of the metal shield 140.
In this embodiment, the material of the second interconnection electrode 720 is a conductive material. In this embodiment, the materials of the second interconnection electrode 720 include: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and has better conductive effect.
Referring to fig. 13, the first wafer 100 is bonded to the second wafer 700, the first surface to be bonded 100c is opposite to the second surface to be bonded 700a, the first conductive pillars 130 are electrically connected to the first interconnection electrode 710, and the metal shielding pillars 140 are electrically connected to the second interconnection electrode 720.
In this embodiment, the bonding of the first wafer 100 and the second wafer 700 is relatively achieved through the second surface to be bonded 700a and the first surface to be bonded 100 c.
In this embodiment, bonding is achieved by hybrid bonding, i.e., silicon oxide-silicon nitride, copper-copper, and copper-silicon nitride hybrid bonding. In other embodiments, bonding may also be accomplished using other bonding means, such as, for example, bonding in the form of a silica-silica fusion bond.
In this embodiment, the first conductive pillars 130 are electrically connected to the first interconnect electrode 710, and the electrical connection between the first conductive pillars 130 and the devices in the second wafer 700 is achieved.
In this embodiment, when the metal shielding column 140 is electrically connected to the second interconnection electrode 720, the metal shielding column 140 is grounded through the second interconnection electrode 720, so that current crosstalk can be led out, which is further beneficial to reducing the occurrence of crosstalk and coupling noise when the first conductive column 130 is electrically connected, thereby improving the reliability of the package structure.
Specifically, in the step of bonding the first wafer 100 to the second wafer 700, the first interconnection electrode 710 is disposed opposite to and electrically connected to the third interconnection electrode 610, thereby electrically connecting the first conductive pillar 130 to the device in the second wafer 700, and the second interconnection electrode 720 is disposed opposite to and electrically connected to the fourth interconnection electrode 620, thereby grounding the metal shielding pillar 140.
With continued reference to fig. 13, after the backside thinning process, the packaging method further includes: the carrier substrate 500 is removed.
The carrier substrate 500 is removed to expose the front surface 100a of the first wafer 100, so as to prepare for bonding other wafers on the front surface 100a of the first wafer 100 according to practical requirements.
In this embodiment, the wafer back surface 100b of the first wafer 100 is used as the first surface to be bonded 100c.
Therefore, after the first wafer 100 is bonded to the second wafer 700, the carrier substrate 500 is removed, so that after the 3D package is completed, the carrier substrate 500 is removed, which is beneficial to fully utilizing the carrier substrate 500 and further beneficial to continuously protecting the wafer front surface 100a of the first wafer 100 during the bonding process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1. A package structure, comprising:
a first wafer including a first bonding surface;
a plurality of first conductive pillars penetrating the first wafer;
the metal shielding columns are positioned between the adjacent first conductive columns and penetrate through the first wafer;
The second wafer bonded on the first wafer comprises a second bonding surface, the second bonding surface is opposite to the first bonding surface, a first interconnection electrode and a second interconnection electrode are formed on the second bonding surface, the first interconnection electrode is electrically connected with a device in the second wafer, the second interconnection electrode is grounded, the first conductive column is electrically connected with the first interconnection electrode, and the metal shielding column is electrically connected with the second interconnection electrode.
2. The package structure of claim 1, wherein the package structure further comprises: a second dielectric layer covering the first bonding surface;
the third interconnection electrode penetrates through the second dielectric layer and is electrically connected with the first conductive column, and the first interconnection electrode and the third interconnection electrode are oppositely arranged and are electrically connected;
and the fourth interconnection electrode penetrates through the second dielectric layer and is electrically connected with the metal shielding column, and the second interconnection electrode and the fourth interconnection electrode are oppositely arranged and electrically connected.
3. The package structure of claim 1, wherein the first wafer comprises opposing wafer front and wafer back surfaces, the wafer back surface being a first bonding surface;
The package structure further includes: the first dielectric layer is positioned on the front surface of the first wafer;
the first interconnection structure penetrates through the first dielectric layer, is positioned at the top of the first conductive column and is electrically connected with the first conductive column;
and the second interconnection structure penetrates through the first dielectric layer, is positioned at the top of the metal shielding column and is electrically connected with the metal shielding column.
4. The package structure of claim 3, wherein the first dielectric layer comprises a first bottom dielectric layer covering the front side of the wafer, and a first top dielectric layer covering the first bottom dielectric layer;
the first interconnect structure includes: the second conductive column is positioned at the top of the first conductive column and penetrates through the first bottom dielectric layer, and the projection of the second conductive column on the top surface of the first conductive column coincides with the top surface of the first conductive column;
a fifth interconnect electrode penetrating the first top dielectric layer and electrically connected to the second conductive pillar;
the second interconnect structure includes: the sub-interconnection structure is positioned at the top of the metal shielding column and penetrates through the first bottom dielectric layer, and the sub-interconnection structure is electrically connected with the metal shielding column;
And a sixth interconnection electrode penetrating the first top dielectric layer and electrically connected with the sub-interconnection structure.
5. The package structure of claim 1, wherein the material of the metal shield post comprises Cu, co, or W.
6. The package structure of claim 1, wherein a pitch between adjacent first conductive pillars and metal shield pillars is 3 μm to 18 μm.
7. A method of packaging, comprising:
providing a first wafer, wherein the first wafer comprises a first surface to be bonded;
forming a plurality of first conductive pillars and metal shielding pillars penetrating through the first wafer, wherein the metal shielding pillars are positioned between adjacent first conductive pillars;
providing a second wafer, wherein the second wafer comprises a second surface to be bonded, a first interconnection electrode and a second interconnection electrode are formed on the second surface to be bonded, the first interconnection electrode is used for electrically connecting devices in the second wafer, and the second interconnection electrode is grounded;
and bonding the first wafer and the second wafer, wherein the first surface to be bonded is opposite to the second surface to be bonded, the first conductive column is electrically connected with the first interconnection electrode, and the metal shielding column is electrically connected with the second interconnection electrode.
8. The packaging method of claim 7, wherein after forming the first conductive pillars and metal shielding pillars, prior to bonding the first wafer to the second wafer, the packaging method further comprises: forming a second dielectric layer covering the first surface to be bonded;
forming a third interconnection electrode covering the first conductive column and a fourth interconnection electrode covering the metal shielding column in the second dielectric layer;
in the step of bonding the first wafer and the second wafer, the first interconnection electrode is disposed opposite to and electrically connected with the third interconnection electrode, and the second interconnection electrode is disposed opposite to and electrically connected with the fourth interconnection electrode.
9. The packaging method of claim 7, wherein in the step of providing the first wafer, the first wafer includes opposite wafer front and wafer back surfaces, either of which serves as a first surface to be bonded;
the step of forming a plurality of first conductive pillars and metal shield pillars through the first wafer comprises: forming a plurality of first grooves and second grooves in the first wafer on the front surface of the wafer, wherein the second grooves are positioned between adjacent first grooves;
Filling the first groove to form the first conductive column;
filling the second groove to form the metal shielding column;
after forming the plurality of first conductive pillars and metal shielding pillars, the packaging method further includes: and carrying out back thinning treatment on the back of the wafer to expose the first conductive column and the metal shielding column.
10. The packaging method of claim 9, wherein a plurality of first trenches and second trenches are formed in the first wafer in a same step;
and filling the first groove and the second groove in the same step to form the first conductive column and the metal shielding column.
11. The packaging method of claim 9, wherein in the step of providing the first wafer, the back surface of the wafer serves as a first surface to be bonded;
after the first conductive posts and the metal shielding posts are formed, before the back surface of the wafer is subjected to back surface thinning treatment, the packaging method further comprises the following steps: and forming a first dielectric layer covering the front surface of the wafer, and a first interconnection structure and a second interconnection structure which are positioned in the first dielectric layer and penetrate through the first dielectric layer, wherein the first interconnection structure is positioned at the top of the first conductive column and is electrically connected with the first conductive column, and the second interconnection structure is positioned at the top of the metal shielding column and is electrically connected with the metal shielding column.
12. The packaging method of claim 11, wherein forming the first dielectric layer, and the first and second interconnect structures comprises: forming a first bottom dielectric layer covering the front surface of the wafer;
forming a second bottom interconnection structure which is electrically connected with the metal shielding column and penetrates through the first bottom dielectric layer at the top of the metal shielding column;
forming a first middle dielectric layer covering the first bottom dielectric layer and the second bottom interconnection structure;
forming a second conductive column penetrating through the first bottom dielectric layer and the first middle dielectric layer at the top of the first conductive column, wherein the projection of the second conductive column on the top surface of the first conductive column coincides with the top surface of the first conductive column;
forming a first top dielectric layer covering the first middle dielectric layer and the second conductive pillar;
forming a fifth interconnection electrode covering the second conductive column and a second top interconnection structure electrically connected with the second bottom interconnection structure in the first top dielectric layer, wherein the first top dielectric layer exposes the fifth interconnection electrode and the second top interconnection structure, the second conductive column and the fifth interconnection electrode form a first interconnection structure, and the second top interconnection structure of the second bottom interconnection structure forms a second interconnection structure.
13. The packaging method of claim 11, wherein in the step of forming first and second interconnect structures in the first dielectric layer that extend through the first dielectric layer, circuit structures for electrically connecting devices in the first wafer are also formed in the first dielectric layer.
14. The packaging method of claim 9, further comprising, prior to back thinning the back surface of the wafer: providing a bearing substrate, wherein the bearing substrate comprises a bearing surface;
the step of performing back thinning treatment on the back of the wafer comprises the following steps: bonding the first wafer and the bearing substrate, wherein the bearing surface is opposite to the front surface of the wafer;
after bonding the first wafer and the bearing substrate, carrying out back thinning treatment on the first wafer through the back of the wafer;
after the back side thinning process, the packaging method further includes: and removing the bearing substrate.
15. The packaging method of claim 14, wherein the back side of the wafer is a first surface to be bonded;
and removing the bearing substrate after bonding the first wafer and the second wafer.
16. The method of forming a semiconductor structure of claim 9, wherein the plurality of first trenches and second trenches in the first wafer are formed using an anisotropic etching process.
17. The method of forming a semiconductor structure of claim 9, wherein the first and second trenches are filled using a physical vapor deposition process to form the first conductive pillar and the metal shield pillar.
CN202111604680.4A 2021-12-24 2021-12-24 Packaging method and packaging structure Pending CN116344438A (en)

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