CN102610567A - Method for producing double-layer semiconductor device - Google Patents
Method for producing double-layer semiconductor device Download PDFInfo
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- CN102610567A CN102610567A CN2012100902533A CN201210090253A CN102610567A CN 102610567 A CN102610567 A CN 102610567A CN 2012100902533 A CN2012100902533 A CN 2012100902533A CN 201210090253 A CN201210090253 A CN 201210090253A CN 102610567 A CN102610567 A CN 102610567A
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Abstract
The invention adopts a method of adopting low-temperature bonding and peeling to realize the layer transfer of an upper semiconductor layer on a lower semiconductor device layer, then an upper layer of semiconductor device is produced in the upper semiconductor layer, and finally, technologies of an upper layer of contact holes and a lower layer of contact holes are completed at one time. The method realizes the isolation production of the upper and the lower semiconductor device layers, has a simple technology, and effectively improves the integrated level of the semiconductor device.
Description
Technical field
The present invention relates to a kind of preparation method of semiconductor device, relate in particular to a kind of preparation method of upper and lower two-layer semiconductor device.
Background technology
SOI (Silicon On Insulator) can realize that because of its particular structure and a series of premium properties the insulation of components and parts in the integrated circuit manufacturing is isolated, and eliminates the parasitic latch-up among the body silicon CMOS; Simultaneously, the CMOS/SOI circuit has also that parasitic capacitance is little, integrated level is high, speed is fast, low in energy consumption, series of advantages such as working temperature is high (300 ℃), anti-irradiation.Therefore, the SOI material will be one of main material of more hachure (0.1 μ m) integrated circuit, estimate will mainly use above-mentioned material when integrated level reaches when 1Gb uses Φ 300mm silicon chip.In recent years, the development of SOI material more and more causes people's great attention rapidly, and is considered to most important silicon integrated circuit technology of 21st century.
At present, layer transfer technology is the mainstream technology of preparation SOI material, in layer transfer technology, after a thin surface silicon layer is peeled off from a silicon substrate, is transferred on the silicon substrate after the oxidation, forms a slice SOI material.Owing to be substrate preparation, do not have the restriction of temperature among the preparation technology, therefore, bonding and stripping process in preparation SOI silicon substrate mostly adopt high-temperature technology, with the increase bond strength, make simultaneously peel off easier.At present, business-like layer transfer technology mainly comprises smart peeling technology (Smart-Cut), epitaxial loayer transfer techniques (ELTRAN) and annotates oxygen bonding techniques (Simbond).
But the support chip in layer shifts is to have prepared when the device of semiconductor device sheet is arranged; Because the existence of semiconductor device and semiconductor metal alloy (like nickel silicon alloy, cobalt silicon alloy, tungsten silicon alloy, alusil alloy etc.) in the support chip; Just can not adopt the high temperature bonding and the high temperature lift-off technology of conventional SOI silicon substrate, and must adopt cryogenic technique (generally requiring below 400 ℃).
Chinese patent CN1610114A discloses a kind of three-dimensional complementary metal oxide semiconductor device (CMOS) structure and preparation method thereof; It adopts low-temperature bonding and low temperature lift-off technology; Can realize the multiple-level stack of CMOS; Improve the device integration density, but have following defective: need add the layer of metal layer between layer and the layer, two layer devices are connected with it through through hole about it; This has increased the complexity of technology.
Chinese patent CN100440513C discloses a kind of three-dimensional complementary metal oxide semiconductor (CMOS) device architecture and preparation method thereof; It adopts low-temperature bonding and low temperature lift-off technology; Can realize the multiple-level stack of CMOS; Improve the device integration density, though it need not increase the layer of metal layer conduct articulamentum of device layer up and down between two-layer device layer, it still needs to prepare connecting through hole between each layer device layer; As the connecting line of two-layer device layer up and down, this has increased the complexity of technology equally.
What above-mentioned two patented technologies realized all is multiple-level stacks of CMOS, and multiple-level stack must increase the parasitic capacitance between semiconductor device, thereby the circuit response speed is restricted.
Summary of the invention
To the problems referred to above, the invention provides a kind of preparation method of upper and lower two-layer semiconductor device.
First aspect of the present invention provides a kind of preparation method of two-layer semiconductor device, and step comprises:
Preferably, when upper strata silicon key and segment thickness hour, on the part of upper strata silicon and lower layer support sheet bonding, carry out growing epitaxial silicon;
Step 4, preparation upper strata semiconductor device in the silicon of upper strata.
A kind of preferred implementation of above-mentioned preparation method according to the present invention, wherein, step also comprises
Step 5 forms upper strata ILD layer on the upper strata semiconductor device that in step 4, obtains, prepare upper strata contact hole and lower floor's contact hole then.Upper strata contact hole and lower floor's contact hole can be disposable or form one by one.
Above-mentioned preparation method's the further preferred implementation according to the present invention, wherein, the MOS district of last layer device MOS district and following layer device does not also line up, thereby is lower floor's device contacts hole slot milling.
Among the above-mentioned preparation method of the present invention, said lower layer support sheet can be a body silicon silicon chip, also can be soi wafer, also can be other semiconductor chips such as germanium wafer, germanium silicon chip, strain silicon chip etc.
ILD layer on the semiconductor device of lower layer support sheet can be SiO
2Layer in order to reduce the capacitively coupled effect between the device layer up and down, also can hang down the κ silicon dioxide layer for the carbon containing with microcellular structure.Wherein, in order to guarantee a layer transfer mass, must guarantee the ILD of lower floor enough little surface roughness CMP after, preferably, can adopt FACMP (Fixed Abrasive CMP) processing, make surface roughness less than 10nm.
Second aspect of the present invention provides a kind of two-layer semiconductor device of method for preparing, comprises layer device and last layer device down, and last layer device is connected to a fixed through the low-temperature bonding technology with following layer device.
Wherein, in the above-mentioned steps 4, epitaxial growth temperature is controlled at≤and 650 ℃.
The method of the present invention through adopting low-temperature bonding, low temperature to peel off; The layer of realizing the upper strata semiconductor layer on lower floor's semiconductor device layer shifts; In the semiconductor layer of upper strata, prepare the upper strata semiconductor device then, last property completion upper strata contact hole and lower floor's contact hole technology realize two-layer semiconductor device isolation preparation method up and down; Technology is simple, has effectively improved the integrated level of semiconductor device.
The present invention is owing to have only up and down two-layer semiconductor device layer, so the upper strata contact hole can once accomplish with lower floor's contact hole, and is technological than existing multi-lager semiconductor, simply many on technology.
Description of drawings
Fig. 1 is in an embodiment of the present invention, lower layer support sheet and upper strata silicon structure sketch map;
Fig. 2 is an attaching process sketch map among the said embodiment of Fig. 1;
Fig. 3 is a structural representation behind the low-temperature bonding among the said embodiment of Fig. 1;
Fig. 4 peels off the back structural representation for low temperature among the said embodiment of Fig. 1;
Fig. 5 is a structural representation after the epitaxial growth among the said embodiment of Fig. 1;
Fig. 6 is a preparation upper strata semiconductor device structure sketch map among the said embodiment of Fig. 1;
Fig. 7 forms ILD layer structural representation among the said embodiment of Fig. 1;
Fig. 8 is a preparation contact hole structural representation among the said embodiment of Fig. 1.
Embodiment
The invention provides a kind of preparation method of two-layer semiconductor device and the semiconductor device of said method preparation, Fig. 1 ~ Fig. 8 has provided the schematic flow sheet of the two-layer semiconductor device of preparation in the one embodiment of the invention; With reference to the accompanying drawings, the present invention is carried out detailed introduction and description through specific embodiment, so that better understand content of the present invention, but should be understood that following embodiment does not limit the scope of the invention.
In the present embodiment, be example, but also can be various semiconductor device with plane CMOS FET structure.
With reference to Fig. 1, lower layer support sheet 1 is graphical, and support chip 1 selective body silicon silicon chip also can be soi wafer, also can be other semiconductor chips such as germanium wafer, germanium silicon chip, strain silicon chip etc., and its semiconductor layer is conventional silicon layer.
The ILD layer 11 of lower layer support sheet 1 is SiO
2Layer is (in order to reduce the capacitively coupled effect between the device layer up and down; Also can hang down the κ silicon dioxide layer) for carbon containing with microcellular structure; In order to guarantee a layer transfer mass; Must guarantee the ILD of lower floor enough little surface roughness CMP after, employing FACMP (Fixed Abrasive CMP) makes surface roughness less than 10nm.
Contain rich boron, hydrogen layer 21 in the upper strata silicon 2, the part that wherein is used for lower layer support sheet 1 bonding is a silicon dioxide layer 22.
Always there is oxide layer in silicon chip surface, and some is in, and the silica covalent bond can rupture in the surperficial silicon dioxide molecules, makes silicon atom form dangling bonds.The silicon atom of suspension shows electropositive, can regard silicon face one deck charge layer as.During through hydrophilic treatment, silicon face absorption OH-group forms the silanol key.Two silicon chips that form the silanol keys near the time, can attract each other by the formation hydrogen bond between silanol key, hydrone and the silanol key.The applying period of Here it is bonding.What the silicon chip interface existed is (Si-OH) and hydrone.When temperature raises, following reaction is arranged:
2SiOH→Si-O-Si+H
2O
Be that the silanol key transforms to silicon oxygen bond.This reaction is reversible reaction, and temperature is high more, and the Direction of Reaction carries out to the right more.Here it is, and why high annealing can strengthen bond strength.Process annealing is exactly to require under lower temperature, and reaction can be carried out to the right more fully.This just has following two requirements: (1) silicon chip surface will form the silanol key as much as possible, silicon chip is combined when fitting closely and enough reactants are arranged; (2) the process annealing time will be grown, and is beneficial to hydrone escape and diffusion, and reaction is constantly carried out to positive direction.For the second above point, prolong annealing time and get final product.And first point requires silicon chip that dangling bonds are as much as possible arranged before hydrophilic treatment, so that adsorb a large amount of (OH) groups.With the oxygen plasma Activiation method is example, and it can have following reaction on the oxide layer surface, thereby reaches the purpose that forms a large amount of silicon dangling bonds, and this is the main cause that process annealing can strengthen bonded interface intensity.
Therefore, earlier the bonding surface of lower layer support sheet 1 and the silicon dioxide layer 22 of upper strata silicon chip are carried out activation processing (like chemistry or Cement Composite Treated by Plasma), hydrophilic treatment, so that bonding face forms a large amount of silanol keys.
With reference to Fig. 2, the silicon dioxide layer 22 and the treatment surface of lower layer support sheet 1 of upper strata silicon 2 to be fitted (arrow is the applying direction), this step can at room temperature be carried out.
With reference to Fig. 3, low-temperature bonding is reinforced upper strata silicon 2 on lower layer support sheet 1.
This step can be carried out with reference to prior art.
With reference to Fig. 4, through the low-temperature bonding technology, upper strata silicon is ruptured from rich boron, hydrogen layer, thereby rich boron, the above part of hydrogen layer are peeled off in will scheming, and lower part (bonding part) becomes one with lower layer support sheet bonding.
This step can be carried out with reference to prior art.Several different methods is also arranged now, is 5E16cm like dosage
-2To 9E16cm
-2Notes hydrogen sheet or hydrogen helium annotate sheet altogether and can about 500 ℃, peel off, and boron, hydrogen is annotated the sheet exfoliation temperature altogether can be less than 400 ℃.Even; Containing the bonding pad of annotating hydrogen layer or porous silicon layer can just can at room temperature successfully peel off under mechanism, and these technology all be that the support chip in layer transfer is to have prepared when the device of semiconductor device sheet is arranged required low temperature to peel off technical foundation is provided.
Low temperature solid phase (or liquid phase) growing epitaxial silicon, key forms upper strata silicon layer 3 with part, and is as the basis of preparation upper strata semiconductor device, as shown in Figure 5.This epitaxial growth steps is an optional step, under the enough thick situation of the upper strata silicon layer behind the bonding, can omit.
Step 4
Preparation upper strata semiconductor device is as shown in Figure 6 in the upper strata silicon layer 3 that in step 3, obtains.
Step 5
Deposition ILD layer 23 is as shown in Figure 7 on the upper strata semiconductor device that step 4 obtains, and prepares upper strata contact hole 20 and lower floor's contact hole 10 simultaneously, and is as shown in Figure 8.
In this step 5, can adjust the upper strata device position, for example will go up the certain distance that squints between layer device MOS district and the following layer device MOS district, thereby be the preparation lower floor enough spaces of contact hole reservation.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (7)
1. the preparation method of a two-layer semiconductor device is characterized in that, step comprises:
Step 1 provides patterned lower layer support sheet (following layer device), and the upper strata silicon chip is provided, and wherein, said upper strata silicon comprises rich boron, hydrogen layer, and comprises bonded layer; Activation processing and hydrophilic treatment are carried out in patterned lower layer support sheet surface and said bonded layer; The surfacing of upper strata silicon bonded layer and lower layer support sheet is silicon dioxide;
Step 2 is fitted in the lower layer support sheet surface after the processing with the bonded layer of upper strata silicon, and through low-temperature bonding upper strata silicon is fixed on lower layer support sheet surface;
Step 3 through the low temperature lift-off technology, is peeled off upper strata silicon from rich boron, the fracture of hydrogen layer, the part of rich boron, hydrogen layer below is connected as a single entity with lower layer support sheet surface bond;
Step 4, preparation upper strata semiconductor device in the silicon layer of upper strata.
2. preparation method according to claim 1 is characterized in that step also comprises
Step 5 forms upper strata ILD layer on the upper strata semiconductor device that in step 4, obtains, prepare upper strata contact hole and lower floor's contact hole then.
3. preparation method according to claim 2 is characterized in that, the MOS district of last layer device MOS district and following layer device does not also line up, thereby is lower floor's device contacts hole slot milling.
4. preparation method according to claim 1 is characterized in that, the lower layer support sheet is selected from body silicon silicon chip, soi wafer, germanium wafer, germanium silicon chip, strain silicon chip.
5. preparation method according to claim 1 is characterized in that, after the step 3, on the part of upper strata silicon and lower layer support sheet bonding, carries out growing epitaxial silicon; Epitaxial growth temperature is controlled at≤and 650 ℃.
6. preparation method according to claim 1 is characterized in that, the ILD layer on the semiconductor device of lower layer support sheet is selected from SiO
2The low κ silicon dioxide layer of layer or carbon containing.
7. two-layer semiconductor device of method preparation according to claim 1.
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|---|---|---|---|
| CN2012100902533A CN102610567A (en) | 2012-03-31 | 2012-03-31 | Method for producing double-layer semiconductor device |
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| CN2012100902533A CN102610567A (en) | 2012-03-31 | 2012-03-31 | Method for producing double-layer semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098687A (en) * | 2016-08-03 | 2016-11-09 | 贵州大学 | A kind of three-dimensional power VDMOSFET device and integrated approach thereof |
| CN109712880A (en) * | 2018-12-03 | 2019-05-03 | 武汉新芯集成电路制造有限公司 | A kind of method for improving and enhancing system of wafer bonding power |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528388B2 (en) * | 2000-02-21 | 2003-03-04 | Rohm Co., Ltd. | Method for manufacturing semiconductor device and ultrathin semiconductor device |
| US6821826B1 (en) * | 2003-09-30 | 2004-11-23 | International Business Machines Corporation | Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers |
| CN1610113A (en) * | 2004-10-15 | 2005-04-27 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof |
-
2012
- 2012-03-31 CN CN2012100902533A patent/CN102610567A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528388B2 (en) * | 2000-02-21 | 2003-03-04 | Rohm Co., Ltd. | Method for manufacturing semiconductor device and ultrathin semiconductor device |
| US6821826B1 (en) * | 2003-09-30 | 2004-11-23 | International Business Machines Corporation | Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers |
| CN1610113A (en) * | 2004-10-15 | 2005-04-27 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098687A (en) * | 2016-08-03 | 2016-11-09 | 贵州大学 | A kind of three-dimensional power VDMOSFET device and integrated approach thereof |
| CN106098687B (en) * | 2016-08-03 | 2019-04-16 | 贵州大学 | A kind of three-dimensional power VDMOSFET device and its integrated approach |
| CN109712880A (en) * | 2018-12-03 | 2019-05-03 | 武汉新芯集成电路制造有限公司 | A kind of method for improving and enhancing system of wafer bonding power |
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Application publication date: 20120725 |