CN103066007B - A kind of preparation method of full isolation structure - Google Patents
A kind of preparation method of full isolation structure Download PDFInfo
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- CN103066007B CN103066007B CN201210545605.XA CN201210545605A CN103066007B CN 103066007 B CN103066007 B CN 103066007B CN 201210545605 A CN201210545605 A CN 201210545605A CN 103066007 B CN103066007 B CN 103066007B
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Abstract
A kind of preparation method of full isolation structure, including：One silicon substrate is provided；Isolation channel is formed using groove isolation technology on a silicon substrate；Etching removes the portion of oxide layer in isolation channel；One layer of silicon nitride is deposited on a silicon substrate；Continue the portion of oxide layer in the silicon nitride and groove of etching removal isolation trench bottom；Hot oxygen technique is carried out, insulating barrier is formed between bottom silicon and top layer silicon；Through groove isolation technology, full isolation structure is formed.The preparation method of the present invention, using the technique compatible with standard COMS phases, full isolation structure is directly prepared on a silicon substrate, avoids the drawbacks of usually requiring that using SOI substrate full isolation structure could be realized, not only cost is low, easy operation, and obtained SOI substrate reliability is high.
Description
Technical field
The present invention relates to ic manufacturing technology field, more particularly to a kind of preparation method of full isolation structure.
Background technology
SOI English is silicon-on-insulator, i.e., the silicon on insulating barrier.It is by bottom silicon/insulation layer/top layer
What silicon was formed.Middle insulating barrier is usually silica, abbreviation oxygen buried layer, for isolating device and silicon substrate.Now, it is based on
It is super that the product of SOI technology has spread all over microprocessor, printing device, network and storage device and wrist-watch and automotive electronics etc.
Low-power consumption product, these products suffer from special requirement to device speed, feature and low-power consumption.Research it is also shown that with
Device based on body silicon substrate is compared, and under identical leakage current, the device performance based on SOI substrate is improved significantly, and is had
There is lower transient state crash rate, can improve 5-7 times in terms of transient state failure；Device based on SOI substrate has more excellent temperature
Sensitiveness, therefore can work in high temperature environments.Field-effect transistor is colonized in further, since eliminating（FET）Between post
Raw bipolar device, therefore avoid latch-up.SOI technology also has some advantages in terms of processing technology, it is not necessary to cumbersome
Isolation technology or the deeper N-type or P-type channel ion implanting of injection depth.With the further scaled down of technology, body silicon
Technique needs to increase extra processing step in ion implanting and shallow ditch groove separation process (STI) technical module, and these are all
It is that SOI technology institute is unwanted.With the reduction of integrated circuit dimensions, the arrangement more crypto set of the device of circuit, silicon lining are formed
The density of unit area active device is more and more important on bottom, so being effectively dielectrically separated between circuit also becomes more important.
At present, the conventional preparation method of the full isolation structure of body silicon is using standard CMOS process, including provides a silicon
Substrate, a layer insulating is deposited in surface of silicon, then using carrying out local oxide isolation technique（LOCOS）Or STI techniques are formed
Full isolation structure；And the conventional preparation method of full isolation structure is first to use to produce SOI linings the methods of Smart cut, SIMOX
Bottom, then using carrying out local oxide isolation technique（LOCOS）Or STI techniques form full isolation structure.
Compare above two technique, forming full isolation structure using the technique of the latter needs pre-production to go out SOI, SOI linings
Bottom uses smart-cut（Smart cut）, note oxygen isolation（SIMOX）The methods of, cost of manufacture is high, and Smart cut are obtained
Full isolation structure substrate in oxygen buried layer and surface silicon be also easy to produce peeling, subsequent technique and device performance can be influenceed.
Therefore, because standard CMOS process is simple to operate, easily realize, if can using the technique of standard COMS compatibilities come
Make full isolation structure, it is possible to reduce cost, and the reliability of the full isolation structure formed is higher.
The content of the invention
To overcome above mentioned problem, it is an object of the invention to provide a kind of preparation method of full isolation structure, can simplify
Technique, production cost is reduced, and prepare the higher full isolation structure of reliability.
Full isolation structure is followed successively by bottom silicon, absolutely bottom-up in a kind of preparation method of full isolation structure of the present invention
Edge layer, top layer silicon and the isolation channel with oxide layer, making step include：
Step S01：One silicon substrate is provided；
Step S02：The isolation channel with oxide layer is formed on the silicon substrate using groove isolation technology；
Step S03：Etching removes the portion of oxide layer in the isolation channel；
Step S04：One layer of silicon nitride is deposited on the silicon substrate；
Step S05：Etching removes the portion of oxide layer in the silicon nitride and groove of the isolation trench bottom；
Step S06：Hot oxygen technique is carried out, the insulating barrier is formed between the bottom silicon and the top layer silicon；
Step S07：Through groove isolation technology, the full isolation structure is formed.
Preferably, the depth of the isolation channel is 200-1000nm.
Preferably, in step S03, etch the portion of oxide layer and refer to etch oxide layer in the isolation channel until institute
Oxide layer top to the distance at the top of the top layer silicon stated in isolation channel is 50-300nm.
Preferably, the thickness of described silicon nitride is 3-30nm.
Preferably, in step S04, in addition to the silicon nitride using the anisotropic etching removal isolation trench bottom.
Preferably, in step S05, etch the portion of oxide layer and refer to that etching removes the oxide layer in the isolation channel
Thickness is 5-30nm.
Preferably, the insulating layer material is silica.
A kind of preparation method of full isolation structure provided by the invention, can be compatible with standard COMS phases, is directly served as a contrast in silicon
Full isolation structure is prepared on bottom, avoids the drawbacks of usually requiring that using SOI substrate full isolation structure could be realized, not only
Cost is low, easy operation, and obtained SOI substrate reliability is high.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of a preferred embodiment of the preparation method of the full isolation structure of the present invention
Fig. 2~8 are each preparation process signals of the preparation method of the full isolation structure of the above-mentioned preferred embodiment of the present invention
Figure.
Embodiment
The preparation method of silicon nanowire array provided by the invention is made below in conjunction with the drawings and specific embodiments further
Describe in detail.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing
Non- accurately ratio is used using very simplified form and, only implemented conveniently, lucidly to aid in illustrating the present invention
The purpose of example.
In conjunction with accompanying drawing 1-8, a kind of preparation method of full isolation structure of the present invention is entered by a specific embodiment
One step describes in detail.It should be noted that accompanying drawing uses using very simplified form and non-accurately ratio, only to side
Just the purpose of the embodiment of the present invention, is lucidly aided in illustrating.
Fig. 1 is the schematic flow sheet of a preferred embodiment of the preparation method of the full isolation structure of the present invention.Fig. 3-8 is
Each preparation process schematic diagram of the preparation method of the full isolation structure of the above embodiment of the present invention.Fig. 8 is the above-mentioned of the present invention
The schematic diagram of the full isolation structure of embodiment.
Referring to Fig. 8, as illustrated, the full isolation structure in the present embodiment is followed successively by bottom silicon, insulation bottom-up
Layer, top layer silicon and the isolation channel with oxide layer.
Referring to Fig. 1, as illustrated, the preparation method of the full isolation structure in the present embodiment comprises the following steps：
Step S01：One silicon substrate is provided；In the present embodiment, the silicon substrate can be monocrystalline silicon, polysilicon or amorphous
Silicon.
Step S02：Refering to Fig. 2, the isolation channel with oxide layer is formed using groove isolation technology on a silicon substrate；Here,
The depth of isolation channel is 200-1000nm.Groove isolation technology can be, but not limited to be STI techniques.As shown in Figure 2, the present embodiment
In, the structure of the silicon substrate formed after groove isolation technology is followed successively by bottom-up：Bottom silicon, pad silicon dioxide layer, top layer
Silicon, silicon nitride layer and isolation channel, STI techniques are used by forming this structure in the present embodiment：Using but being not limited to
Learn vapour deposition process and sequentially form pad silicon oxide layer and silicon nitride layer on a silicon substrate, then use but be not limited to plasma
Dry etching pad silicon oxide layer, silicon nitride layer and partial silicon substrate then use to form isolation channel but are not limited to chemical gas
Phase sedimentation or atomic layer deposition method form pad silicon oxide layer in isolation channel and silicon nitride surface, can be repaired by padding silicon oxide layer
Caused surface defect and alleviation stress, then form insulating barrier on pad silicon oxide layer surface in previous process, then chemical
Mechanical lapping removes the pad silicon oxide layer and insulating barrier on silicon nitride layer surface, and this is not used in limitation the scope of the present invention.This implementation
Insulating barrier in example is silicon dioxide layer.
Step S03：Referring to Fig. 3, using but be not limited to plasma dry etch or wet etching and remove isolation channel
Interior portion of oxide layer；Here, etched portions oxide layer refer to etch isolation channel in oxide layer until isolation channel in oxidation
Layer top to the distance at the top of top layer silicon is 50-300nm.In the present embodiment, the oxygen in the isolation channel is specifically etched downwards
Change layer, the distance at the top of the oxide layer distance from top top layer silicon after being etched in isolation channel is 50-300nm.Used quarter
Erosion gas can be, but not limited to be Cl2, HBr or other gases mixed gas.The thickness of etching can by the time of etching come
Control, the present invention are not intended to be limited in any to this.
Step S04：Referring to Fig. 4, using but be not limited to chemical vapor deposition or atomic layer deposition method and sink on a silicon substrate
One layer of silicon nitride of product；Here, nitride deposition is also deposited in isolation channel while surface of silicon, and this is not used in limitation
The present invention.By controlling the process time, the thickness of deposited silicon nitride layer can be controlled, in the present embodiment, the silicon nitride is thin
The thickness of film is 3-30nm.
Step S05：Refer to Fig. 5 and Fig. 6, using but be not limited to dry plasma etch or wet etching and remove isolation channel
The silicon nitride of bottom, use again but be not limited to dry plasma etch or wet etching remove isolation channel in partial oxidation
Layer；In the present embodiment, the oxide layer in isolation channel is etched downwards, the thickness for the oxide layer in isolation channel being etched away is 5-
30nm。
Step S06：Referring to Fig. 7, carrying out hot oxygen technique, insulating barrier is formed between bottom silicon and top layer silicon；This implementation
Example in, the material of the insulating barrier is silica, the temperature of used hot oxygen technique can be, but not limited to be 900 °C or
1000 °C, used gas can be, but not limited to be the oxidizer flows such as oxygen or vapor.During hot oxygen, pass through control
The suitable process time is made, includes gas phase diffusion and solid phase in isolation channel and to the diffusion of isolation channel both sides with oxidizer flow
Diffusion, not only forms silicon dioxide layer in isolation channel, the silicon dioxide layer of connection is also formed between isolation channel, is finally being pushed up
One layer of continuous silicon dioxide layer is formed between layer silicon and bottom silicon.Also, because active area of the size more than 90nm need not
Full isolation structure is formed, the present invention is applied to the semiconductor integrated circuit manufacturing process in 90-14nm technology generations, due to active area very
It is narrow, so by process above, the rational time is controlled, the silicon dioxide layer of connection can be formed between isolation channel.
Step S07：Referring to Fig. 8, using groove isolation technology, silicon dioxide layer is formed in isolation channel, and through chemical machine
Tool grinding removes the silicon dioxide layer of silicon nitride surface, ultimately forms full isolation structure.
The preparation method of a kind of full isolation structure of the present invention, using the technique compatible with standard COMS phases, directly in silicon
Full isolation structure is prepared on substrate, avoids the drawbacks of usually requiring that using SOI substrate full isolation structure could be realized, no
Only cost is low, easy operation, and obtained SOI substrate reliability is high.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (7)
1. a kind of preparation method of full isolation structure, the full isolation structure are followed successively by bottom silicon, insulating barrier, top bottom-up
Layer silicon and the isolation channel with oxide layer, it is characterised in that including：
Step S01：One silicon substrate is provided；
Step S02：The isolation channel with oxide layer is formed on the silicon substrate using groove isolation technology；
Step S03：Etching removes the portion of oxide layer in the isolation channel, the member-retaining portion oxide layer in isolation channel；Wherein, originally
The thickness that the portion of oxide layer of removal is etched in step S03 is the height of the silicon nitride in the full isolation structure ultimately formed；
Step S04：One layer of silicon nitride is deposited on the silicon substrate；
Step S05：Etching removes the portion of oxide layer in the isolation channel bottom nitride silicon and groove, the member-retaining portion in isolation channel
Oxide layer；Wherein, the thickness for the portion of oxide layer for etching removal in this step S05 determines forms connection between isolation channel
The thickness of insulating barrier；
Step S06：Thermal oxidation technology is carried out, the insulating barrier is formed between the bottom silicon and the top layer silicon；Isolating
The bottom that the insulating barrier of connection is formed between groove is higher than the bottom of isolation channel；
Step S07：Through groove isolation technology, new oxide layer is filled in isolation channel, so as to form the full isolation structure.
2. the preparation method of full isolation structure according to claim 1, it is characterised in that the depth of the isolation channel is
200-1000nm。
3. the preparation method of full isolation structure according to claim 1, it is characterised in that in step S03, etch the portion
Point oxide layer refers to etch the oxide layer in the isolation channel until to the top layer silicon at the top of oxide layer in the isolation channel
The distance at top is 50-300nm.
4. the preparation method of full isolation structure according to claim 1, it is characterised in that the thickness of described silicon nitride is
3-30nm。
5. the preparation method of full isolation structure according to claim 1, it is characterised in that in step S04, using each to different
Property etching remove it is described isolation trench bottom silicon nitride.
6. the preparation method of full isolation structure according to claim 1, it is characterised in that in step S05, etch the portion
Point oxide layer refers to that the thickness that etching removes the oxide layer in the isolation channel is 5-30nm.
7. the preparation method of full isolation structure according to claim 1, it is characterised in that the insulating layer material is dioxy
SiClx.
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| CN103390575A (en) * | 2013-08-01 | 2013-11-13 | 上海集成电路研发中心有限公司 | Manufacture method of full isolation structure |
| CN110858561A (en) * | 2018-08-23 | 2020-03-03 | 合肥晶合集成电路有限公司 | Silicon island structure and manufacturing method thereof |
| US20240030282A1 (en) * | 2022-07-21 | 2024-01-25 | Invention And Collaboration Laboratory Pte. Ltd. | Bulk semiconductor substrate with fully isolated single-crystalline silicon islands and the method for forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4685198A (en) * | 1985-07-25 | 1987-08-11 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing isolated semiconductor devices |
| EP1170786A1 (en) * | 2000-07-07 | 2002-01-09 | Agere Systems Guardian Corporation | Silicon-on-insulator (SOI) semiconductor structure and method of manufacture |
| CN102479742A (en) * | 2010-11-30 | 2012-05-30 | 中国科学院微电子研究所 | Substrate for integrated circuit and formation method thereof |
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2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4685198A (en) * | 1985-07-25 | 1987-08-11 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing isolated semiconductor devices |
| EP1170786A1 (en) * | 2000-07-07 | 2002-01-09 | Agere Systems Guardian Corporation | Silicon-on-insulator (SOI) semiconductor structure and method of manufacture |
| CN102479742A (en) * | 2010-11-30 | 2012-05-30 | 中国科学院微电子研究所 | Substrate for integrated circuit and formation method thereof |
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