CN102623406A - Method for producing two layers of semiconductor devices with half empty structure - Google Patents

Method for producing two layers of semiconductor devices with half empty structure Download PDF

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Publication number
CN102623406A
CN102623406A CN2012100904308A CN201210090430A CN102623406A CN 102623406 A CN102623406 A CN 102623406A CN 2012100904308 A CN2012100904308 A CN 2012100904308A CN 201210090430 A CN201210090430 A CN 201210090430A CN 102623406 A CN102623406 A CN 102623406A
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layer
silicon
upper strata
support sheet
hole
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CN2012100904308A
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Chinese (zh)
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CN102623406B (en
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黄晓橹
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上海华力微电子有限公司
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Abstract

According to the invention, the methods of low-temperature bonding and low-temperature exfoliation are utilized to achieve the layer transfer of an upper semiconductor layer above a lower semiconductor device layer, then an upper semiconductor device is produced in the upper semiconductor layer, and finally, the processes for an upper contact hole and a lower contact hole are completed in one time to realize isolation in production of the upper and the lower layers of semiconductor devices. The method provided by the invention has the advantage of simple process. The integration level of the semiconductor devices is increased effectively. Additionally, a half empty isolation structure of an empty layer and the lower contact hole is produced between the upper and the lower layers of the semiconductor devices to effectively reduce the capacitance coupling effect between the upper and the lower layers of the semiconductor devices.

Description

Have the preparation method of the two-layer semiconductor device of hole structure in midair

Technical field

The present invention relates to a kind of preparation method of semiconductor device, relate in particular to a kind of preparation method of the upper and lower two-layer semiconductor device of hole isolation structure in midair that has.

Background technology

SOI (Silicon On Insulator) can realize that because of its particular structure and a series of premium properties the insulation of components and parts in the integrated circuit manufacturing is isolated, and eliminates the parasitic latch-up among the body silicon CMOS; Simultaneously, the CMOS/SOI circuit has also that parasitic capacitance is little, integrated level is high, speed is fast, low in energy consumption, series of advantages such as working temperature is high (300 ℃), anti-irradiation.Therefore, the SOI material will be one of main material of more hachure (0.1 μ m) integrated circuit, estimate will mainly use above-mentioned material when integrated level reaches when 1Gb uses Φ 300mm silicon chip.In recent years, the development of SOI material more and more causes people's great attention rapidly, and is considered to most important silicon integrated circuit technology of 21st century.

At present, layer transfer technology is the mainstream technology of preparation SOI material, in layer transfer technology, after a thin surface silicon layer is peeled off from a silicon substrate, is transferred on the silicon substrate after the oxidation, forms a slice SOI material.Owing to be substrate preparation, do not have the restriction of temperature among the preparation technology, therefore, bonding and stripping process in preparation SOI silicon substrate mostly adopt high-temperature technology, with the increase bond strength, make simultaneously peel off easier.At present, business-like layer transfer technology mainly comprises smart peeling technology (Smart-Cut), epitaxial loayer transfer techniques (ELTRAN) and annotates oxygen bonding techniques (Simbond).

But the support chip in layer shifts is to have prepared when the device of semiconductor device sheet is arranged; Because the existence of semiconductor device and semiconductor metal alloy (like nickel silicon alloy, cobalt silicon alloy, tungsten silicon alloy, alusil alloy etc.) in the support chip; Just can not adopt the high temperature bonding and the high temperature lift-off technology of conventional SOI silicon substrate, and must adopt cryogenic technique (generally requiring below 400 ℃).

Chinese patent CN1610114A discloses a kind of three-dimensional complementary metal oxide semiconductor device (CMOS) structure and preparation method thereof; It adopts low-temperature bonding and low temperature lift-off technology; Can realize the multiple-level stack of CMOS; Improve the device integration density, but have following defective: need add the layer of metal layer between layer and the layer, two layer devices are connected with it through through hole about it; This has increased the complexity of technology.

Chinese patent CN100440513C discloses a kind of three-dimensional complementary metal oxide semiconductor (CMOS) device architecture and preparation method thereof; It adopts low-temperature bonding and low temperature lift-off technology; Can realize the multiple-level stack of CMOS; Improve the device integration density, though it need not increase the layer of metal layer conduct articulamentum of device layer up and down between two-layer device layer, it still needs to prepare connecting through hole between each layer device layer; As the connecting line of two-layer device layer up and down, this has increased the complexity of technology equally.

What above-mentioned two patented technologies realized all is multiple-level stacks of CMOS, and multiple-level stack must increase the parasitic capacitance between semiconductor device, thereby the circuit response speed is restricted.

Summary of the invention

To the problems referred to above, the invention provides a kind of preparation method of the upper and lower two-layer semiconductor device of hole structure in midair that has.

First aspect of the present invention provides a kind of preparation method of the two-layer semiconductor device of hole structure in midair that has, and step comprises:

Step 1 provides patterned lower layer support sheet (following layer device), and the ILD layer of device is amorphous carbon layer (an AC layer) in the lower layer support sheet, on the ILD of lower layer support sheet layer, deposits the thin layer silicon dioxide layer; Upper strata silicon is provided, and wherein, said upper strata silicon comprises rich boron, hydrogen layer, and comprises the silicon dioxide layer that is positioned at the surface; The silicon dioxide layer of upper strata silicon and the silicon dioxide layer of lower layer support sheet are carried out activation processing and hydrophilic treatment, to increase the silanol key of treatment surface;

Step 2 is fitted in the silicon dioxide layer of upper strata silicon on the lower layer support sheet surface silica dioxide layer after the processing, and through low-temperature bonding upper strata silicon is fixed on lower layer support sheet surface;

Step 3 through the low temperature lift-off technology, is peeled off upper strata silicon from rich boron, the fracture of hydrogen layer, the part of rich boron, hydrogen layer below is connected as a single entity with lower layer support sheet surface bond;

Preferably, under the less situation of upper strata silicon layer bonding segment thickness, on the part of upper strata silicon and lower layer support sheet bonding, carry out growing epitaxial silicon, increase the thickness of upper strata silicon;

Step 4, preparation upper strata semiconductor device in the silicon of upper strata; On the upper strata semiconductor device that obtains, form upper strata ILD layer, prepare upper strata contact hole and lower floor's contact hole then.Upper strata contact hole and lower floor's contact hole can be disposable or form one by one;

Step 5 prepares amorphous carbon ashing through hole at last layer device then, and said amorphous carbon ashing through hole runs through the ILD layer of layer device to lower layer support sheet;

Step 6 is carried out ashing treatment through said amorphous carbon ashing through hole to the ILD layer in the lower layer support sheet, forms the cavity layer in the ILD position of lower layer support sheet;

Step 7 upwards deposits dielectric in the amorphous carbon ashing through hole in the layer device, with the shutoff of amorphous carbon ashing through hole.

In a kind of preferred implementation of the present invention, said amorphous carbon ashing through hole prepares above the sti structure of last layer device, and amorphous carbon ashing through hole runs through ILD layer and the STI layer of layer device until the ILD of lower layer support sheet layer.

In another kind of preferred implementation of the present invention, dielectric is preferably SiO described in the step 7 2

In another kind of preferred implementation of the present invention, the MOS district of last layer device MOS district and following layer device does not also line up, thereby is lower floor's device contacts hole slot milling.

Among the above-mentioned preparation method of the present invention, said lower layer support sheet can be a body silicon silicon chip, also can be soi wafer, or other semiconductor chip, like germanium wafer, germanium silicon chip, strain silicon chip etc.

Wherein, in order to guarantee a layer transfer mass, must guarantee the ILD of lower floor enough little surface roughness CMP after, preferably, can adopt FACMP (Fixed Abrasive CMP) processing, make surface roughness less than 10nm.

Second aspect of the present invention provides a kind of two-layer semiconductor device of method for preparing, comprises layer device and last layer device down, and last layer device is connected to a fixed through the low-temperature bonding technology with following layer device.

Wherein, in the above-mentioned steps 4, epitaxial growth temperature is controlled at≤and 650 ℃.

The AC layer can ashing before the hole preparation in midair in order to guarantee lower floor, in the step 1, the lower layer support sheet since AC layer deposition back to thin layer SiO 2Between having deposited, can not occur that dry method is removed photoresist and cineration technics, can only adopt wet processing.In addition, it is big that the EBR (Edge Bead Removal) of deposition AC layer must come than the EBR of deposition SiO2 layer, to guarantee that AC on the wafer limit is by SiO 2Wrap.

The method of the present invention through adopting low-temperature bonding, low temperature to peel off; The layer of realizing the upper strata semiconductor layer on lower floor's semiconductor device layer shifts; In the semiconductor layer of upper strata, prepare the upper strata semiconductor device then, last property completion upper strata contact hole and lower floor's contact hole technology realize two-layer semiconductor device isolation preparation method up and down; Technology is simple, has effectively improved the integrated level of semiconductor device.

The present invention is owing to have only up and down two-layer semiconductor device layer, so the upper strata contact hole can once accomplish with lower floor's contact hole, and is technological than existing multi-lager semiconductor, simply many on technology.Since contact hole technology before the amorphous carbon ILD layer ashing treatment preparation accomplish, lower floor's contact hole is simultaneously also as the usefulness of the supporting construction between the semiconductor device layer up and down.Like this, preparation has the isolation structure of hole in midair of cavity layer+lower floor contact hole supporting construction in the levels semiconductor device layer, effectively reduces the capacitance coupling effect between the device layer up and down.

Description of drawings

Fig. 1 is in an embodiment of the present invention, lower layer support sheet and upper strata silicon structure sketch map;

Fig. 2 is an attaching process sketch map among the said embodiment of Fig. 1;

Fig. 3 is a structural representation behind the low-temperature bonding among the said embodiment of Fig. 1;

Fig. 4 peels off the back structural representation for low temperature among the said embodiment of Fig. 1;

Fig. 5 is a structural representation after the epitaxial growth among the said embodiment of Fig. 1;

Fig. 6 is a preparation upper strata semiconductor device structure sketch map among the said embodiment of Fig. 1;

Fig. 7 forms ILD layer structural representation among the said embodiment of Fig. 1;

Fig. 8 is a preparation contact hole structural representation among the said embodiment of Fig. 1;

Fig. 9 is a preparation amorphous carbon through-hole structure sketch map among the said embodiment of Fig. 1;

Figure 10 is with the structural representation after the ashing of AC layer among the said embodiment of Fig. 1;

The two-layer semiconductor device structure sketch map of Figure 11 for preparing in the foregoing description.

Embodiment

The invention provides a kind of preparation method of two-layer semiconductor device and the semiconductor device of said method preparation, Fig. 1 ~ Figure 11 has provided the schematic flow sheet of the two-layer semiconductor device of preparation in the one embodiment of the invention; With reference to the accompanying drawings, the present invention is carried out detailed introduction and description through specific embodiment, so that better understand content of the present invention, but should be understood that following embodiment does not limit the scope of the invention.

 

In the present embodiment, be example, but also can be various semiconductor device with plane CMOS FET structure.

 

Step 1

With reference to Fig. 1, lower layer support sheet 1 is graphical, and support chip 1 selective body silicon silicon chip also can be soi wafer, perhaps other semiconductor chips such as germanium wafer, germanium silicon chip, strain silicon chip etc.

The ILD layer 11 of lower layer support sheet 1 is an amorphous carbon layer 11, in order to guarantee a layer transfer mass, must guarantee the ILD of lower floor enough little surface roughness CMP after, and employing FACMP (Fixed Abrasive CMP) makes surface roughness less than 10nm.

For the needs of follow-up bonding, stringer SiO on ILD layer 11 2Layer 12.

Contain rich boron, hydrogen layer 21 in the upper strata silicon 2, the part that wherein is used for lower layer support sheet 1 bonding is SiO 2Layer 22.

Always there is oxide layer in silicon chip surface, and some is in, and the silica covalent bond can rupture in the surperficial silicon dioxide molecules, makes silicon atom form dangling bonds.The silicon atom of suspension shows electropositive, can regard silicon face one deck charge layer as.During through hydrophilic treatment, silicon face absorption OH-group forms the silanol key.Two silicon chips that form the silanol keys near the time, can attract each other by the formation hydrogen bond between silanol key, hydrone and the silanol key.The applying period of Here it is bonding.What the silicon chip interface existed is (Si-OH) and hydrone.When temperature raises, following reaction is arranged:

2SiOH→Si-O-Si+H 2O

Be that the silanol key transforms to silicon oxygen bond.This reaction is reversible reaction, and temperature is high more, and the Direction of Reaction carries out to the right more.Here it is, and why high annealing can strengthen bond strength.Process annealing is exactly to require under lower temperature, and reaction can be carried out to the right more fully.This just has following two requirements: (1) silicon chip surface will form the silanol key as much as possible, silicon chip is combined when fitting closely and enough reactants are arranged; (2) the process annealing time will be grown, and is beneficial to hydrone escape and diffusion, and reaction is constantly carried out to positive direction.For the second above point, prolong annealing time and get final product.And first point requires silicon chip that dangling bonds are as much as possible arranged before hydrophilic treatment, so that adsorb a large amount of (OH) groups.With the oxygen plasma Activiation method is example, and it can have following reaction on the oxide layer surface:

Si-O+O +→(Si) ++O 2

Thereby reach the purpose that forms a large amount of silicon dangling bonds, this is the main cause that process annealing can strengthen bonded interface intensity.

Therefore, earlier the bonding surface of lower layer support sheet 1 and the silicon dioxide layer 22 of upper strata silicon chip are carried out activation processing (like chemistry or Cement Composite Treated by Plasma), hydrophilic treatment, so that bonding face forms a large amount of silanol keys.

 

Step 2

With reference to Fig. 2, with the silicon dioxide layer 22 of upper strata silicon 2 and the SiO of lower layer support sheet 1 2Layer 12 is fitted (arrow is the applying direction), and this step can at room temperature be carried out.

With reference to Fig. 3, low-temperature bonding is reinforced upper strata silicon 2 on lower layer support sheet 1.

This step can be carried out with reference to prior art.

 

Step 3

With reference to Fig. 4, through the low-temperature bonding technology, upper strata silicon is ruptured from rich boron, hydrogen layer, thereby rich boron, the above part of hydrogen layer are peeled off in will scheming, and lower part (bonding part) becomes one with lower layer support sheet bonding.

This step can be carried out with reference to prior art.Several different methods is also arranged now, is 5E16cm like dosage -2To 9E16cm -2Notes hydrogen sheet or hydrogen helium annotate sheet altogether and can about 500 ℃, peel off, and boron, hydrogen is annotated the sheet exfoliation temperature altogether can be less than 400 ℃.Even; Containing the bonding pad of annotating hydrogen layer or porous silicon layer can just can at room temperature successfully peel off under mechanism, and these technology all be that the support chip in layer transfer is to have prepared when the device of semiconductor device sheet is arranged required low temperature to peel off technical foundation is provided.

Low temperature solid phase (or liquid phase) growing epitaxial silicon, key forms upper strata silicon layer 3 with part, and is as the basis of preparation upper strata semiconductor device, as shown in Figure 5.This epitaxial growth steps is an optional step, under the enough thick situation of the upper strata silicon layer behind the bonding, can omit.

 

Step 4

Preparation upper strata semiconductor device is as shown in Figure 6 in the upper strata silicon layer 3 that in step 4, obtains.

Deposition ILD layer 23 is as shown in Figure 7 on the upper strata semiconductor device that obtains, and prepares upper strata contact hole 20 and lower floor's contact hole 10, (omitting contact hole in the subsequent figures) as shown in Figure 8 simultaneously.

In this step 5, can adjust the upper strata device position, for example will go up the certain distance that squints between layer device MOS district and the following layer device MOS district, thereby be the preparation lower floor enough spaces of contact hole reservation.

 

Step 5

Preparation amorphous carbon ashing through hole 24 in last layer device, amorphous carbon ashing through hole 24 connect goes up the ILD layer of layer device in following layer device.Amorphous carbon ashing through hole can be the through hole and the position that can arrive down layer device ILD layer arbitrarily, is chosen in the preparation of layer device sti structure top in the present embodiment, amorphous carbon ashing through hole 24 is connected go up layer device ILD layer and sti structure, and is as shown in Figure 9.

 

Step 6

With reference to Figure 10; To descend the ILD layer ashing in the layer device through amorphous carbon ashing through hole 24, form cavity layer 15, preferably ashing fully of the ILD layer in the following layer device; But also allow residue small amount of amorphous carbon, as long as can form the cavity layer with the upper strata device isolation.Since contact hole technology before the amorphous carbon ILD layer ashing treatment preparation accomplish, lower floor's contact hole is simultaneously also as the usefulness of the supporting construction between the semiconductor device layer up and down.

 

Step 7

Above last layer device, deposit dielectric (SiO for example 2), the amorphous carbon through hole should be enough little, so that in the dielectric deposition process, can not get in the cavity layer that forms in the step 6; But the dielectric of deposition preferably can be packed in the amorphous carbon ashing through hole, with the shutoff of amorphous carbon ashing through hole.

Because amorphous carbon ashing through hole is in the preparation of the STI position of last layer device in the present embodiment, therefore, the part that is positioned at STI can not impact device even without by shutoff fully yet.

Remove unnecessary dielectric at last, obtain two-layer semiconductor device, shown in figure 11.

 

More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.

Claims (8)

1. one kind has the preparation method of the two-layer semiconductor device of hole structure in midair, it is characterized in that step comprises:
Step 1 provides patterned lower layer support sheet, and the ILD layer of device is an amorphous carbon layer in the lower layer support sheet, on the ILD of lower layer support sheet layer, deposits the thin layer silicon dioxide layer; Upper strata silicon is provided, and wherein, said upper strata silicon comprises rich boron, hydrogen layer, and comprises the silicon dioxide layer that is positioned at the surface; The silicon dioxide layer of upper strata silicon and the silicon dioxide layer of lower layer support sheet are carried out activation processing and hydrophilic treatment, to increase the silanol key of treatment surface.
2. step is fitted in the silicon dioxide layer of upper strata silicon on the lower layer support sheet surface silica dioxide layer after the processing, and through low-temperature bonding upper strata silicon is fixed on lower layer support sheet surface;
Step 3 through the low temperature lift-off technology, is peeled off upper strata silicon from rich boron, the fracture of hydrogen layer, the part of rich boron, hydrogen layer below is connected as a single entity with lower layer support sheet surface bond;
Step 4, preparation upper strata semiconductor device in the silicon of upper strata; On the upper strata semiconductor device that obtains, form upper strata ILD layer, prepare upper strata contact hole and lower floor's contact hole then.
3. upper strata contact hole and lower floor's contact hole can be disposable or form one by one;
Step 5 prepares amorphous carbon ashing through hole at last layer device then, and said amorphous carbon ashing through hole runs through the ILD layer of layer device to lower layer support sheet;
Step 6 is carried out ashing treatment through said amorphous carbon ashing through hole to the ILD layer in the lower layer support sheet, forms the cavity layer in the ILD position of lower layer support sheet;
Step 7 upwards deposits dielectric in the amorphous carbon ashing through hole in the layer device, with the shutoff of amorphous carbon ashing through hole.
4. preparation method according to claim 1 is characterized in that, said amorphous carbon ashing through hole prepares above the sti structure of last layer device, and amorphous carbon ashing through hole runs through ILD layer and the STI layer of layer device until the ILD of lower layer support sheet layer.
5. preparation method according to claim 3 is characterized in that dielectric is preferably SiO described in the step 7 2
6. preparation method according to claim 1 is characterized in that, also comprises after the step 3: on the part of upper strata silicon and lower layer support sheet bonding, carry out growing epitaxial silicon; Epitaxial growth temperature is controlled at≤and 650 ℃.
7. preparation method according to claim 1 is characterized in that, said lower layer support sheet is selected from body silicon silicon chip, soi wafer, germanium wafer, germanium silicon chip, strain silicon chip.
8. two-layer semiconductor device of method preparation according to claim 1.
CN201210090430.8A 2012-03-31 2012-03-31 Method for producing two layers of semiconductor devices with half empty structure CN102623406B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331759A (en) * 2017-08-21 2017-11-07 厦门华联电子股份有限公司 Exempt from the wafer-level packaging method and LED flip chip packaging body of organic gel

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US6528388B2 (en) * 2000-02-21 2003-03-04 Rohm Co., Ltd. Method for manufacturing semiconductor device and ultrathin semiconductor device
US6821826B1 (en) * 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
CN1610113A (en) * 2004-10-15 2005-04-27 中国科学院上海微系统与信息技术研究所 Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof
US20110018095A1 (en) * 2009-07-27 2011-01-27 International Business Machines Corporation Three dimensional integrated deep trench decoupling capacitors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528388B2 (en) * 2000-02-21 2003-03-04 Rohm Co., Ltd. Method for manufacturing semiconductor device and ultrathin semiconductor device
US6821826B1 (en) * 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
CN1610113A (en) * 2004-10-15 2005-04-27 中国科学院上海微系统与信息技术研究所 Three-dimensional complementary metal oxide semiconductor device structure and producing method thereof
US20110018095A1 (en) * 2009-07-27 2011-01-27 International Business Machines Corporation Three dimensional integrated deep trench decoupling capacitors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331759A (en) * 2017-08-21 2017-11-07 厦门华联电子股份有限公司 Exempt from the wafer-level packaging method and LED flip chip packaging body of organic gel

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