CN1592963A - 利用三元铜合金获得低电阻与大颗粒尺寸互连的方法 - Google Patents

利用三元铜合金获得低电阻与大颗粒尺寸互连的方法 Download PDF

Info

Publication number
CN1592963A
CN1592963A CNA028234405A CN02823440A CN1592963A CN 1592963 A CN1592963 A CN 1592963A CN A028234405 A CNA028234405 A CN A028234405A CN 02823440 A CN02823440 A CN 02823440A CN 1592963 A CN1592963 A CN 1592963A
Authority
CN
China
Prior art keywords
perforation
copper
alloy
conducting shell
ternary copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA028234405A
Other languages
English (en)
Other versions
CN1320630C (zh
Inventor
S·洛帕京
P·R·贝瑟
P－C·C·王
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1592963A publication Critical patent/CN1592963A/zh
Application granted granted Critical
Publication of CN1320630C publication Critical patent/CN1320630C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种制造集成电路的方法，系包括沿着横向侧壁与贯孔的底层形成阻障层并于该贯孔中提供三元(temary)铜合金贯孔材料以形成贯孔。该贯孔的形成被用来接收该三元铜合金贯孔材料并电性连接第一传导层与第二传导层。该三元铜合金贯孔材料有助于该贯孔具有较低的电阻以及具有足够颗粒边界的增大颗粒尺寸。

Description

利用三元铜合金获得低电阻与大颗粒尺寸互连的方法
技术领域
本发明大体上涉及一种集成电路以及集成电路的制造方法。尤其涉及一种利用三元铜合金以取得低电阻与大颗粒尺寸互连的方法。
背景技术
半导体装置或集成电路(ICs)中可包括有数以百万计如晶体管的装置。超大规模集成电路(Ultra-large Scale Integration；ULSI)可包括互补金属氧化半导体(CMOS)场效应晶体管(FET)。尽管公知的系统与方法已具有于单一集成电路上制造数以百万计的集成电路装置的能力，然仍需要缩小集成电路形体尺寸，并因而增加单一集成电路上装置的数量。然而有许多因素致使集成电路持续缩小化遭遇到困难。举例而言，贯孔(或介于集成电路层间用以电性连接相分离传导层的通道)尺寸的缩小、电阻的增加等。
公知的集成电路利用贯孔连接结构(如闸极、漏极区域、源极区域等)与传导线。贯孔典型的为延伸通过绝缘层的金属连接(metal plug)。阻障层则用以保护该贯孔不受金属扩散与电迁移(electromigration；EM)的影响。阻障层可提供足够的电阻与贯孔金属结合。因介于传导电子与扩散金属原子洞量交换之故电迁移系为质量输送。电迁移会对于集成电路中的金属导体造成累进的损害。一般而言，此为在非常高电流密度以及摄氏100度或更高的温度下金属的特性。
当通过减少阻障材料的厚度而缩小贯孔尺寸时集成电路制造者已尝试着减少贯孔电阻。依据一种公知的电浆气相沉积(Plasma VaporDeposition；PVD)制造过程，由于非一致的沉积集成电路制造者沉积非常薄的阻障材料于该贯孔的底部。该阻障材料的厚度系通过化学气相沉积(Chemical Vapor Deposition；CVD)原子层沉积(Atomic LayerDeposition；ALD)予以减少。这些先进的沉积制造过程可形成高一致性阻障材料薄膜。然而，减少阻障的厚度会导致该阻障变得更容易造成铜扩散的渗入，且对于阻挡电迁移也有不利的影响。
图1A与1B用以显示集成电路的部分100的概略断面图，该集成电路包括铜层110、铜贯孔120、铜层130、介电层150以及介电层160。贯孔120系通过阻障层140与铜层130相分离。
部分100还包括介电层142，该介电层142通过蚀刻终止层174与铜层130相分离。介电层142可为氧化层而该蚀刻终止层174可为氮化硅(SiN)。蚀刻终止层174防止来自铜层130的铜扩散至介电层142中。介电层150可通过阻障层152与铜层130相分离。同样的，介电层160可通过阻障层182与铜层110相分离。阻障层152与182可为氮化钽(TaN)。蚀刻终止层172、174、176以及178则可为氮化硅(SiN)。
依据公知的制造过程，阻障层140具有介于7纳米至25纳米间的断面厚度。阻障层140可阻止来自该些层的铜离子扩散至贯孔120中并由该贯孔扩散至介电层142中。公知的阻障层可包括氮化钽(TaN)。
图图1A用以显示依据单镶嵌(damascene)制造过程所形成的部分，其中铜层110与铜贯孔120是在二相分离的步骤中予以沉积并通过阻障区段182相分离。图图1B用以显示依据双镶嵌制造过程所形成的部分，其中铜层110与铜贯孔120是在单一的步骤或制造过程中予以沉积且并未通过阻障物相分离。
如上所述，公知的系统已尝试减少该阻障层140的厚度以减少与该贯孔120相关的电阻。然而，如此的厚度减少会导致电迁移故障。图2A与2B用以显示图1A与1B中的部分100，其于铜层130中复具有电迁移故障或孔隙145。图2A显示依据单镶嵌制造过程(如上述图1A所示)所形成的部分，其中铜层110与铜贯孔120是在二相分离的步骤或制造过程中予以形成。图2B显示依据双镶嵌制造过程(如上述图1B所示)所形成的部分，其中铜层110与铜贯孔120是在单一步骤或制造过程中予以形成。
图3A与3B用以显示因来自铜贯孔层120的铜扩散故于贯孔120中具有电迁移故障或孔隙155的部分100。第3A图显示依据单镶嵌制造过程(如上述图1A所示)所形成的部分，其中铜层110与铜贯孔120是在二相分离的步骤或制造过程中予以形成。图3B显示依据双镶嵌制造过程(如上述图1B所示)所形成的部分，其中铜层110与铜贯孔120是在单一步骤或制造过程中予以形成。
关于电迁移故障的描述已见诸于美国加州日落海滩Lattice Press出版由史坦利伍尔夫博士所著的「超大规模集成电路年代的硅制造过程」第2卷第264-65页中。伍尔夫博士解释导体的离子运动的正偏离(positive divergence)会导致空间的累积，进而于该金属中形成孔隙。这些孔隙最终会长到足以导致该传导线产生开路故障的尺寸。
因此，亟需要一种具有低电阻且无需遭受贯孔或线路电迁移故障的互连(interconnect)或贯孔。此外，亦需要一种形成具有足够的颗粒边界以达到高电迁移信赖性的大颗粒尺寸互连的方法。再者，还需要一种利用三元铜合金以获得低电阻与大颗粒尺寸互连的方法。
【发明内容】
例示的实施例是关于一种制造集成电路的方法。此方法包括沿着横向侧壁与贯孔的底层形成阻障层并在该贯孔中提供三元铜合金贯孔材料以形成贯孔。该贯孔的形成系用以接收该三元铜合金贯孔材料并电性连接第一传导层与第二传导层。该三元铜合金贯孔材料有助于该贯孔具有较低的电阻以及具有足够颗粒边界的增大颗粒尺寸。
另一例示的实施例是关于一种利用三元铜合金以获得低电阻与大颗粒尺寸互连或贯孔的方法。此方法包括形成覆盖于集成电路基材上的第一传导层，在设置在第一传导层上的贯孔的底部与侧边形成保形(conformal)层区段借以形成分离该贯孔与第一传导层的阻障，填充三元铜合金贯孔材料至该贯孔中借以形成三元铜合金贯孔，以及形成覆盖于该三元铜合金贯孔的第二传导层借以令该三元铜合金贯孔电性连接该第一传导层与第二传导层。
又一例示的实施例是关于一种在集成电路中形成贯孔的方法。此方法包括沉积第一传导层，沉积蚀刻终止层于该第一传导层上，沉积绝缘层于该蚀刻终止层上，在该绝缘层与蚀刻终止层中形成贯孔，在该贯孔的底部与侧边形成阻障材料借以形成阻障层，填充三元铜合金贯孔材料至该贯孔中借以形成三元铜合金贯孔，以及形成第二传导层于该三元铜合金贯孔上据此该三元铜合金贯孔可电性连接该第一传导层与第二传导层。
本发明的其它原理特性与优点对于本领域普通技术人员在浏览过以下的图式、详细说明以及申请专利范围后将更为明了。
附图说明
例式的实施例将伴随以下的图式予以说明，相同的组件具有相同的符号；
图1A用以显示依据公知技术所制造的集成电路的单镶嵌部分的概略断面图；
图1B用以显示依据公知技术所制造的集成电路的双镶嵌部分的概略断面图；
图2A为图1A中的集成电路的单部分的概略断面图，用以显示电迁移故障；
图2B为图1B中的集成电路的双部分的概略断面图，用以显示电迁移故障；
图3A为图1A中的集成电路的单镶嵌部分的概略断面图，用以显示电迁移故障；
图3B为图1B中的集成电路的双镶嵌部分的概略断面图，用以显示电迁移故障；
图4为集成电路的部分的概略断面图，用以显示例示实施例中的三元铜合金互连；
图5为集成电路的部分的顶部概略断面图，用以显示另一例示实施例中的三元铜合金互连结构；
图6为集成电路的部分的概略断面图，用以显示又一例示实施例中的三元铜合金互连；以及
图7为集成电路的部分的概略断面图，用以显示再一例示实施例中的三元铜合金互连。
具体实施方式
请参阅图4，其用以显示集成电路的部分400的概略断面图，该集成电路包括传导贯孔层410，传导层与贯孔区段420，传导层430，阻障层440，介电层450，以及介电层460。部分400较佳的可为具有数百万或更多晶体管的超大规模集成电路的一部分。部分400为如同硅晶片等的半导体晶片上的集成电路的部分予以制造。
部分400还可包括通过蚀刻终止层474与该传导层430分离的介电层442。在例示的实施例中，介电层442为氧化材料而蚀刻终止层474则为氮化硅(Si3N4)或其它适当的材料。蚀刻终止层474可防止材料自传导层430扩散至介电层442中。传导贯孔层410可为任何一种如铜或其它材料的传导材料层。
介电层450可通过阻障层462与铜层430相分离，相同的，介电层460可通过阻障层482与铜层410相分离。阻障层462与482可为氮化钽。蚀刻终止层472、274、476以及478可为氮化硅。
传导层与贯孔区段420可由传导材料所组成并用以电性连接传导层410与传导层430。传导层与贯孔区段420可包括三元铜合金，亦即Cu-X-Y。X可为具有低电阻特性的不同种类元素的任一者，如锌、银或锡等。Y可为具有增加颗粒尺寸特性的不同种类元素的任一者，如钙或铬等。
有益的，贯孔区段420的三元铜合金提供低电阻互连或贯孔，大颗粒尺寸互连以及足够的颗粒边界。由于晶体结构影响铜离子的迁移率故大颗粒尺寸可提升电迁移信赖性。大颗粒尺寸复提供较低的互连电阻。由于沿着颗粒边界的铜扩散通道的减少或限制故足够的颗粒边界可增加电迁移信赖性。
传导层与贯孔区段420的材料可利用电化学沉积(ElectrochemicalDeposition；ECD)-无电电镀及/或电镀方式予以沉积。作为电化学沉积的种晶层可通过原子层沉积/化学气相沉积及/或电浆气相沉积/离子金属电浆(PVD/IMP)，自我离子化电浆(SIP)等予以形成。于一例式中，铜-X-Y的三元铜合金可为铜-锡-铬，其中锡的原子量百分比小于1且铬的原子量百分比亦小于1。于另一例示中，铜-X-Y可为铜-锌-铬，其中锌的原子量百分比小于1且铬的原子量百分比亦小于1。在铜-锌-铬的情况下，所减少的电阻可为1.8至2.2电阻率(μΩcm)间而增加的颗粒尺寸则可介于0.5至3微米间。
作为铜-锌-铬合金沉积的电镀溶液可包括作为铜离子源的铜盐(Cusalt)，作为锌离子源的锌盐(Zn salt)，作为铬离子源的铬盐(Cr salt)，金属离子错合剂(complexing agents)，酸调整剂(pH adjuster)以及有机添加剂。优化在溶液中的金属离子的浓度比例以形成铜-锌-铬薄膜，该铜-锌-铬薄膜具有在合金薄膜中小于1的原子量百分比的锌与铬。错合剂可选自由乙二胺(ethylenediamine)、乙烯二胺四乙酸(Ethylenediaminetetraacetic acid)以及酒石酸(tartaric acid)所组成的群组。有机添加剂可选自聚丙烯glycoles(polypropylene glycoles)，聚乙烯glycoles(polyethylene glycoles)以及硫醇硫醚类(mercaptandisulfides)所组成的群组并提供适当的条件用作为贯孔/沟槽区域形状的生长借以完成铜-锌-铬填料并用以形成不具有孔隙的传导贯孔层。
执行电镀后的铜-锌-铬层的退火以完成再结晶制造过程进一步致使颗粒尺寸增加以及电阻减少。
可利用化学机械研磨，化学研磨及/或电解研磨以从该介电层移除铜-锌-铬以及阻障层以形成平坦表面以备后续的介电层沉积。
传导层430可为设置于接近贯孔区段420的位置的铜层。传导层430可包括含有铜的合金。在另一替代的实施例中，传导层430可为数个层的堆叠。
阻障层440可为钽、氮化钽、氮化钛、氮化钛硅(TiSiN)、氮化钨或其它适当的材料。在一例示实施例中，阻障层440具有5至10纳米的断面厚度。于另一实施例中，阻障层440具有2至5纳米小的尺寸。
在例示的双镶嵌制造部分400的方法中，当传导层430完成沉积时，蚀刻终止层474沉积于传导层430上而介电层442则沉积于蚀刻终止层474上。沉积光阻层于介电层442上并用以图案化与蚀刻贯孔区段420结构中的介电层442以及蚀刻终止层474的贯孔。在例式的实施例中贯孔与沟槽区段具有二个不同的宽度，二个不同的光阻层可应用在二步骤贯孔/沟槽形成制造过程中。在沉积贯孔/沟槽材料于传导层与贯孔区段420之前移除该一个或多个光阻层。形成传导贯孔层410以电性连接传导层420。
请参阅图5，集成电路的部分500包括具有三元铜合金的双镶嵌贯孔/沟槽区段。由于锡与铬的添加，因此贯孔/沟槽区段可包括增大的颗粒尺寸520，减少的电阻以及足够的颗粒边界510。通过增大的颗粒尺寸，足够的颗粒边界510以及减少的电阻，贯孔/沟槽区段可具有改良的电迁移信赖性。如图4中相关的说明，可利用不同的技术以包括低电阻组件与增大颗粒尺寸的组件。亦可利用不同种类的组件以及组件的组合。
图6用以显示集成电路双镶嵌部分600的概略断面图，其包括传导层610，贯孔/沟槽区段620，传导层630，阻障层640，介电层650以及介电层660。部分600还包括通过蚀刻终止层644与传导层630相分离的介电层642。除了在与贯孔/沟槽区段420的窄互连形状相比较具有较宽互连形状的贯孔/沟槽区段620之外，部分600与图4的部分400相同。
介电层可包括通过化学气相沉积或旋转涂布技术(spin-on)形成的低介电常数材料。低介电常数材料的介电常数k可于1.5至3.5间且可包括孔隙率介于百分之10至45间的含孔材料。孔的尺寸可为1至15纳米间。
介电层650可通过阻障层652与铜层630相分离。同样的，介电层660可通过阻障层682与铜层610相分离。阻障层652与682可为氮化钽。蚀刻终止层672、674、676以及678可为氮化硅。
图7用以显示集成电路单镶嵌部分700的概略断面图，其包括传导层710，贯孔区段720，传导层730，阻障层740，介电层750以及介电层760。部分700复包括通过蚀刻终止层744与传导层730相分离的介电层742。
在贯孔或互连结构中应用三元铜合金可有助于提升可靠性与效能。举例而言，由于足够的颗粒边界故可提升电迁移可靠性。此外，增加的颗粒尺寸亦可改善电迁移。
上述实施例仅为例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域普通技术人员均能在不违背本发明的精神及范畴下，对上述实施例进行修饰与变化。因此，本发明的权利保护范围，应如后述的申请专利范围所列。

Claims (10)

1.一种制造集成电路(400)之方法，其包含：
沿着横向侧壁与贯孔的底层形成阻障层(440)，该贯孔之形成被用来接收贯孔材料并电性连接第一传导层(410)与第二传导层(420)；以及
在该贯孔中提供三元铜合金贯孔材料以形成贯孔(420)。
2.一种利用三元铜合金以获得低电阻与大颗粒尺寸互连或贯孔的方法，其包含：
形成覆盖于集成电路基材上之第一传导层(430)
在设置在第一传导层(430)上之贯孔的底部与侧边形成保形层区段(440)借以形成分离该贯孔与第一传导层(430)之阻障；
填充三元铜合金贯孔材料至该贯孔中借以形成三元铜合金贯孔(420)；以及
形成覆盖于该三元铜合金贯孔(420)之第二传导层(410)借以令该三元铜合金贯孔(420)电性连接该第一传导层(410)与第二传导层(430)。
3.如权利要求1或2所述的方法，其中该三元铜合金贯孔材料包括具有低电阻特性之元素。
4.如权利要求3所述的方法，其中该具有低电阻特性之元素可为锌、银或锡。
5.如权利要求3所述的方法，其中该三元铜合金贯孔材料中具有低电阻特性元素之原子量百分比为1或小于1。
6.如权利要求1或2所述的方法，其中该三元铜合金贯孔材料包括具有增加颗粒尺寸特性之元素。
7.如权利要求6所述的方法，其中该具有增加颗粒尺寸特性之元素可为钙或铬。
8.如权利要求6所述的方法，其中该三元铜合金贯孔材料中具有增加颗粒尺寸特性元素之原子量百分比为1或小于1。
9.如权利要求6所述的方法，其中该颗粒尺寸系介于0.5至3.0微米间。
10.如权利要求2所述的方法，其中该三元铜合金贯孔材料包含铜-银-铬、铜-锡-钙、铜-锆-钙或铜-银-钙。
CNB028234405A 2001-11-26 2002-10-11 利用三元铜合金获得低电阻与大颗粒尺寸互连的方法 Expired - Fee Related CN1320630C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/994,395 2001-11-26
US09/994,395 US7696092B2 (en) 2001-11-26 2001-11-26 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

Publications (2)

Publication Number Publication Date
CN1592963A true CN1592963A (zh) 2005-03-09
CN1320630C CN1320630C (zh) 2007-06-06

Family

ID=25540628

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028234405A Expired - Fee Related CN1320630C (zh) 2001-11-26 2002-10-11 利用三元铜合金获得低电阻与大颗粒尺寸互连的方法

Country Status (7)

Country Link
US (1) US7696092B2 (zh)
EP (1) EP1449247A2 (zh)
JP (1) JP4463555B2 (zh)
KR (1) KR100966359B1 (zh)
CN (1) CN1320630C (zh)
AU (1) AU2002335805A1 (zh)
WO (1) WO2003046979A2 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696092B2 (en) 2001-11-26 2010-04-13 Globalfoundries Inc. Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
US7989338B2 (en) * 2005-06-15 2011-08-02 Globalfoundries Singapore Pte. Ltd. Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
JP5234306B2 (ja) * 2006-10-18 2013-07-10 三菱マテリアル株式会社 熱欠陥発生が少なくかつ表面状態の良好なｔｆｔトランジスターを用いたフラットパネルディスプレイ用配線および電極並びにそれらを形成するためのスパッタリングターゲット
US8575019B2 (en) * 2010-09-30 2013-11-05 Institute of Microelectronics, Chinese Academy of Sciences Metal interconnection structure and method for forming metal interlayer via and metal interconnection line
DE112012005535T5 (de) * 2011-12-28 2014-09-11 Yazaki Corporation Ultrafeines Leitermaterial, ultrafeiner Leiter, Verfahren zum Vorbereiten eines ultrafeinen Leiters und ultrafeinener Leitungsdraht
JP5987443B2 (ja) * 2012-04-19 2016-09-07 富士通株式会社 操作動作検出装置、操作動作検出方法、及びプログラム
KR102211741B1 (ko) * 2014-07-21 2021-02-03 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
US9431343B1 (en) 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
KR20220030455A (ko) * 2020-09-01 2022-03-11 삼성전자주식회사 반도체 장치

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908275A (en) * 1987-03-04 1990-03-13 Nippon Mining Co., Ltd. Film carrier and method of manufacturing same
JPH0750697B2 (ja) 1989-02-20 1995-05-31 株式会社東芝 半導体装置の製造方法
US5224520A (en) * 1990-11-19 1993-07-06 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Weaving bar prevention in a jet loom
US5243222A (en) * 1991-04-05 1993-09-07 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
JP2534434B2 (ja) 1992-04-30 1996-09-18 インターナショナル・ビジネス・マシーンズ・コーポレイション 耐酸化性化合物およびその製造方法
KR960010056B1 (ko) 1992-12-10 1996-07-25 삼성전자 주식회사 반도체장치 및 그 제조 방법
US5654245A (en) 1993-03-23 1997-08-05 Sharp Microelectronics Technology, Inc. Implantation of nucleating species for selective metallization and products thereof
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
DE69637333T2 (de) * 1995-06-27 2008-10-02 International Business Machines Corp. Kupferlegierungen für Chipverbindungen und Herstellungsverfahren
JP3296709B2 (ja) * 1995-07-10 2002-07-02 古河電気工業株式会社 電子機器用薄板銅合金およびその製造方法
US6268291B1 (en) 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
KR100243286B1 (ko) 1997-03-05 2000-03-02 윤종용 반도체 장치의 제조방법
US5770517A (en) 1997-03-21 1998-06-23 Advanced Micro Devices, Inc. Semiconductor fabrication employing copper plug formation within a contact area
US5969422A (en) 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6069068A (en) 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US5821168A (en) 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US5882738A (en) 1997-12-19 1999-03-16 Advanced Micro Devices, Inc. Apparatus and method to improve electromigration performance by use of amorphous barrier layer
US6344413B1 (en) 1997-12-22 2002-02-05 Motorola Inc. Method for forming a semiconductor device
US6482734B1 (en) * 1998-01-20 2002-11-19 Lg Semicon Co., Ltd. Diffusion barrier layer for semiconductor device and fabrication method thereof
KR100404649B1 (ko) * 1998-02-23 2003-11-10 가부시끼가이샤 히다치 세이사꾸쇼 반도체장치 및 그 제조방법
JP3955386B2 (ja) 1998-04-09 2007-08-08 富士通株式会社 半導体装置及びその製造方法
US6156638A (en) 1998-04-10 2000-12-05 Micron Technology, Inc. Integrated circuitry and method of restricting diffusion from one material to another
US6181012B1 (en) * 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6015749A (en) 1998-05-04 2000-01-18 Taiwan Semiconductor Manufacturing Company Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure
US6461675B2 (en) 1998-07-10 2002-10-08 Cvc Products, Inc. Method for forming a copper film on a substrate
US6380083B1 (en) * 1998-08-28 2002-04-30 Agere Systems Guardian Corp. Process for semiconductor device fabrication having copper interconnects
US6144096A (en) 1998-10-05 2000-11-07 Advanced Micro Devices, Inc. Low resistivity semiconductor barrier layers and manufacturing method therefor
US6117770A (en) 1998-10-08 2000-09-12 Advanced Micro Devices, Inc. Method for implanting semiconductor conductive layers
KR100385042B1 (ko) * 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법
US6294836B1 (en) * 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
US6096648A (en) 1999-01-26 2000-08-01 Amd Copper/low dielectric interconnect formation with reduced electromigration
KR100309642B1 (ko) 1999-01-29 2001-09-26 김영환 반도체장치의 콘택 형성방법
JP3910752B2 (ja) 1999-03-23 2007-04-25 株式会社東芝 半導体装置の製造方法
US6521532B1 (en) 1999-07-22 2003-02-18 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance
US6159845A (en) * 1999-09-11 2000-12-12 United Microelectronics Corp. Method for manufacturing dielectric layer
US6440849B1 (en) * 1999-10-18 2002-08-27 Agere Systems Guardian Corp. Microstructure control of copper interconnects
KR20020070443A (ko) * 1999-11-24 2002-09-09 허니웰 인터내셔널 인코포레이티드 전도성 상호연결장치
CN1155057C (zh) * 1999-12-02 2004-06-23 国际商业机器公司 形成电子结构中铜导体的方法
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6376370B1 (en) * 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
US6225221B1 (en) 2000-02-10 2001-05-01 Chartered Semiconductor Manufacturing Ltd. Method to deposit a copper seed layer for dual damascene interconnects
US6627995B2 (en) * 2000-03-03 2003-09-30 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
US6410383B1 (en) 2000-03-16 2002-06-25 Sharp Laboratories Of America, Inc. Method of forming conducting diffusion barriers
US6426289B1 (en) 2000-03-24 2002-07-30 Micron Technology, Inc. Method of fabricating a barrier layer associated with a conductor layer in damascene structures
US6423633B1 (en) * 2000-04-10 2002-07-23 Vanguard International Semiconductor Corp. Method for manufacturing diffusion barrier layer
TW508658B (en) * 2000-05-15 2002-11-01 Asm Microchemistry Oy Process for producing integrated circuits
US6749699B2 (en) * 2000-08-09 2004-06-15 Olin Corporation Silver containing copper alloy
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6294463B1 (en) * 2000-09-13 2001-09-25 Vanguard International Semiconductor Corp. Method for manufacturing diffusion barrier layer
US6977224B2 (en) * 2000-12-28 2005-12-20 Intel Corporation Method of electroless introduction of interconnect structures
US6465867B1 (en) * 2001-02-21 2002-10-15 Advanced Micro Devices, Inc. Amorphous and gradated barrier layer for integrated circuit interconnects
US6500749B1 (en) * 2001-03-19 2002-12-31 Taiwan Semiconductor Manufacturing Company Method to improve copper via electromigration (EM) resistance
US6534865B1 (en) 2001-06-12 2003-03-18 Advanced Micro Devices, Inc. Method of enhanced fill of vias and trenches
US7696092B2 (en) 2001-11-26 2010-04-13 Globalfoundries Inc. Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

Also Published As

Publication number Publication date
US7696092B2 (en) 2010-04-13
KR20040064287A (ko) 2004-07-16
KR100966359B1 (ko) 2010-06-28
CN1320630C (zh) 2007-06-06
AU2002335805A1 (en) 2003-06-10
JP2005510875A (ja) 2005-04-21
JP4463555B2 (ja) 2010-05-19
AU2002335805A8 (en) 2003-06-10
WO2003046979A3 (en) 2003-10-30
US20040005773A1 (en) 2004-01-08
EP1449247A2 (en) 2004-08-25
WO2003046979A2 (en) 2003-06-05

Similar Documents

Publication Publication Date Title
KR102526836B1 (ko) 코발트계 인터커넥트 및 그의 제조 방법
US10332838B2 (en) Schemes for forming barrier layers for copper in interconnect structures
US6703307B2 (en) Method of implantation after copper seed deposition
EP2248164B1 (en) Microstructure modification in copper interconnect structure
US10686126B2 (en) Back end of line metallization structures
US7611984B2 (en) Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy
US6998342B2 (en) Electronic device manufacturing method
US20120077053A1 (en) Barrier layers
CN101034695A (zh) 半导体结构和制造半导体结构的方法
CN1320630C (zh) 利用三元铜合金获得低电阻与大颗粒尺寸互连的方法
CN101051632A (zh) 互连结构及其制造方法
US6724087B1 (en) Laminated conductive lines and methods of forming the same
US7169706B2 (en) Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition
US11177163B2 (en) Top via structure with enlarged contact area with upper metallization level
US6835655B1 (en) Method of implanting copper barrier material to improve electrical performance
KR20040006116A (ko) 구리 배선의 형성 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: ADVANCED MICRO DEVICES INC

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC.

Effective date: 20100709

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, USA TO: GRAND CAYMAN ISLAND RITISH CAYMAN ISLANDS

TR01 Transfer of patent right

Effective date of registration: 20100709

Address after: Grand Cayman, Cayman Islands

Patentee after: Globalfoundries Semiconductor Inc.

Address before: American California

Patentee before: Advanced Micro Devices Inc.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070606

Termination date: 20181011

CF01 Termination of patent right due to non-payment of annual fee