CN1588612A - Direct bonding method for indium phosphide and gallium arsenide materials - Google Patents
Direct bonding method for indium phosphide and gallium arsenide materials Download PDFInfo
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- CN1588612A CN1588612A CN 200410052711 CN200410052711A CN1588612A CN 1588612 A CN1588612 A CN 1588612A CN 200410052711 CN200410052711 CN 200410052711 CN 200410052711 A CN200410052711 A CN 200410052711A CN 1588612 A CN1588612 A CN 1588612A
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Abstract
The invention relates to direct bonding method of InP and GaAs including thee technical processes of surface cleaning, laminating and high-temp annealing. The characteristic is that surface of InP and GaAs is processed two times by deoxidizing before bonding, then it is direct soaked in reducibility nitrogen solution without drying by high-purity nitrogen, after being soaked, it is direct put into anti-oxide alcohol solution. Laminate is processed in the alcohol solution, burnishing surface of InP is downward to be put on burnishing surface of GaAs straight, InP and GaAs are coincided together that side and side are aligned, bonding temp. is from 500 to 700 deg.C, annealed after being bonded, keeping time is from 30 to 40 minutes, both bonding and annealing are proceeded by nitrogen protection. Optical and electrical performance of whole material structure can not be reduced since the bonded IP and GaAs interface.
Description
Technical field
The invention provides the Direct Bonding method of a kind of III-V compound semiconductor indium phosphide (InP) and GaAs (GaAs) material, belong to semi-conductor photoelectronic, microelectronic component technology field.
Background technology
Along with the development of epitaxial growth of semiconductor material technology such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition technology such as (MOCVD), III-V family semiconductor material growing can very accurately be controlled parameters such as its growth thickness, component.Yet the semiconductor material growing system but has been subjected to the very big restriction of storeroom lattice mismatch and coefficient of thermal expansion mismatch, when the thickness of growth material greater than by the critical thickness of this material system mismatch degree decision the time, to produce dislocation in the material, the dislocation line epi-layer surface of can climbing from the interface of dissimilar materials, in epitaxial material, introduce defective thus, thereby greatly influence device performance; Under big lattice mismatch situation, dislocation can make device material work.For example, the lattice mismatch between InP and the GaAs semi-conducting material is up to 3.8%, and also there is bigger difference in thermal coefficient of expansion, and the thermal coefficient of expansion of GaAs is 5.8 * 10
-6/ K, the thermal coefficient of expansion of InP are 4.5 * 10
-6/ K.Therefore, picture InGaAs, InAsP, microelectronics such as InGaAsP, photoelectron fine structure material, can only on the InP substrate, just can grow the epitaxial material of low-dislocation-density, on the other hand, then can only on the GaAs substrate, just can grow high-quality epitaxial loayer as the AlGaAs material, in order to reach excellent device performance, people often need these combinations of materials of growing on different substrates to together, and how InP base fine structure material, set of devices being installed on the GaAs sill is one of the focus in domestic and international III-V family semiconducter research field.
The Direct Bonding technology of InP and GaAs material has very important application prospects in photoelectron and microelectronic component manufacturing, for example, vertical cavity surface emitting laser (VCSEL) has been subjected to greatly paying close attention to and research widely in the application of optical communication field in recent years, compare with traditional edge-emitting laser, surface-emitting laser has advantages such as single mode operation, high modulation bandwidth, high coupling efficiency, low-power consumption.Surface-emitting laser is made up of two distribution Bragg reflectors (DBR) and the luminescent active region that is clipped in wherein.Owing to the shortcoming of material self performance, be operated in the InP basal plane emitting laser of 1.3 μ m and 1.55 μ m, be subjected to the restriction of InP base distribution Bragg reflector thermal conductivity, conductivity and reflectivity.And GaAs base distribution Bragg reflector is much more superior than the InP base in this respect, therefore utilizes bonding techniques, obtains the combined material of high-quality InP-GaAs optics and electric property, is one of important channel of realizing high performance vertical cavity surface emitting laser.
The Direct Bonding technology is different from epitaxy technology.Epitaxy technology is arranged by the thermodynamic process in the growth course, atom condenses in substrate surface migration and absorption, with the substrate lattice is that template is piled up the epitaxial material atomic layer, when the epitaxial material lattice constant is different from substrate, lattice mismatch stress excessive when atom is stacked to certain thickness is no longer piled up foreign atom in strict accordance with substrate, promptly produce dislocation; And bonding process is to occur in epitaxial material at the interface, under certain impressed pressure and temperature, the counterdiffusion of atom phase also forms chemical bond and makes two layers of material bonding securely, even therefore two layers of material has very big lattice mismatch, only be present near the material interface through dislocation behind the bonding, and can not expand in the whole material, this influences the performance of material behind the bonding hardly.Though the InP sill has some bibliographical informations with the bonding techniques of GaAs sill in the world: all have different shortcomings:
Document [1] [Z.L.Liau and D.E.Mull, Wafer fusion:A novel technique foroptoelectronic device fabrication and monolithic integration, Appl.Phys.Lett., Vol.56, No.8,737 (1990)] though also reported the Direct Bonding method of InP and GaAs, principal character is the temperature height that adopt (1), be 830 ℃, too high temperature can cause the decomposition of III-V compounds of group; (2) the added pressure of anchor clamps can not be adjusted;
Document [2] [Yae Okuno, Kazuhisa Uomi, Masahiro Aoki, and TomonobuTsuchiya, Direct wafer bonding of III-V compound semiconductors forfree-material and free-orientation integration, IEEE Journal of QuantumElectronics, Vol.33, No.6,959 (1997)] report is the bonding of InP base epitaxial film, be that to dry up the back with nitrogen superimposed in air, easily oxidation causes that to be bonded to power not high;
Document [3] [H.C.Lin, K.L.Chang, G.W.Pickrell, K.C.Hsieh, and K.Y.Cheng, Low temperature wafer bonding by spin on glass, J.Vac.Sci.Technol.B Vol.20 No.2., 752 (2002)] then be to introduce to come bonding InP and GaAs material with Spin on glass (SOG) medium, SOG is silanol and the solvate of methyl macromolecule in alcohol, though bonding temperature is lower, but because bonding medium has certain thickness, poorly conductive, shortcomings such as absorbing light, so limitation is bigger.
Summary of the invention
The object of the invention is to provide a kind of Direct Bonding method that is used to carry out III-V group iii v compound semiconductor material InP and GaAs.
Bonding process comprises three steps: cleaning surfaces, lamination and high annealing.InP and GaAs substrate are through the removal of surface organic matter and oxide, and surface roughness is below tens dusts.When the sample of two cleanings in methanol solution face-to-face, be superimposed with each other to the edge-to-edge, the methanol solution that is in has therebetween partly stoped interior during this period of time before air of arrival annealing temperature and dust to enter contact interface, and whole annealing process is carried out under nitrogen atmosphere.When the sample annealing temperature arrived 200～400 ℃, methyl alcohol, steam and other chemical reactants were at first escaped from the InP-GaAs contact interface, and when elevated temperature arrives 500～700 ℃, the migration of atom took place at the interface.At first the P that decomposes from InP surface is gradually to the diffusion of GaAs face and be filled in slot between contact interface, but GaAs body material has stoped the inside diffusion of P simultaneously, this makes that P air pressure raises gradually between the interface, the rising of P air pressure has then weakened the decomposition of InP, the stable distribution of therefore last interface and near formation P thereof; Because the remaining unnecessary In in the decomposition InP of P surface, the In atom mainly also is filled in because the small empty place that interface random fluctuation forms at lateral migration morely, the pressure that adds in such atomic migration process and this process makes original InP-GaAs contact interface room and slot major part be filled by In atom and P atom, and therefore InP contacts tightr with GaAs.When the annealing end temp reduces, near material generation recrystallization process interface and the both sides, form the InGaAsP unformed layer of one deck chemical bond combination, InP and GaAs rely on this one deck unformed layer to be bonded together, the quality of bonding by the surface cleaning degree, add pressure, annealing temperature and annealing time and determine jointly.Mainly be that the near interface atom moves in the bonding process, InP and GaAs material internal do not change, yet because InP and GaAs lattice mismatch are very big, the bonded interface place then has a large amount of dislocation groups to produce, experimental results show that such bonded interface with a large amount of dislocations does not make InP-GaAs material structure degradation behind the bonding, this has the different of essence with direct epitaxially grown InP-GaAs is heterogeneous.On the contrary, the optics that 500～700 ℃ annealing process may be improved material in the bonding process closes electric property.
The Direct Bonding method of a kind of InP provided by the invention and GaAs is characterized in that:
(a) InP and GaAs substrate are cleaved into square or rectangular;
(b) cleaning substrate is to use isopropyl alcohol, acetone and absolute ethyl alcohol ultrasonic cleaning successively, uses rinsed with deionized water more than 3 minutes then, and dries up with high pure nitrogen.Described cleaning sample strip each 3 times, each 3-5 minute;
(c) remove InP and GaAs oxide on surface, InP is at static H
2SO
4+ H
2O
2+ H
2Corrode in the O solution, three's volume ratio is 3: 1: 1; Time is for corroding 5-15 second; GaAs is at static H
2SO
4+ H
2Corrode in the O solution, the volume ratio of the two is 1: 20; Etching time is used rinsed with deionized water for 30-60 etches the back second, then InP and GaAs sheet is dried up direct immersion HF+H without high pure nitrogen
2In the O solution, HF and H
2The volume ratio of O is 1: 10; Use deionized water rinsing 3-5 time again, and above corrosion process is carried out under 20-25 ℃ of room temperature all;
(d) removing InP and GaAs oxide on surface for the second time is to remove the InP and the GaAs sheet of oxide on surface in the step (c), dry up without high pure nitrogen and directly to put into reproducibility ammonia spirit (concentration is 25～28%) and soak, directly put into anti-oxidation methanol solution after the immersion;
(e) lamination carries out in methanol solution, with the burnishing surface of InP place down the GaAs burnishing surface directly over, with InP and GaAs limit on one side alignment and congruence be in the same place;
(f) lamination with step (e) moves in the square or rectangular open slot of anchor clamps, and groove is of a size of 25 * 25 * 15mm.Add certain pressure, pressure is 0.5～35Kg/cm
2, bonding temperature is 500～700 ℃; Whole bonding and annealing process nitrogen protection.Nitrogen flow rate is the 150-250 ml/min; The liter of 25-500 ℃ of temperature range gradually speed is 10-15 ℃/minute, and the heating rate of 500-700 ℃ of temperature range is 5-10 ℃/minute, and furnace temperature is risen to annealing temperature (between 500-700 ℃), keeps on 30-40 minute under annealing temperature.After annealing was finished, the rate of temperature fall of the temperature of annealing furnace in 700-450 ℃ of interval was 3-4 ℃/minute, and the rate of temperature fall in 450-300 ℃ of interval is 2-3 ℃/minute; Treat to close when furnace temperature is reduced to below 300 ℃ N
2, naturally cool to stove at last and be lower than 100 ℃ of taking-ups.
This shows InP-GaAs material Direct Bonding method provided by the invention, though technical process and bibliographical information are roughly the same, essence is different, and good effect also of the present invention is conspicuous:
(1) bonding temperature is controlled at 500-700 ℃ described low more than document 1, can not cause that III～V compounds of group decomposes;
(2) method of acting surface oxide skin(coating) is different with document (1), and adopts for two steps removed the method for oxide on surface;
(3) etch recipe of the deoxidation thing layer that uses of the present invention and bibliographical information is also different;
(4) be that invention is a Direct Bonding rather than to dry up the back with nitrogen superimposed in air in organic solvent, thereby anti-oxidation keep bonding face clean, is bonded to power near 100% thereby make
(5) but bonding of the present invention is once the bonding multi-disc, the InP-GaAs limit for the treatment of bonding as shown in Figure 1 with can stack after aliging in the limit, stack height needs only the height a little less than open slot, and the mode of exerting pressure is various, or bloom weight thing, or firm of screw or hydraulic means implement, and reads with pressure sensor or Pressure gauge; And applied pressure is at 0.5-35Kg/cm
2Scope is continuously adjustable.The bonding temperature height is then exerted pressure lower, and vice versa.
(6) optics and the electric property variation of Direct Bonding method provided by the invention whole material structure after the InP-GaAs interface of bonding process and introducing thus can't make bonding, after InP and the GaAs Direct Bonding, can carry out device technology processes such as mechanical lapping attenuate, polishing, chemical corrosion and reactive ion etching, this technology not only can have been utilized the advantage of InP sill but also can utilize the advantage of GaAs sill, and the development of III-V family semiconductor integrated opto-electronic and microelectronic component is had great importance.
Description of drawings
Fig. 1 InP-GaAs lamination and pressurization schematic diagram.
Embodiment
Further illustrate substantive distinguishing features of the present invention and marked improvement square below by specific embodiment.
Embodiment 1
InP and GaAs Direct Bonding processing step are:
1. InP and GaAs substrate being cleaved into the length of side is the 2.5cm square;
2. cleaning substrate: use isopropyl alcohol, acetone and absolute ethyl alcohol ultrasonic cleaning sample strip successively each 3 times, each 5 minutes, use rinsed with deionized water more than 3 minutes then;
3. go oxide on surface: InP at static H
2SO
4+ H
2O
2+ H
2Corroded for 10 seconds among the O (volume ratio is 3: 1: 1), GaAs is at static H
2SO
4+ H
2Corroded for 40 seconds among the O (volume ratio is 1: 20), InP and GaAs all need dry up with high pure nitrogen before the corrosion, etch the back and use rinsed with deionized water more than 5 minutes; Then, InP and GaAs sheet are dried up direct immersion HF+H without high pure nitrogen
2Soaked 30 seconds among the O (volume ratio is 1: 10), use deionized water rinsing again three times; Above corrosion process is all finished under room temperature (20～25 ℃);
4. remove for the second time oxide on surface: InP and GaAs substrate slice are dried up without high pure nitrogen directly put into reproducibility ammonia spirit (concentration is 28%) 3 minutes, directly put into anti-oxidation methanol solution afterwards.
5. lamination: soak more than three minutes in methanol solution, carefully clamp the InP substrate slice with tweezers, and careful upset places directly over the GaAs its face down, whole process all can not make epitaxial wafer expose methanol solution; Carefully regulate InP sheet position, be superimposed together (limit and limit angle are within ± 2 °) with making InP and GaAs edge-to-edge with tweezers;
6. load: clamp the InP and the GaAs epitaxial wafer back side simultaneously with tweezers, carefully put into the square slotting position of anchor clamps as shown in Figure 1, finely tune the slice, thin piece position once more, make slice, thin piece just in time be positioned at opening central authorities, and InP and GaAs sheet still the edge-to-edge be superimposed together; Totally 10 pairs together bonding carefully press bloom weight thing, and the screw pressue device is installed, careful hand-tight make-up screw, the pressurization size is 10Kg/cm
2, total pressure is read by pressure sensor or Pressure gauge.If the temperature of selected then bonding is lower, then the pressure that need add is suitably big; Bloom and chassis are moved, in order to avoid InP and GaAs sheet are extremely cracked because of discontinuity;
7. annealing: after installing the epitaxial wafer that needs bonding, immediately anchor clamps are put into annealing furnace, feed N
2Protective gas, N
2Flow velocity be 200ml/ minute; Heating rate with 10-11 ℃/minute (100-500 ℃) and 7-8 ℃/minute (500-700 ℃), furnace temperature is risen to annealing temperature (between 500-700 ℃), under annealing temperature, kept 35 minutes, close the stove power supply afterwards it is lowered the temperature naturally, employed stove rate of temperature fall is 3 ℃/minute (700-450 ℃) and 2 ℃/minute (450-300 ℃); Treat that furnace temperature is reduced to below 300 ℃ and close N
2, annealing finishes;
8. be cooled to below 100 ℃ with stove and take out sample.
Embodiment 2
Present embodiment InP and GaAs are cleaved into rectangle, and the length of side is respectively 1.5cm and 2.5cm, and limit and limit alignment and congruence angle are 1 °.Bonding temperature is 680 ℃, keeps 30 minutes applied pressures less, is 2Kg/cm
2, be 3.5 ℃/minute for 680-450 ℃ of temperature range detemperature rate, the rate of temperature fall in 450-300 ℃ of interval is 2 ℃/minute, all the other are with embodiment 1.
Claims (9)
1, the Direct Bonding method of a kind of InP and GaAs comprises cleaning surfaces, lamination and three technical processs of high annealing, it is characterized in that the processing step of concrete Direct Bonding is:
(a) InP and GaAs substrate are cleaved into square or rectangular;
(b) cleaning substrate is to use isopropyl alcohol, acetone and absolute ethyl alcohol ultrasonic cleaning successively, uses rinsed with deionized water then;
(c) remove InP and GaAs oxide on surface, InP is at static H
2SO
4+ H
2O
2+ H
2Corrode in the O solution, three's volume ratio is 3: 1: 1; GaAs is at static H
2SO
4+ H
2Corrode in the O solution, the volume ratio of the two is 1: 20; Etch the back and use rinsed with deionized water, then InP and GaAs sheet are dried up direct immersion HF+H without high pure nitrogen
2In the O solution, HF and H
2The volume ratio of O is 1: 10; Rinse well with deionized water again;
(d) removing for the second time InP and GaAs oxide on surface is InP and the GaAs sheet of removing oxide on surface in will step (c), dries up without high pure nitrogen and directly puts into the reproducibility ammonia spirit and soak, and directly puts into anti-oxidation methanol solution after the immersion;
(e) lamination carries out in methanol solution, with the burnishing surface of InP place down the GaAs burnishing surface directly over, InP is in the same place with GaAs limit and limit alignment and congruence;
(f) lamination layer with step (e) moves in the open slot of anchor clamps, but bonding multi-disc is once added certain pressure, and bonding temperature is 500～700 ℃; Whole bonding and annealing process nitrogen protection, annealing temperature are 500-700 ℃, keep under annealing temperature 30-40 minute, after annealing is finished, are cooled to below 300 ℃ by given pace and close N
2, treat that stove is cooled to and be lower than 100 ℃ of taking-ups.
2, by the Direct Bonding method of described InP of claim 1 and GaAs, it is characterized in that the degree of depth of every pair of InP-GaAs stack height of a bonding process a little less than open slot.
3, by the Direct Bonding method of described InP of claim 1 and GaAs, it is characterized in that InP and GaAs substrate are cleaved into square or rectangular, the length of side is between 0.5～2.5cm.
4, by the Direct Bonding method of described InP of claim 1 and GaAs, it is characterized in that InP is at H
2SO
4+ H
2O
2+ H
2Corroded in the O solution 5～15 seconds; GaAs is at H
2SO
4+ H
2Etching time is 30～60 seconds in the O solution, needs dry up with high pure nitrogen before corroding, and the corrosion back uses rinsed with deionized water more than 5 minutes, then at HF+H
2Soaked in the O solution 20～40 seconds; Use deionized water rinsing again 2～5 times.
5, by the Direct Bonding method of described InP of claim 1 and GaAs, it is characterized in that InP or the GaAs substrate slice in the step (d) soaked 2～5 minutes in reproducibility ammoniacal liquor, ammonia concn is 25-28%.
6, by the Direct Bonding method of claim 1 or 2 described InP and GaAs, when it is characterized in that InP and GaAs substrate edge opposite side stack in the step (e) align with the limit in the limit, and its angle is within ± 2 °.
7. by the Direct Bonding method of claim 1 or 2 described InP and GaAs, it is characterized in that described open slot is a square or rectangular.
8. by the Direct Bonding method of the described InP of claim 1 and GaAs, when it is characterized in that annealing nitrogen flow rate be the 150-250 person of outstanding talent rise/minute; After annealing was finished, the rate of temperature fall of the temperature of annealing furnace in 700-450 ℃ of interval was on 3-4 ℃/minute, and the rate of temperature fall in 450-300 ℃ of interval is 2-3 ℃/minute.
9. press the Direct Bonding method of described InP of claim 1 and GaAs, it is characterized in that InP and GaAs lamination bonding time institute's plus-pressure or bloom weight thing in the step (f), or firm of screw or hydraulic means implement, and reads with pressure sensor or Pressure gauge; And at 0.5-35kg/cm
2Continuously adjustable in the scope.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410052711XA CN100356507C (en) | 2004-07-09 | 2004-07-09 | Direct bonding method for indium phosphide and gallium arsenide materials |
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|---|---|---|---|
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| CN100356507C CN100356507C (en) | 2007-12-19 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1933096B (en) * | 2005-09-14 | 2010-04-21 | 中国科学院半导体研究所 | Low-temperature chip direct bonding method |
| MD176Z (en) * | 2009-04-15 | 2010-10-31 | Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы | Process for the manufacture of high-voltage diode |
| CN101667716B (en) * | 2008-09-03 | 2011-10-26 | 中国科学院半导体研究所 | Double-sided bonding long-wavelength vertical cavity surface emitting laser and manufacturing method thereof |
| CN102796526A (en) * | 2012-08-02 | 2012-11-28 | 中国电子科技集团公司第四十六研究所 | Etching solution and etching method for etching indium phosphide monocrystal wafer |
| CN104183667A (en) * | 2013-05-24 | 2014-12-03 | 上海空间电源研究所 | Method for reducing bonding multi-junction solar cell GaAs/InP interface electrical loss |
| CN107338481A (en) * | 2017-06-27 | 2017-11-10 | 台山市华兴光电科技有限公司 | A kind of cleaning method of indium phosphide polycrystal material |
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| DE102019003069B4 (en) | 2019-04-30 | 2023-06-01 | Azur Space Solar Power Gmbh | Stacked high-blocking III-V semiconductor power diodes |
| DE102019003068A1 (en) * | 2019-04-30 | 2020-11-05 | 3-5 Power Electronics GmbH | InGaAS stacked high-blocking semiconductor power diode |
Family Cites Families (3)
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|---|---|---|---|---|
| CN1028191C (en) * | 1992-11-10 | 1995-04-12 | 东南大学 | Silicon chip directive bonding method |
| JP2675519B2 (en) * | 1993-11-17 | 1997-11-12 | 株式会社日立製作所 | Semiconductor substrate, semiconductor device, and manufacturing method thereof |
| JP2002185080A (en) * | 2000-12-15 | 2002-06-28 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
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- 2004-07-09 CN CNB200410052711XA patent/CN100356507C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1933096B (en) * | 2005-09-14 | 2010-04-21 | 中国科学院半导体研究所 | Low-temperature chip direct bonding method |
| CN101667716B (en) * | 2008-09-03 | 2011-10-26 | 中国科学院半导体研究所 | Double-sided bonding long-wavelength vertical cavity surface emitting laser and manufacturing method thereof |
| MD176Z (en) * | 2009-04-15 | 2010-10-31 | Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы | Process for the manufacture of high-voltage diode |
| CN102796526A (en) * | 2012-08-02 | 2012-11-28 | 中国电子科技集团公司第四十六研究所 | Etching solution and etching method for etching indium phosphide monocrystal wafer |
| CN104183667A (en) * | 2013-05-24 | 2014-12-03 | 上海空间电源研究所 | Method for reducing bonding multi-junction solar cell GaAs/InP interface electrical loss |
| CN104183667B (en) * | 2013-05-24 | 2018-04-17 | 上海空间电源研究所 | The method for reducing bonding multijunction solar cell GaAs/InP interfaces electrical losses |
| CN107338481A (en) * | 2017-06-27 | 2017-11-10 | 台山市华兴光电科技有限公司 | A kind of cleaning method of indium phosphide polycrystal material |
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|---|---|
| CN100356507C (en) | 2007-12-19 |
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Granted publication date: 20071219 Termination date: 20100709 |