CN1571142A - 基于外延的CMOS或BiCMOS工艺中提供三阱的方法 - Google Patents

基于外延的CMOS或BiCMOS工艺中提供三阱的方法 Download PDF

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CN1571142A
CN1571142A CNA2004100430947A CN200410043094A CN1571142A CN 1571142 A CN1571142 A CN 1571142A CN A2004100430947 A CNA2004100430947 A CN A2004100430947A CN 200410043094 A CN200410043094 A CN 200410043094A CN 1571142 A CN1571142 A CN 1571142A
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CN1571142B (zh
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P·阿戈特松
K·安德松
H·诺尔斯特伦
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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Abstract

本发明涉及到在基于外延的CMOS或BiCMOS工艺中提供三阱的方法，其中，在外延淀积之前，注入三阱。

Description

基于外延的CMOS或BiCMOS工艺中提供三阱的方法
技术领域
本发明涉及到在基于外延的CMOS或BiCMOS工艺中提供三阱的方法。
背景技术
在主流CMOS或BiCMOS工艺中，可以在P/p型衬底中注入NMOS中的PWELL/pwell，因此，对在芯片上所有的NMOS晶体管来说，pwell的偏置是共同的。为了防止整体偏置，可以选择使用三阱(TRIPLE WELL/triple well)的方案。很早就知道了三阱的使用，并已很早公开了提供三阱的方法，例如参见美国专利NO.6.388.295和日本专利NO.11026601。
三阱的使用首次提供了在每个NMOS晶体管上分别偏置的可能，由此可以单独地调节阈值电压。对模拟RF来说并且对混合信号电路来说或许最理想的是，三阱的使用也隔离了NMOS晶体管并抑制了噪声耦合。通过使用三阱的概念能获得几个益处。在集成电路中，一组晶体管的整体偏置是有利的。
发明内容
本发明涉及提供例如三阱的深NWELL/nwell的新方法。使用三阱的传统工艺流程具有通过使用高能量注入制成进入硅的深掺杂注入磷。相反，本发明建议利用在沉积外延层之前掺杂注入砷。由于砷的扩散比磷慢并有更好的晶格匹配，所以砷更可取。所述砷被深注入硅内，以便将对晶体管参数的影响减少到最小。在NMOS晶体管外延淀积之后，随后的pwell注入的深度决定了三阱注入的深度。该方法优先用于浅沟槽隔离(STI)工艺。STI的深度一定不能到达已注入砷的三阱。这意味着必须引进一些额外的N型掺杂，以切断在STI下面的路径。这通过在外延淀积之前与三阱注入连续进行附加的N注入来实现。PMOS晶体管的标准nwell注入也可以用来切断这条路径。在STI刻蚀和填充后，进行该nwell注入。用N型掺杂到达STI下面的区域并与深nwell一起形成PMOS晶体管的良好隔离的方式选择能量。
在外延淀积之前引入所述深层N注入基本上构成了发明的第一个权利要求的实质内容。在这种应用中，砷的使用构成了发明的第二个权利要求的实质内容。
这种工艺顺序可以容易地增加到标准的CMOS/BiCMOS工艺流程。通过使用这个概念，可以在同一个岛中具有一组NMOS晶体管，并与它的周围隔离。本发明介绍了一组NMOS晶体管，其具有相同偏置应被标准的NWELL注入或外延淀积之前的额外N型注入所包围，这基本上构成了发明的第三个权利要求的实质内容。
在STI下面增加额外的硼掺杂基本上构成了本发明第四个权利要求的实质内容。根据类型或工艺，在STI下面的P型路径的电阻率可以是很高，这需要pwell接触之间短的距离。为了增加这个距离，用与深阱/DEEP NWELL注入相同的方式，在外延淀积之前引进额外的P型注入。该注入必需以下面的方式被优化：注入不穿透三阱/TRIPLE WFLL注入并建立到衬底的导电路径。设计NMOS晶体管的pwell使得它到达比STI深度更深的深度，并由此降低STI下面的电流路径的电阻。
附图说明
图1是P型衬底的剖视图。
图2是根据本发明具有已注入的三阱的P型衬底的剖视图。
图3是根据本发明具有已注入的三阱的P型衬底的剖视图，其中展示了n型掺杂剂的注入。
图4是根据本发明具有已注入的三阱的P型衬底的剖视图，其中示出了p型掺杂剂的注入。
图5是根据本发明具有已注入的三阱的P型衬底的剖视图，其中展示了已获得的不同岛之间的隔离。
图6是根据具有三个NMOS晶体管的本发明，具有已注入的三阱的P型衬底的剖视图。
优选实施方式
为了理解本发明，将描述特定的例子，省略了本领域技术人员熟知的具体细节。下面的描述是工艺步骤的顺序，并且可以作为单独的模块合到主流CMOS或BiCMOS工艺内。没有介绍这些工艺步骤之前或之后的流程。也假定在先前的步骤中已制作了对准标记，并且可以在描述的顺序中使用对准标记。
在图1中，展示了p型衬底1的截面图。依据电路的应用，选择衬底的掺杂水平。只要具有高欧姆，上述原则就不会受电阻率的选择的影响。
在该起始材料上，外延淀积之前进行一系列三次注入。应用第一掩模2以在优选的区域中获得三阱3。掩模2仅在这些区域的正上方的区域有开口。接着，使用该图案化的抗蚀剂2作为掩模，进行砷的离子注入4。以2×10exp13cmexp-2的建议的掺杂剂量、480keV的能量和0度的倾斜角进行该注入4，该注入4渗入到衬底深部。在图2中，展示了该注入步骤和已获得的三阱区3的步骤。
进行下一个掩模步骤5以掩蔽同一岛中将围绕器件或器件群的另外的n型注入6。必须以在已注入区中的STI 12a下没有剩余p型的方式进行注入。它也必须连接到三阱区，确保没有p型区域将此注入与三阱分离。在图3中，展示了该n型掺杂剂的注入。
最后的掺杂8目标是终止在STI 12b的下面，这将在后面的工艺流程中完成。将有单独的图案化抗蚀剂掩模9。选择该注入的能量和剂量，使其到达三阱3。它应当尽可能的高，但仍不切断三阱3。当确定剂量和能量时，甚至必须考虑可能对设计规则有影响的横向扩散。当制订设计规则时，注入应被优化以使STI下的电流路径的电阻率应当被最小化。在图4中，展示了该p型掺杂的注入。
本说明书以特定的顺序介绍了这三个注入。但可以进行注入顺序的任何排列，并且仍能获得想要的结构。
在这三个掩模注入后，将进行外延生长。对硅的掩模蚀刻将跟着进入外延层。用介质材料，例如高密度等离子体氧化物(HDP)，填充已获得的沟槽，接着，通过化学和/或机械抛光CMP平面化。这些方框(boxes)STI 12将在如在图5中所示的工艺中的器件之间提供隔离。到此为止，没有提及深度和厚度的绝对数字。原因是对于这些数字，本概念适用于很宽的范围。但需要下面的条件以实现概念。外延的厚度、STI的深度和所述三个注入的深度必须如下互相关联。STI不应到达三阱。P型不应当注入在将注入n型的区域中。环绕的n型必须到达三阱，并切断在注入区中STI下的所有p型。三阱必须足够的深，以对晶体管的特性没有任何较大的影响。
掩模步骤的数量是技术复杂度的象征。在该顺序中，基本工艺流程包括三个附加层。要减少到仅一个附加的掩模，可以用pwell注入代替8，并且可以使用nwell或掩埋的集电极代替6，这将降低工艺成本。
在已取得的该结构中，通过传统的主流CMOS或BiCMOS流程能制作传统的NMOS设计。在图6中，展示了三个NMOS晶体管的横截面图。在此视图中，看不到pwell6和三阱3的接线端。在图中能看到漏14、源15和栅13。如果单独地偏置单个器件，那么附加的p型注入是没有必要的。在这种情况下，周围的STI12a是与用来隔离器件的STI 12b相同的STI，这意味着附加的n型注入将在与用于隔离器件的STI相同的STI的下面。在这种情况下，当制造多于一个器件时，与该附加n型一样的岛将仅在周围的STI下面。p型将位于被周围的STI锁定的STI和n型注入之下。

Claims (5)

1.一种在基于外延的CMOS或BiCMOS工艺中提供三阱的方法，其特征在于：在外延淀积前，注入所述三阱。
2.根据权利要求1的方法，其特征在于，当注入所述三阱时，使用砷，其中发生慢扩散。
3.根据权利要求2的方法，其特征在于，在已获得的结构中，增加至少一个NMOS器件。
4.根据权利要求2或3的方法，其特征在于，在外延淀积之前，注入硼。
5.根据权利要求4的方法，其特征在于，在已获得的结构中，增加一个以上的NMOS器件。
CN2004100430947A 2003-03-28 2004-03-26 基于外延的CMOS或BiCMOS工艺中提供三阱的方法 Expired - Fee Related CN1571142B (zh)

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SE03009248 2003-03-28
SE0300924A SE0300924D0 (sv) 2003-03-28 2003-03-28 A method to provide a triple well in an epitaxially based CMOS or BiCMOS process
SE0300924-8 2003-03-28

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