CN1552105A - 具有深植入结的功率mosfet - Google Patents

具有深植入结的功率mosfet Download PDF

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CN1552105A
CN1552105A CNA028172809A CN02817280A CN1552105A CN 1552105 A CN1552105 A CN 1552105A CN A028172809 A CNA028172809 A CN A028172809A CN 02817280 A CN02817280 A CN 02817280A CN 1552105 A CN1552105 A CN 1552105A
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power semiconductor
conduction type
gate electrode
semiconductor arrangement
base region
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CN1333468C (zh
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K・斯普林
K·斯普林
J·曹
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Abstract

示出一种MOS栅极的半导体装置，其包括深植入结和厚氧化物间隔物置于共用导电区的实质部分上。

Description

具有深植入结的功率MOSFET
相关申请
本申请基于并要求2001年7月5日提交的美国临时申请No.60/303059标题为″Power MOSFET With Ultra-Deep Base and Reduced On Resistance″的权利。
发明领域
本发明涉及功率MOSFET和其制造过程，尤其涉及新颖的MOSFET，它具有提高的击穿电压，和对给定额定值产生减小的接通电阻和模具面积降低的漂移区中较高的掺杂浓度。
发明背景
功率MOSFET是公知的半导体装置。功率MOSFET的两个竞争的工作特性是击穿电压和Rdson(接通电阻)。功率MOSFET的另一个重要的工作特性是其开关频率。通常希望具有较高击穿电压、较低Rdson和较高开关频率能力的功率MOSFET。还希望具有前述特性，以及在单元装置中具有较高单元密度以降低装置尺寸的功率MOSFET。
图1示出已知的垂直导电的功率MOSFET的结构。图1所示的已知装置采用硅基片30，它具有其上表面上生长的结吸收外延层31。作为外延层31和基片30的相同导电率的多个源极区33设置在相反导电类型的基极区32中。可逆沟道32’设置在源极区33和共用导电区35之间。
薄栅极氧化物34置于可逆沟道32’和共用导电区35的上部上。导电多晶硅层36置于栅极氧化物层34上并通过低温氧化物层37绝缘。多晶硅层36用作栅电极结构，用于产生转换可逆沟道32’所需的电场，以便将源极区33电连接到共用导电区35。氧化物间隔物38还形成于多晶硅层36的侧壁上。氧化物间隔物38和低温氧化物层37使多晶硅层36和接触层39电绝缘，所述接触层39电连接到源极区33并用作其接触件。可以用铝或某些其它合适的金属形成接触层39。值得注意的是，图1所述的装置中，接触层39延伸通过源极区33中的沉降部分(depression)以便与基极区32接触，因此使源极区33和基极区32短路，由此防止装置主体中寄生双极晶体管的工作。在诸如图1所示的垂直导电MOSFET中，还金属处理基片30的下自由表面以用作装置的漏极接触件。
图1所示的装置是N沟道MOSFET。在该装置中，用诸如硼的P型掺杂物轻度掺杂基极区32，而用诸如磷的N型掺杂物高度掺杂源极区33；用诸如磷的N型掺杂物轻度掺杂外延层31(或漂移区)，而用诸如磷的N型掺杂物高度掺杂基片30。可以用图1所示的相同结构设计P沟道MOSFET，但在每个区域中使用与在图1所示相反的导电率。
在将足够强度的正电压施加到多晶硅层36上时，产生电场，该电场开始耗尽可逆沟道。在足够地耗尽该沟道时，可逆沟道被转换且N沟道形成于源极区33和共用导电区35之间。源极区33和装置下部的漏极之间的电压将引起它们两个之间流过的电流。
外延层31中轻度掺杂的区域常称作漂移区。在图1所示的常规MOSFET中，该区域被轻度掺杂以便提高装置的击穿电压。由于其被轻度掺杂，漂移区显著地影响装置的Rdson。因此，在常规MOSFET中，必须建立所需击穿电压和Rdson之间的平衡，其中通过改变漂移区中掺杂物浓度而获得的其中一个的改善会相反地影响另一个。
已知超结(superjunction)装置。这种装置包括通常在基极区下形成的高度掺杂的柱或支架。超结装置中的漂移区也被高度掺杂并具有与高度掺杂的支架或柱中的电荷相等的电荷。由于漂移区中掺杂物浓度的增加，超结装置的Rdson小于其它装置。但是，并不由于漂移区中掺杂物浓度的增加而损害超结装置的击穿电压，其中高度掺杂的柱或支架引起反向电压条件下漂移区的侧向耗尽由此改善装置中的击穿能力。
图2示出这种结构的图示，它常被称为超结结构。参考图2，在主体区域32下形成高度掺杂的支架或柱32”。利用超结的特性，必须在支架32”和围绕高度掺杂的支架32”的区域之间建立电荷平衡。因此，提高漂移区中的掺杂物浓度以与支架32”的掺杂物浓度匹配。漂移区中掺杂物浓度的增加降低了装置的Rdson。但是，如图2所示，掺杂物浓度的增加不会降低击穿电压，其中支架32”工作以耗尽支架纵向之间的漂移区(for the length of the of the pylons)，由此改善装置的击穿电压。结果，获得了具有较小Rdson和较高击穿电压的装置。
如上所述，为了在降低RDSON的同时保持击穿电压较高，在装置的漂移区中形成一种导电类型的深支架或柱32”。支架或柱32”的形成需要许多外延沉积，每个都伴随着扩散驱动。这种过程可能需要许多掩蔽方法，这进一步使超结装置的制造变得复杂。因此，常规已知超结装置的制造是费时又费钱的过程。
MOSFET的频率响应由其输入电容的充电和放电限制。MOSFET的输入电容是栅极到漏极电容(Cgd)和栅极到源极电容(Cgs)的和。当Cgd和Cgs变小时，MOSFET可以在较高的频率范围中工作。因此，需要具有较低的输入电容以便改善MOSFET的频率响应。
发明概述
根据本发明，深植入结(junction)设置在漂移区中的基极区下，其本身可以是被深度掺杂的并可以具有和深植入结基本相等的电荷。通过在深度掺杂的漂移区中设置深植入结，可以降低漂移区的电阻率而不牺牲装置的击穿电压。
根据本发明的一个方面，在形成MOS栅极沟道区之前，由5E11到1E14原子/cm2和150KeV到4MeV能量的一个或多个早先的深植入体(例如，用于P沟道装置的硼)形成深植入结。该过程排除了对多外延沉积的需要以形成多个支架或柱，如现有技术装置所需的。更重要的，可以在同一掩蔽过程期间实现植入体，从而降低了所需掩蔽的次数。
根据本发明的另一个方面，根据本发明的装置包括设置在漂移区(或“共用导电区”)上的急剧加厚的氧化物，这减小了其相对区域的实质部分上多晶硅栅极和漏极表面之间的间距，因此基本降低了栅极到漏极之间的电容。同样基本降低了QGD/QGS的比率，这导致极佳的Cdv/dt免疫性。
附图概述
图1示出根据现有技术的小部分垂直导电MOSFET的剖视图。
图2示出根据现有技术的MOSFET装置。
图3示出根据本发明的MOSFET。
图4-13示出根据本发明制造半导体装置中采用的各种步骤。
图14A-14C示出根据本发明第二实施例的用于制造另一种装置的步骤。
图15A-15D示出根据本发明制造装置的可选步骤。
图16示出根据本发明的第二实施例的装置的剖视图。
图17示出根据本发明的第三实施例的装置的剖视图。
图18示出根据本发明的第四实施例的装置的剖视图。
具体实施方式
图3示出根据本发明的MOSFET的剖视图。参考图3，其中相同的标号表示上述相同的零件，根据本发明的MOSFET包括高度掺杂的半导体基片30，它可以是单晶硅或某些其它半导体材料；轻度掺杂的外延层31；高度掺杂的源极区33，其电导率等于相对导电类型的各轻度掺杂的主体区32种形成的外延层31的电导率。图3所示的MOSFET还包括可逆沟道32’上形成的栅极绝缘层34。但是，与图1所示的现有技术装置不同，栅极绝缘层34不在位于主体区域32之间的共用导电区35的整个区域上延伸。相反，栅极绝缘层只在部分共用导电区35上延伸。不由绝缘层34覆盖的共用导电区35的其余部分由绝缘间隔物50覆盖。
如图3所示，通常由单晶硅形成的栅电极51形成于栅极绝缘层34上。根据本发明的一个方面，绝缘间隔物50置于栅电极51之间。绝缘间隔物50接触外延层31的上表面并覆盖每个共用导电区35的实质部分。可以提供由铝形成的源极接触件39来接触源极区33和主体区32。绝缘侧壁38和绝缘上层37插入栅电极51和源极接触件39之间以使两者彼此绝缘。可选地，硅化物壁80插入侧壁38和栅电极51之间。
绝缘间隔物50急剧加厚并优选在共用导电区35的大体部分宽度上延伸。例如，绝缘间隔物50可以具有约0.5μ的高度，这显著地大于栅极氧化物34的厚度(小于1000埃)。同样，绝缘间隔物50的宽度可以是至少超过共用导电区35的宽度的一半。
从图3可以看出，绝缘间隔物50减少了共用导电区35的表面上的栅电极51的面积。这导致减小的栅极到漏极电容。由于装置的输入电容大大改善，从而改善了其频率响应。
再参考图3，根据本发明的MOSFET包括外延层31的主体中形成的深植入结92。根据本发明的一个方面，深植入结92可以是主体区32的至少两倍深度且较佳地几乎与外延层31的整个深度一样深。可以增加深植入结92中的掺杂浓度。深植入结92中的掺杂浓度增加允许共用导电区35的掺杂浓度的增加，这改善Rdson而不牺牲击穿电压。已发现根据本发明的装置中每个面积的电阻(薄层电阻)降低了常规装置的一半以上，从而允许装置尺寸的减小。
图3所示的装置是N沟道装置并因此包括高度掺杂的N型源极区33，轻度掺杂的P型主体区32，N型外延层和N型基片。图3所示装置的深植入结92可以是高度掺杂的P型区。通过倒转这里讨论的N沟道装置的每个区的极性，根据本发明的P沟道MOSFET也是可以的。
可以根据以下描述的过程制造根据本发明的MOSFET。
首先，提供掺杂的基片30，它可以是高度掺杂的N型单晶硅片，具有设置在其上表面上的硅的掺杂的外延层。现在参考图4，可以是绝缘氧化物的厚绝缘层被沉积或生长于外延层31的上面的表面上。例如，厚绝缘层可以是0.5微米厚。随后，将厚绝缘层形成图案和蚀刻，剩下绝缘间隔物50。
随后，在绝缘间隔物50之间暴露的外延层31的表面上生长薄栅极氧化物层34。
由此，如图5所示，诸如多晶硅的栅极材料36的层沉积于图4所示的结构的上表面上。随后，掺杂该栅极材料以使其导电。例如，如果将多晶硅用作栅极材料，则用N型掺杂物进行掺杂。随后扩散驱动可以接在掺杂过程之后，以活化掺杂物。
在扩散驱动之后，上表面被去玻璃(deglass)且，如图6所示，将多晶硅形成图案并蚀刻以便形成在绝缘间隔物50的侧部上分开的栅电极51。
随后，用双扩散的常规已知技术植入主体区32和源极区33以提供浅基极区32和自对准的源极区33，其中使用栅电极51作为掩膜。随后，扩散主体区32和源极区33。在扩散驱动期间，薄氧化物层60(源极氧化物)在多晶硅间隔物51上生长。随后，根据本发明的另一个方面，将P型掺杂物植入外延层以形成深植入结92。为了形成深植入结92，需要诸如硼的P型掺杂物的一个或多个植入体形成深植入结92。可以以150keV到4MeV之间的能量以约5E11到1E14的剂量实现每个植入体。结果，在主体区32下形成深植入结92。值得注意的是，无需多掩蔽，其中可以实现植入体而不重新掩蔽，从而使得该过程更加有效。
接着参考图7，可以是氮化物的薄氧化阻塞层70沉积于氧化物层60顶部或上部。随后，源极区33的中间部分上的间隙由诸如光阻材料75(图8)的蚀刻防护剂填充且上面的表面接收短暂的蚀刻以除去过剩的光阻材料。
由此，如图9所示，氮化物70暴露的上层被蚀刻并除去了光阻材料75。随后，可以是氧化物的绝缘层37在栅电极51的顶部生长。随后如图10所示除去剩余的氮化物薄膜70(等)。
作为降低栅电极的电阻RG的一个选择，如图11所示，多晶硅壁80可以形成于栅电极51的侧部上。在该过程中，相邻栅电极51之间的间隙部分由诸如光阻材料的蚀刻防护剂填充以便覆盖水平氧化物表面，但栅电极51的多数垂直侧壁不受保护。随后，进行短暂的蚀刻以除去栅电极51的侧壁上的氧化物60并剥去光阻材料。例如WSi等的层80随后形成于栅电极51裸露的侧壁上。
由此，实施自对准接触过程，其中共形氧化物层沉积于模具表面顶并由平面氧化物深蚀刻(etch back)步骤形成图案和蚀刻以在图12所示的位置处留下绝缘侧壁38。随后，进行硅沟蚀刻以形成沟道40。
随后使装置上表面形成图案和蚀刻以便形成多栅极(polygate)接触并再次除去光阻材料。随后，进行短暂的氧化物蚀刻且诸如铝层的金属接触层39沉积于图13所示的晶片的顶部。随后，如所需要地使该接触件适当成形。
图14A到14C示出修改过的处理流程，其中通过用诸如SiN3的氧化阻塞层(图14B)保护多晶硅“凹部”82来形成栅电极51，随后蚀刻多晶硅并氧化，由此去掉蚀刻的多晶硅。图14A示出形成外延层31、绝缘间隔物50和多晶硅层36之后的硅基片30。(参见图5)。参考图14B，随后形成氮化物层90等。用诸如光阻材料的防护剂填充间隙并蚀刻暴露的氮化物以及剥去保护层(resist)。暴露的多晶硅台面(mesa)随后被蚀刻成绝缘间隔物50的水平且多氧化物37在多晶硅层51的被蚀刻表面顶生长。随后，剥去氮化物90和蚀刻多晶硅以及如图6-13所示地完成过程。图16中示出根据第二实施例的装置，它是根据图14A-14C所示的修改后的过程制造的。
图15A到15D示出进一步修改的过程，其中如图15A所示地将开始的厚氧化物层50初始成形以形成双多晶硅栅极51和单元。随后生长栅极氧化物34并形成多晶硅层36来填充氧化物间隔物50之间的间隙，如图15B所示。随后，进行平面深蚀刻或CMP(化学机械抛光)步骤以使上面的表面平坦，如图16C所示。
随后进行不十分关键的对准步骤以保护共用导电区35上的厚氧化物50并蚀刻氧化物层50的较宽部分，如图16D所示。随后，继续如图6到13所示的过程。
本发明的其它实施例也是可以的。例如，图17示出根据本发明第三实施例的装置，它包括氧化物间隔物50上延伸的多晶硅栅电极36。同样，图18示出第四实施例，其中修改了第三实施例从而包括位于氧化物间隔物51的各垂直侧处的侧壁间隔物51。
虽然关于其特殊实施例描述了本发明，但对于本技术领域内熟练的技术人员来说许多其它变化和修改以及其它使用是显而易见的。所以，较佳地，本发明不受这里所特定揭示的内容所限制。

Claims (14)

1.一种功率半导体装置，其特征在于，包括：
第一导电类型的基片；
第一导电类型的外延层，形成于所述基片的表面上；
第二导电类型的多个轻度掺杂的基极区，在所述外延层中形成到第一预定深度，所述基极区彼此隔开；
共用导电区，设置在所述基极区之间；
第一导电类型的多个高度掺杂的源极区，形成在所述轻度掺杂的基极区内；
可逆沟道区，设置在所述源极区和所述共用导电区之间；
所述第二导电类型的深植入结，形成于所述基极区下所述外延层中，在所述第一预定深度到第二预定深度之间延伸；以及
栅电极，形成在所述可逆沟道之上，所述栅电极通过绝缘层而与所述可逆沟道绝缘。
2.如权利要求1所述的功率装置，其特征在于，还包括：厚绝缘间隔物，置于至少部分所述共用导电区之上。
3.如权利要求2所述的功率半导体装置，其特征在于，所述栅电极设置于所述厚绝缘间隔物的侧部上。
4.如权利要求1所述的功率半导体装置，其特征在于，还包括与所述源极区电连接的接触层。
5.如权利要求4所述的功率半导体装置，其特征在于，所述接触层与所述源极区和所述基极区电连接。
6.如权利要求1所述的功率半导体装置，其特征在于，所述栅电极包括多晶硅。
7.如权利要求1所述的功率半导体装置，其特征在于，一绝缘结构形成于所述栅电极上。
8.如权利要求1所述的功率半导体装置，其特征在于，还包括绝缘间隔物，它形成在所述栅电极的侧部上。
9.如权利要求8所述的功率半导体装置，其特征在于，还包括多晶硅层，它置于所述绝缘间隔物和所述栅电极之间。
10.如权利要求1所述的功率半导体装置，其特征在于，还包括绝缘层，形成于所述栅电极上。
11.如权利要求1所述的功率半导体装置，其特征在于，所述第二预定深度至少是所述第一预定深度的两倍。
12.如权利要求1所述的功率半导体装置，其特征在于，所述第二预定深度约是所述外延层的厚度。
13.一种用于制造MOSFET装置的过程，其特征在于，包括：
提供第一导电类型的基片，它具有相同导电类型的外延层形成于其上表面上；
在所述外延层中形成第二导电类型的基极区；
在所述基极区中形成所述第一导电类型的源极区；
在所述基极区下通过多植入所述第二导电类型的掺杂物形成所述第二导电类型的深层结。
14.如权利要求13所述的过程，其特征在于，所述深层结与所述外延层一样厚或是所述基极区厚度的至少两倍。
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AU2002318191A1 (en) 2003-01-21
EP1417721A2 (en) 2004-05-12
WO2003005414A3 (en) 2003-05-01
KR100566599B1 (ko) 2006-03-31
US6846706B2 (en) 2005-01-25
JP2004538626A (ja) 2004-12-24
US20030020115A1 (en) 2003-01-30
EP1417721A4 (en) 2008-04-09
JP4234586B2 (ja) 2009-03-04
CN1333468C (zh) 2007-08-22
US6639276B2 (en) 2003-10-28

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