CN1549340A - 设有触接垫的半导体装置 - Google Patents

设有触接垫的半导体装置 Download PDF

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CN1549340A
CN1549340A CNA031254950A CN03125495A CN1549340A CN 1549340 A CN1549340 A CN 1549340A CN A031254950 A CNA031254950 A CN A031254950A CN 03125495 A CN03125495 A CN 03125495A CN 1549340 A CN1549340 A CN 1549340A
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contacting pad
electric conductor
semiconductor device
pad
probe
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木村直树
司
杉原启司
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Co Rong Industries Ltd
Renesas Technology Corp
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Co Rong Industries Ltd
Renesas Technology Corp
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Abstract

在本发明的设有触接垫的半导体装置中，在触接垫(1)的表面上配置有第一导电体(1a)和第二导电体(1b)，第一导电体(1a)具有比第二导电体1b高的硬度，同时具有高于探针(11)的硬度。第一导电体(1a)被配置在触接垫1的表面上并在滑过触接垫时，至少有一次触碰第一导电体(1a)。因而，获得不需要对探针加以清理、研磨的设有触接垫的半导体装置。

Description

设有触接垫的半导体装置
技术领域
本发明涉及设有触接垫(pad)的半导体装置，具体涉及设有在半导体元件的电学特性检查或测量时用于使端子触接的触接垫的半导体装置。
背景技术
当在晶片状态下检查半导体元件的电学特性时，使用配置多个探针的探针插件。作为这种探针插件，例如有在特开平1-128535号公报上公开的一例。
在电学特性性检查时，通过把探针插件的探针压接到所述触接垫上来将半导体元件与测试仪导通。探针不与触接垫的表面垂直，而是以某个角度相触接。因此，在探针与触接垫触接之后，通过使晶片再次向探针插件一侧移动，使探针的尖端滑过触接垫的表面。然后，在适当的地方停止晶片的移动，探针也就停止在晶片表面上的滑动。
由于这个触接垫通常以铝作为主要成分，在触接垫的表面存在铝的氧化物。探针通常是由比铝硬的钨构成。因此，把探针压接在触接垫上时，由于探针的尖端滑过触接垫的表面，就削刮触接垫表面的铝氧化物。因此，形成了探针尖端与内部没有氧化的铝的接触，构成了探针与触接垫以低电阻导通。
然而，由于探针的尖端削刮触接垫表面的铝氧化物，被削掉的铝、铝氧化物等的触接垫碎屑附着在探针上。附着在这个探针尖端上的触接垫碎屑在电学特性检查、测量时，构成了电阻，给检查、测量带来不良影响。在晶片批量生产测试时，在晶片更换和批变更时，要定期进行探针的清理或研磨，因此，存在着增加晶片测试处理时间、由研磨引起探针尖端的磨损、针尖清洗时的损坏等问题。
发明内容
本发明是为解决上述诸问题而产生的发明，提供了有不需要探针清理、研磨的触接垫的半导体装置。
本发明的设有触接垫的半导体装置，是设有在半导体元件的电学特性检查或测量时使端子触接的触接垫的半导体装置。在触接垫的表面配有第一导电体和第二导电体。第一导电体具有比第二导电体更高的硬度，同时具有高于端子的硬度。在触接垫上配置第一导电体的原则是，在端子触接到触接垫的表面并滑过触接垫表面时至少有一次触碰第一导电体。
依据本发明的设有触接垫的半导体装置，不需要定期地进行晶片更换或批变更时的清理与研磨，以清除由于触碰第一导电体而附着在端子尖端上的触接垫碎屑。并且，能够削减清理、研磨所需花费的晶片测试的处理时间，防止因研磨而使端子的尖端磨损所造成的端子损坏。
附图说明
[图1]是概略表示在本发明的实施例1中设有触接垫的半导体装置的结构的剖面图。
[图2]是概略表示在本发明的实施例1中设有触接垫的半导体装置的结构的平面图。
[图3]是表示在本发明的实施例1中设有触接垫的半导体装置上，探针接触在触接垫上的情况的第一剖面图。
[图4]是表示在本发明的实施例1中设有触接垫的半导体装置上，探针接触在电触及接片上的情况的第二剖面图。
[图5]是概略表示在本发明的实施例2中设有触接垫的半导体装置的结构的剖面图。
[图6]是概略表示本发明的实施例3中有电触及接片的半导体装置的结构的平面图。
[图7]是概略表示在本发明的实施例4中设有触接垫的半导体装置的结构的平面图。
[图8]是概略表示在本发明的实施例5中设有触接垫的半导体装置的结构的剖面图。
具体实施方式
下面就本发明的实施例按图加以说明。
(实施例1)
参照图1和图2，本实施例的半导体装置(例如半导体晶片)10设有触接垫1、衬底2、绝缘层3和玻璃敷层4。
触接垫1与形成在半导体晶片10内的半导体元件电连接，它被配置在衬底层2上。衬底层2由例如硅氮化膜、硅氧化膜等的绝缘材料构成。另外，在触接垫1的周围形成绝缘层3。玻璃敷层4由绝缘性的材料构成，形成在半导体晶片的表面上。在这个玻璃敷层上形成开口4a，从该开口4a露出触接垫1的一部分表面。
触接垫是在半导体元件的电学特性检查或测量时压接探针(端子)11的部分。在该触接垫1的表面设有第一导电体1a和第二导电体1b。第一导电体1a具有比第二导电体1b高的硬度，同时也具有高于探针11的硬度。
第一导电体1a由例如钨(W)、钨合金、钛(Ti)合金、铼(Re)、镍(Ni)及镍合金的任意一种或它们的任意组合的材料构成，可以适当选择这些材质。再有，该第一导电体1a最好用与探针11相同的材料来构成。另外，第二导电体1b由铝(Al)等的含铝的材质构成。
第一导电体1a配置在触接垫1的表面上，使探针11在触接到触接垫1的表面上并滑过触接垫1的表面时，至少有一次触碰第一导电体1a。在本实施例中，触接垫1以第二导电体1b为主体构成，在第二导电体1b的表面上阵列状配置第一导电体1a。
该第一导电体1a埋入在设置于第二导电体1b的表面上的孔中，第一导电体1a的表面与第二导电体1b的表面的高度大致相同。另外，在触接垫1表面上露出的第一导电体1a的各个尺寸与探针11的尖端直径相比充分小。
再有，在本说明书中的所谓阵列状，指的是第一导电体1a在触接垫1的表面上的行列状整齐排列。
下面就探针接触到触接垫上的情况进行说明。
参看图3，为了使探针11与触接垫1导通，沿垂直线1c(与半导体晶10的主面垂直的假想线)向图中的上方向移动半导体晶片10。这样一来，探针11与触接垫在A点作最初接触。之后，通常为了消除探针11与触接垫1之间的接触不良，再次沿垂直线向图中的上方向移动半导体晶片10。
探针11有足够的长度，且与触接垫的表面形成角度(相对于垂直线1c形成的角度θ)来接触。因此，由于半导体晶片10的移动，探针一边弯曲，一边滑过触接垫1的表面至图4的B点。这时，探针11一边削刮第二导电体1b表面的例如铝氧化物，一边滑动行走，在探针11的尖端上附着有铝氧化物等的触接垫碎屑。但是，第一导电体1a被配置成使探针11在滑过触接垫表面时至少有一次触碰第一导电体1a，且第一导电体1a具有高于或等于探针11的硬度。于是，由于接触第一导电体1a，除去了附着在探针11尖端上的触接垫碎屑。因而，探针11与触接垫1以低电阻接触，构成导通状态。
另外，探针11在触接垫1表面的滑行量可用倾斜角度θ、探针11的长度来调整，而通常是30～50μm。这种情况下，第一导电体1a间的间隔W可以在例如20微米以下。
依据本实施例，由于探针11接触第一导电体1a，除去了附着在探针11的尖端上的触接垫碎屑，因而在更换晶片时和批次变更时，不需要定期进行探针11的清理、研磨。另外，可以减少清理、研磨花费的晶片测试处理时间，可以防止由研磨引起探针11的尖端的磨损和由研磨作业引起探针11的损坏。
(实施例2)
参照图5，在本实施例中的半导体装置的结构与上述实施例1的结构的不同点是：第一导电体1a一直延伸到触接垫1的下底面。
除此以外的结构，与上述实施例1的结构大致相同，因此给相同的构成部件附加相同的符号，将其说明省略。
在本实施例中，可以得到与实施例1相同的效果。
(实施例3)
参照图6，在本实施例中的半导体装置的结构与上述实施例1结构的不同点是：第一导电体1a被槽状地配置在触接垫1的表面。
再者，本说明书中的所谓槽状，指的是第一导电体1a在触接垫1的表面上以细长的长方形状排列。这里，第一导电体1a的宽度L在探险针11的滑行量的1/2以下。
除此以外的结构与上述的实施例1的结构大致相同，因此给相同的构成部件附加相同的符号，将其说明省略。
在本实施例中也可以得到与实施例1相同的效果。
(实施例4)
参照图7，在本实施例中的半导体装置的结构与上述实施例1中的结构的不同之点是：第一导电体1a随机分散配置在触接垫1的表面的全面积上。
除此以外的结构与上述的实施例1的结构大致相同，因此给相同的构成部件附加相同的符号，将其说明省略。
在本实施例中，可以得到与实施例1相同的效果。
(实施例5)
参照图8，本实施例中的半导体装置的结构与上述实施例1中的结构的不同点是：触接垫1是以第一导电体1a为主体结构的，且在第一导电体1a的表面上配置第二导电体1b。
在这种结构中，也是把第一导电体1a配置在触接垫1的表面上，使探针11触接在触接垫1的表面上并在滑过触接垫1的表面时，至少有一次触碰第一导电体1a。第二导电体1b也可以用上述的阵列状、槽状或随机分散来加以配置。
除此以外的结构与上述的实施例1的结构大致相同，因此给相同的构成部件附加相同的符号，将其说明省略。
在本实施例中，可以得到与实施例1相同的效果。
这里公开的实施例的全部内容均为举例说明。不应把这些内容视作限制范围。本发明的范围包含上述说明没有提到的、权利要求书所规定的内容，并涉及与权利要求书均等的意义与范围内的所有变更。

Claims (6)

1.一种设有触接垫(1)的半导体装置，该触接垫用以在半导体元件的电学特性检查或测定时让端子(11)触接；其特征在于：
在所述触接垫(1)的表面上配置有第一导电体(1a)和第二导电体(1b)；
所述第一导电体(1a)具有比第二导电体(1b)高的硬度，同时具有高于所述端子(11)的硬度；
所在述第一导电体(1a)配置在所述触接垫(1)的表面，使所述端子(11)在触接所述触接垫(1)的表面并滑过所述触接垫(1)表面时，至少有一次触碰所述第一导电体(1a)。
2.如权利要求1所述的设有触接垫的半导体装置，其特征在于：所述第一导电体(1a)在所述触接垫(1)的表面上阵列状配置。
3.如权利要求1所述的设有触接垫的半导体装置，其特征在于：所述第一导电体(1a)在所述触接垫(1)的表面上槽状地配置。
4.如权利要求1所述的设有触接垫的半导体装置，其特征在于：所述第一导电体(1a)在所述触接垫(1)的表面上随机分散地配置。
5.如权利要求1所述的有电触接垫的半导体装置，其特征在于：所述触接垫(1)将所述第一导电体(1a)作为主体来构成，在所述第一导电体(1a)的表面配置所述第二导电体(1b)。
6.如权利要求1所述的有设有触接垫的半导体装置，其特征在于：所述第一导电体(1a)由含有从钨、钨合金、钛合金、铼、镍与镍合金构成的组中选出的至少一种成分的材料构成，所述第二导电体(1b)由含铝的材料构成。
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* Cited by examiner, † Cited by third party
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CN103779301A (zh) * 2012-10-09 2014-05-07 英飞凌科技股份有限公司 电接触垫

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US7759776B2 (en) * 2006-03-28 2010-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Space transformer having multi-layer pad structures
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EP3302703B1 (en) * 2015-06-01 2021-08-25 Xeno Biosciences Inc. Compositions for use in modulating the gut microbiota and managing weight
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