CN1531057A - Method for producing shallow ridges separating structure (STI) - Google Patents
Method for producing shallow ridges separating structure (STI) Download PDFInfo
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- CN1531057A CN1531057A CNA031194370A CN03119437A CN1531057A CN 1531057 A CN1531057 A CN 1531057A CN A031194370 A CNA031194370 A CN A031194370A CN 03119437 A CN03119437 A CN 03119437A CN 1531057 A CN1531057 A CN 1531057A
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Abstract
The present invention relates to a manufacturing method of the shallow trough isolation structure on a semiconductor substrate which has an excellent trough-filling ability. The method comprises the following steps: forming a trough on a semiconductor substrate and forming a lining silicon oxide layer and a lining silicon nitride layer sequentially on the bottom and the side wall of the trough first; then depositing conformably a partial high density paste oxide (HDP oxide) in the trough; next forming conformably a polysilicon layer on the surface of the semiconductor substrate and thermally processing the semiconductor substrate to oxidize the polysilicon layer; and then flatting the surface of the semiconductor substrate to form the shallow trough isolation ( STI ) structure. The isolation structure having the excellent trough-filling ability so as to have no cavity therein can be formed in the trough by means of the high density paste oxide and the oxidized polysilicon layer.
Description
Technical field
The invention relates to the manufacturing of semiconductor subassembly, be particularly to a kind of manufacturing fleet plough groove isolation structure (shallow trench isolation, method STI).
Background technology
The fast development of integrated circuit manufacture process makes semiconductor product productive setization and microminiaturization day by day.And along with the productive setization of product, the isolation structure size of the size of semiconductor subassembly and isolation of semiconductor assembly is reduction thereupon also.Therefore, in manufacture of semiconductor, it is then difficult more to form the good isolation structure.Known a kind of method that forms isolation structure is to form field oxide (LOCOS) by selective oxidation, yet this kind mode is for the high semiconductor device of integration and be not suitable for, and is easy to generate the problem (bird ' s beak encroachment) that beak corrodes.Therefore, (shallow trench isolation, STI) processing procedure becomes main flow, is specially adapted to time following integrated circuit manufacture process of micron with shallow trench isolation structure at present.
Referring to Fig. 3, known shallow trench isolation structure processing procedure generally comprises the following step.At first, utilize selective etch in semiconductor substrate 300, to form shallow trench 304.Then, deposition one separator on this semiconductor-based basal surface, and fill up this groove.Generally speaking, mostly by chemical vapour deposition technique (chemical vapor deposition, CVD) deposition of silica forms separator 310, for example by atmospheric chemical vapor deposition (atmospheric pressure chemical vapordeposition, APCVD), medium-sized air pressure chemical vapour deposition technique (sub-atmosphericpressure chemical vapor deposition, SACVD) or the high density plasma enhanced chemical vapor deposition method (high density plasma CVD HDPCVD) carries out the deposition of silicon dioxide.At last, (CMP) carries out the planarization of semiconductor-based basal surface by cmp, and the separator that fills up in the groove then forms fleet plough groove isolation structure (STI).
Yet because that semiconductor device gets is complicated day by day, and the semiconductor subassembly volume dwindles day by day, so the width of fleet plough groove isolation structure also is reduced to 0.11 μ m or following, and the depth-to-width ratio of fleet plough groove isolation structure is usually more than 3.Along with the depth-to-width ratio of shallow trench isolation structure increases, fill out the preferable HDPCVD of ditch ability even adopt, still easily in filling out the ditch process, form slit or hole 311, as shown in Figure 3.These slits or hole in the time of may causing follow-up formation electric conducting material, cause the electrical problem of inter-module, reduce the durability of semiconductor product simultaneously.
Summary of the invention
One object of the present invention is to address the above problem, and the method for a manufacturing fleet plough groove isolation structure is provided, and improves it and fills out the ditch ability.
For achieving the above object, the invention provides a kind of method of making fleet plough groove isolation structure, comprise the following step.On the semiconductor-based end, form earlier a groove, then formation liner oxide layer on the bottom of groove and sidewall.Then in this groove, insert the oxide skin(coating) of part with high density plasma enhanced chemical vapor deposition method (HDPCVD).Follow formation one polysilicon layer of compliance on this oxide skin(coating), and the whole semiconductor-based end is heat-treated with this polysilicon layer of oxidation.At last, semiconductor-based basal surface is carried out planarisation step, to form fleet plough groove isolation structure.
According to said method, polysilicon layer forms the good oxide skin(coating) of insulation after heat treatment, and the generation of no slot or hole in the fleet plough groove isolation structure.And prevented effectively that at the high density plasma oxide layer under the polysilicon layer (HDP oxide) sidewall of groove and bottom are subjected to oxidation in heat treatment, therefore avoid the possible leakage current of semiconductor subassembly.In preferred embodiment, before the deposition high density plasma oxide, form a liner nitride layer on the liner oxide in this groove earlier, be not subjected to the destruction of subsequent heat treatment to guarantee the semiconductor-based end.
Description of drawings
Figure 1A to Fig. 1 F is depicted as according in one embodiment of the invention, forms the side flow chart of a shallow trench isolation structure;
During Fig. 2 A to Fig. 2 G is depicted as according to another embodiment of the present invention, form the side flow chart of a shallow trench isolation structure;
Figure 3 shows that the known a kind of shallow trench isolation structure end view that behind high density plasma enhanced chemical vapor deposition, forms with slit.
The figure number explanation
100: semiconductor silicon substrate 101: the pad oxide skin(coating)
102: silicon nitride layer 104: groove
106 liner oxide layers 110: oxide skin(coating)
112: polysilicon layer 112 ': the oxidation polysilicon layer
200: semiconductor silicon substrate 201: the pad oxide skin(coating)
202: nitride layer 204: groove
206: liner oxide layer 208: the liner nitride layer
210: oxide skin(coating) 212: polysilicon layer
212 ': oxidation polysilicon layer 214: oxide skin(coating)
300: the semiconductor-based end 301: the pad oxide skin(coating)
302: silicon nitride layer 304: groove
310:HDP oxide 311: slit
Embodiment
Embodiment one
Figure 1A to Fig. 1 G is depicted as according in one embodiment of the invention, makes the flow process end view of a fleet plough groove isolation structure.
Shown in Figure 1A, at first on the semiconductor-based end 100, form a pad oxide skin(coating) (pad oxide) 101 by a thermal oxidation processing procedure.Then on this pad oxide skin(coating) 101, form mononitride layer (nitride) 102 with low-pressure chemical vapor deposition (LPCVD).Then formation and little shadow define a photoresist layer (not shown) on nitride layer 102, to form the channel patterns that follow-up desire forms.Then the channel patterns according to photoresist layer is that curtain cover nitride etching layer 102 is to form channel patterns, then continue as hard mask layer (hard mask) with this nitride layer 102, (reactive ion etching, RIE) the etching pad oxide 101 and the semiconductor-based end 100, are to form groove 104 with the active-ion-etch method.
Then, a thermal oxidation processing procedure is carried out at the semiconductor-based end 100, with oxidation formation liner oxide layer (SiO on the bottom of groove 104 and sidewall referring to Figure 1B
2) 106.In one embodiment, the thermal oxidation processing procedure can be under 800 to 850 ℃, contains the wet type thermal oxidation processing procedure that carries out in the environment of aerobic hydrogen mixed gas.Perhaps, in another embodiment, the thermal oxidation processing procedure can be in oxygen-containing gas, carries out the dry type oxidation 2 hours under in 900 to 950 ℃.In above-mentioned thermal oxidation processing procedure, the inner wall oxide of groove 104 is the liner oxide layer 106 about thickness 100 to 200 dusts ().
After forming liner oxide layer 106 on the inwall of groove 104, then with high density plasma enhanced chemical vapor deposition method (high density plasma chemical vapor deposition, HDPCVD), the oxide skin(coating) 110 of deposition part in this groove 104, undoped silicon glass (undoped silicate glass for example, USG), shown in Fig. 1 C.
Then, continue on high-density electric slurry undoped silicon glass (HDP-USG) 110 deposition one polysilicon layer 112 of compliance referring to Fig. 1 D.In a preferred embodiment, polysilicon layer 112 is amorphous (amorphous) polysilicons that (are lower than 575 ℃) at low temperatures and formed by Low Pressure Chemical Vapor Deposition (LPCVD).And the preferable height of deposition of polysilicon layer 112 is to fill up the top of groove 104 approximately.
Then the semiconductor-based end 100, heat-treated, with oxidation polysilicon layer 112 at high temperature.In preferred embodiment, semiconductor silicon substrate 100 is to place high temperature furnace pipe, oxidation at high temperature, and the polysilicon layer 112 ' thickness after the oxidation is about original twice, shown in Fig. 1 E.
Generally speaking, polysilicon layer has the good ditch ability of filling out, yet its insulating property (properties) is not good.And after Overheating Treatment, polysilicon layer 112 originally changes polysilicon oxide 112 ' into, reach provide simultaneously shallow trench isolation structure good fill out ditch ability and insulating capacity.Simultaneously, after polysilicon layer 112 oxidations, can form the isolation oxide of evenly compacting, not produce and also do not have slit or hole in the groove 104.
At last, utilize cmp to carry out the planarization processing procedure on the surface of semiconductor silicon substrate 100, to form the good fleet plough groove isolation structure 104 of filling shown in Fig. 1 F.
Embodiment two
During Fig. 2 A to Fig. 2 G is depicted as according to another embodiment of the present invention, make the flow process end view of a fleet plough groove isolation structure.
Shown in Fig. 2 A, in semiconductor silicon substrate 200, form pad oxide skin(coating) (pad oxide) 201 and nitride layer (nitride) 202 in regular turn by thermal oxidation processing procedure and low-pressure chemical vapor deposition (LPCVD) respectively.Then, formation and little shadow define a photoresist layer (not shown) on nitride layer 202, to form the channel patterns that follow-up desire forms.Then the channel patterns according to photoresist layer is that curtain cover nitride etching layer 202 is to form channel patterns, then continue as hard mask layer (hard mask) with this nitride layer 202, (reactive ion etching, RIE) the etching pad oxide 201 and the semiconductor-based end 200, are to form groove 204 with the active-ion-etch method.
Then, the thermal oxidation processing procedure is carried out in semiconductor silicon substrate 200, with oxidation formation liner oxide layer (SiO on the bottom of groove 204 and sidewall referring to Fig. 2 B
2) 206.The thermal oxidation processing procedure can contain the wet type thermal oxidation processing procedure that carries out in the environment of aerobic hydrogen mixed gas under 800 to 850 ℃.Perhaps, the thermal oxidation processing procedure can be in oxygen-containing gas, carries out the dry type oxidation 2 hours under in 900 to 950 ℃.In above-mentioned thermal oxidation processing procedure, the inner wall oxide of groove 204 is the liner oxide layer 206 about thickness 100 to 200 dusts ().
After forming liner oxide layer 206 on the inwall of groove 204, then form the inwall of a liner nitride layer (nitride) 208 thereon, shown in Fig. 2 C with protection groove 204.Liner nitride layer 208 can protect the silicon base of groove 204 not to be damaged in follow-up processing procedure, and particularly Zhi Mi nitride 208 can protect groove not by oxygen penetration.
After in groove 204, forming liner oxide layer 206 and liner silicon nitride layer 208, then with high density plasma enhanced chemical vapor deposition method (HDPCVD), the oxide skin(coating) 210 of deposition part in this groove 204, undoped silicon glass (undoped silicate glass for example, USG), shown in Fig. 2 D.Oxide skin(coating) 210 provides the semiconductor-based end 200 of groove 204 walls not influenced by follow-up hot processing procedure except can the bottom of covering protection groove 204 simultaneously.
Then, continue on high-density electric slurry undoped silicon glass (HDP-USG) 210 deposition one polysilicon layer 212 of compliance referring to Fig. 2 E.In a preferred embodiment, polysilicon layer 212 is amorphous (amorphous) polysilicons that (are lower than 575 ℃) at low temperatures and formed by Low Pressure Chemical Vapor Deposition (LPCVD).And the preferable height of deposition of polysilicon layer 212 is to fill up the top of groove 204 approximately.
Then semiconductor silicon substrate 200 is heat-treated, with oxidation polysilicon layer 212 at high temperature.In preferred embodiment, semiconductor silicon substrate 200 is to place high temperature furnace pipe, oxidation at high temperature, and the polysilicon layer 212 ' thickness after the oxidation is about original twice, shown in Fig. 2 F.
After Overheating Treatment, polysilicon layer 212 originally changes polysilicon oxide 212 ' into, reach provide simultaneously shallow trench isolation structure good fill out ditch ability and insulating capacity.Simultaneously, after polysilicon layer 212 oxidations, can form the isolation oxide of evenly compacting, not produce and also do not have slit or hole in the groove 204.
Then, on the polysilicon layer 212 ' after the oxidation, deposit monoxide layer 214 again, enough thickness and smooth surface are provided, carry out in order to follow-up planarization processing procedure, shown in Fig. 2 F.Preferable oxide skin(coating) 214 can be identical with oxide skin(coating) 210, as the undoped silicon glass (USG) of high density plasma enhanced chemical vapor deposition method (HDPCVD) formation.
At last, utilize cmp to carry out planarization processing procedure (CMP) on the surface of semiconductor silicon substrate 200, to form the good fleet plough groove isolation structure 204 of filling shown in Fig. 2 G.
Claims (8)
1. a method of making fleet plough groove isolation structure is applicable in the semiconductor substrate, comprises the following step:
On this semiconductor-based end, form a groove;
On this channel bottom and sidewall, form a liner oxide (liner oxide);
On this liner oxide, form a liner nitride layer (liner nitride);
Monoxide layer by high density plasma enhanced chemical vapor deposition method (HDPCVD) compliance ground deposition part in this groove;
Compliance ground deposition one silicon layer on this oxide skin(coating);
Should carry out a heat treatment the semiconductor-based end with this silicon layer of oxidation; And
Should carry out planarization by semiconductor-based basal surface.
2. the method for manufacturing fleet plough groove isolation structure according to claim 1, wherein this silicon layer is a polysilicon.
3. the method for manufacturing fleet plough groove isolation structure according to claim 2, wherein this polysilicon layer is the amorphous polysilicon layer that forms at low temperatures with chemical vapour deposition technique.
4. the method for manufacturing fleet plough groove isolation structure according to claim 1, wherein this semiconductor-based end is to place high temperature furnace pipe to heat-treat this polysilicon layer of oxidation.
5. the method for manufacturing fleet plough groove isolation structure according to claim 1, wherein this oxide skin(coating) in this groove is the unadulterated silex glass (USG) with high density plasma enhanced chemical vapor deposition method (HDPCVD) deposition.
6. the method for manufacturing fleet plough groove isolation structure according to claim 1 more comprises: deposition one separator on the polysilicon layer after this oxidation.
7. the method for manufacturing fleet plough groove isolation structure according to claim 6, wherein this separator is the unadulterated silex glass (USG) with high density plasma enhanced chemical vapor deposition method (HDPCVD) deposition.
8. the method for manufacturing fleet plough groove isolation structure according to claim 1, wherein the planarization of this semiconductor-based basal surface is to be undertaken by cmp (CMP).
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| CNA031194370A CN1531057A (en) | 2003-03-12 | 2003-03-12 | Method for producing shallow ridges separating structure (STI) |
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| CNA031194370A CN1531057A (en) | 2003-03-12 | 2003-03-12 | Method for producing shallow ridges separating structure (STI) |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449728C (en) * | 2006-06-12 | 2009-01-07 | 中芯国际集成电路制造(上海)有限公司 | Filling method for isolation groove |
| CN101330035B (en) * | 2007-06-18 | 2010-05-19 | 中芯国际集成电路制造(上海)有限公司 | Isolation structure of shallow plough groove and manufacturing method thereof |
| CN1962934B (en) * | 2005-11-12 | 2011-02-09 | 应用材料公司 | Method of fabricating a silicon nitride stack |
| US7989309B2 (en) | 2006-04-30 | 2011-08-02 | Semiconductor Manufacturing International (Shanghai) Corporation | Method of improving a shallow trench isolation gapfill process |
| US8026151B2 (en) | 2006-05-26 | 2011-09-27 | Semiconductor Manufacturing International (Shanghai) Corporation | Method with high gapfill capability for semiconductor devices |
| CN104377134A (en) * | 2013-08-14 | 2015-02-25 | 上海华虹宏力半导体制造有限公司 | Defect-free deep field oxygen isolation growth method of radio frequency transverse diffusion transistors |
| CN106856189A (en) * | 2015-12-09 | 2017-06-16 | 中芯国际集成电路制造(上海)有限公司 | Fleet plough groove isolation structure and forming method thereof |
-
2003
- 2003-03-12 CN CNA031194370A patent/CN1531057A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1962934B (en) * | 2005-11-12 | 2011-02-09 | 应用材料公司 | Method of fabricating a silicon nitride stack |
| US7989309B2 (en) | 2006-04-30 | 2011-08-02 | Semiconductor Manufacturing International (Shanghai) Corporation | Method of improving a shallow trench isolation gapfill process |
| US8026151B2 (en) | 2006-05-26 | 2011-09-27 | Semiconductor Manufacturing International (Shanghai) Corporation | Method with high gapfill capability for semiconductor devices |
| CN101079391B (en) * | 2006-05-26 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for semiconductor part with high clearance filling capability |
| CN100449728C (en) * | 2006-06-12 | 2009-01-07 | 中芯国际集成电路制造(上海)有限公司 | Filling method for isolation groove |
| CN101330035B (en) * | 2007-06-18 | 2010-05-19 | 中芯国际集成电路制造(上海)有限公司 | Isolation structure of shallow plough groove and manufacturing method thereof |
| CN104377134A (en) * | 2013-08-14 | 2015-02-25 | 上海华虹宏力半导体制造有限公司 | Defect-free deep field oxygen isolation growth method of radio frequency transverse diffusion transistors |
| CN104377134B (en) * | 2013-08-14 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | The growing method of radio frequency horizontal proliferation transistor zero defect depth field oxygen isolation |
| CN106856189A (en) * | 2015-12-09 | 2017-06-16 | 中芯国际集成电路制造(上海)有限公司 | Fleet plough groove isolation structure and forming method thereof |
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