CN104377134A - Defect-free deep field oxygen isolation growth method of radio frequency transverse diffusion transistors - Google Patents
Defect-free deep field oxygen isolation growth method of radio frequency transverse diffusion transistors Download PDFInfo
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- CN104377134A CN104377134A CN201310354097.1A CN201310354097A CN104377134A CN 104377134 A CN104377134 A CN 104377134A CN 201310354097 A CN201310354097 A CN 201310354097A CN 104377134 A CN104377134 A CN 104377134A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
Abstract
The invention discloses a defect-free deep field oxygen isolation growth method of radio frequency transverse diffusion transistors. The method comprises the steps that (1), grooves are etched in a silicon wafer; (2), oxidation treatment is carried out on the surface of the silicon wafer to form a first oxide layer; (3), a first non-doping polycrystalline silicon layer is deposited on the surface of the first oxide layer; (4), oxidation treatment is carried out on the surface of the silicon wafer to form a polycrystalline oxide layer; (5), a second non-doping polycrystalline layer is deposited in the grooves, the grooves are seamlessly filled, and it is ensured that non-doping polycrystalline only exists in the grooves through back etching; (6), oxidation treatment is carried out on the surface of the silicon wafer to enable the surface of the non-doping polycrystalline in the grooves to be subjected to oxide isolation, and then the surface of the silicon wafer is flattened to form a deep field oxygen isolation area. The defect-free deep field oxygen isolation growth can meet the requirement of deep field oxygen isolation, stray capacitance of devices is lowered, it is ensured that crystal lattice dislocation caused by introduction of deep field oxygen of a silicon substrate is avoided, and it is guaranteed that other parameters of the devices are not worsened.
Description
Technical field
The present invention relates to the growing method of the dark field oxygen isolation in a kind of semiconductor applications, particularly relate to the growing method of a kind of radio frequency horizontal proliferation transistor zero defect dark field oxygen isolation.
Background technology
Radio frequency laterally diffused MOS pipe (RFLDMOS) is the main devices technology of the wireless base station high power amplifier (PA) of 0.9 ~ 3.8GHz, extensively introduced in portable high power wireless base station PA application from the nineties, its power output is all very high, be particularly suitable for the wireless telecommunications covering long distance, application comprises: 2G/3G/LTE base station PA, broadcast television transmitters (particularly Digital Television), ISM(industrial, scientific and medical), wideband frequency modulation transmitter, airborne transponder, radar system and military communication etc.Compared with silica-based double pole triode, RFLDMOS has the very high linearity, high efficiency and high-gain.
In numerous Particular crafts of RFLDMOS, due to the isolation of dark field oxygen and longitudinal oxide layer, separate device source and drain terminal at a distance, effectively reduce its parasitic capacitance.The reduction RFLMDMOS(radio frequency horizontal proliferation transistor of industry peer company exploitation) method of parasitic capacitance generally comprises: dark field oxygen and thick intermetallic dielectric layer.Owing to there is a lot of PECVD(plasma enhanced chemical vapor deposition method in thick intermetallic dielectric layer) silicon warp that causes of technique and thickness, become membrane granule, the problems such as cost (as shown in Figure 1), thus, there is the problem of a lot of technique volume production, and when adopting the technique of dark field oxygen, because amount of oxidation is excessive, cause stress to worsen, introduce crystal dislocation (as shown in Figure 2).
Summary of the invention
The technical problem to be solved in the present invention is to provide the growing method of a kind of radio frequency horizontal proliferation transistor zero defect dark field oxygen isolation.By method of the present invention, the requirement of dark field oxygen isolation can be met and the problems such as the lattice dislocation caused because adopting dark field oxygen technique of the prior art can be solved.
For solving the problems of the technologies described above, the growing method of radio frequency horizontal proliferation transistor (RFLMDMOS) zero defect of the present invention dark field oxygen isolation, comprises step:
1) on silicon chip, groove is etched;
2) oxidation processes is carried out to the fluted silicon chip surface of tool, form the first oxide layer;
3) the first un-doped polysilicon layer in the first oxide layer on the surface, is deposited;
4) oxidation processes is carried out to the silicon chip surface that deposited the first un-doped polysilicon layer, form polysilicon oxide layer;
5) in groove, deposit the second un-doped polysilicon layer, complete the seamless filled of groove, and there is un-doped polysilicon by returning to guarantee to only have in groove quarter;
6) oxidation processes is carried out to the silicon chip surface that deposited the second un-doped polysilicon layer, make the oxidized isolation in surface of the un-doped polysilicon in groove, then, planarization is carried out to silicon chip surface, thus form dark field oxygen isolated area.
In described step 1), the method for etching is dry etching; The CD(critical size of groove) in Space/line(spacing/live width) be 0.5 ~ 3.0, be preferably 1.8/2.4(be namely preferably 0.75).
Described step 2) in, the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours; The thickness of the first oxide layer is 500 ~ 2500 dusts, is preferably 2000 dusts.
In described step 3), the method for the deposition of polysilicon comprises: chemical vapour deposition technique etc.; The temperature of deposition is 500 ~ 700 DEG C, and the time of deposition is 5 minutes ~ 5 hours; The thickness of the first un-doped polysilicon layer is 1000 ~ 10000 dusts, is preferably 2500 dusts.
In described step 4), the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours; The thickness of polysilicon oxide layer is 1000 ~ 20000 dusts, is preferably 6000 dusts.
In described step 5), the method for the deposition of polysilicon comprises: chemical vapour deposition technique etc.; The temperature of deposition is 500 ~ 700 DEG C, and the time of deposition is 5 minutes ~ 5 hours; The thickness of the second un-doped polysilicon layer is 1000 ~ 20000 dusts, is preferably 12000 dusts; Return carve method be preferably dry back carve.
In described step 6), the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours; The oxidized thickness in un-doped polysilicon surface in groove is 1000 ~ 20000 dusts, is preferably 6000 dusts; The method of planarization comprises: cmp (CMP) method.
Adopt method of the present invention, the requirement of dark field oxygen isolation can be met, reduce device parasitic capacitance; Meanwhile, ensure that silicon substrate does not have the lattice dislocation caused because of the introducing of dark field oxygen, ensure that other parameters of device are not worsened.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is profile scanning Electronic Speculum (SEM) figure of current technique;
Fig. 2 is profile scanning Electronic Speculum (SEM) figure of current technique; Wherein, there is a large amount of Dislocation (lattice dislocation) in this figure;
Fig. 3 be deep plough groove etched after schematic diagram;
Fig. 4 is the schematic diagram after first thin oxidation;
Fig. 5 is the schematic diagram after first un-doped polysilicon is filled;
Fig. 6 is again the schematic diagram after un-doped polysilicon oxidation;
Fig. 7 is again that the schematic diagram after carving is filled and returned to un-doped polysilicon;
Fig. 8 is the schematic diagram after deep trench un-doped polysilicon surface oxidation and planarization;
Fig. 9 is silicon chip topography scan Electronic Speculum (SEM) figure adopting method of the present invention to be formed.
In figure, description of reference numerals is as follows:
1 is silicon chip, and 2 is deep trench, and 3 is the first oxide layer, and 4 is the first un-doped polysilicon layer, and 5 is main separator, and 6 is the second un-doped polysilicon layer, and 7 is isolated area.
Embodiment
The growing method of radio frequency horizontal proliferation transistor (RFLMDMOS) zero defect of the present invention dark field oxygen isolation, comprises step:
1) adopt dry etching, at silicon chip 1(silicon substrate) on, etch groove, groove be herein deep trench 2(as shown in Figure 3);
Wherein, the Space/line(spacing/live width of deep trench 2) ratio is very important, can adopt 0.5 ~ 3.0, generally adopts 1.8/2.4(that is 0.75), guarantee that follow-up silicon warp is in acceptable scope like this;
2) oxidation processes is carried out to silicon chip 1 surface with deep trench 2, forms the first oxide layer 3(as shown in Figure 4), for the first isolated and reparation front layer etching injury of formation;
Wherein, the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours; The thickness of the first oxide layer 3 is 500 ~ 2500 dusts, is preferably 2000 Izods right.
3) by chemical vapour deposition technique etc. in the first oxide layer 3 on the surface, the first un-doped polysilicon layer 4(is deposited as shown in Figure 5);
Wherein, the temperature of deposition is 500 ~ 700 DEG C, and the time of deposition is 5 minutes ~ 5 hours; The thickness of the first un-doped polysilicon layer 4 is 1000 ~ 10000 dusts, is preferably 2500 Izods right.
4) oxidation processes is carried out to silicon chip 1 surface that deposited the first un-doped polysilicon layer 4, form polysilicon oxide layer (as shown in Figure 6), thus form main separator 5;
Wherein, the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours; The thickness of polysilicon oxide layer is 1000 ~ 20000 dusts, is preferably 6000 Izods right.
5) in deep trench 2, deposit the second un-doped polysilicon layer 6 by chemical vapour deposition technique etc., complete the seamless filled of deep trench 2, and carve to guarantee to only have in deep trench 2 by dry back and there is un-doped polysilicon (as shown in Figure 7);
Wherein, the temperature of deposition is 500 ~ 700 DEG C, and the time of deposition is 5 minutes ~ 5 hours; The thickness of the second un-doped polysilicon layer 6 is 1000 ~ 20000 dusts, is preferably 12000 Izods right;
6) oxidation processes is carried out to silicon chip 1 surface that deposited the second un-doped polysilicon layer 6, guarantee to make the oxidized isolation in surface of the un-doped polysilicon in deep trench 2, then, adopt and planarization is carried out to cmp (CMP) method silicon chip 1 surface, final one-tenth, thus the isolated area 7(dark field oxygen isolated area forming the one of bulk) (as shown in Figure 8).
Wherein, the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours; The oxidized thickness in un-doped polysilicon surface in deep trench is 1000 ~ 20000 dusts, is preferably 6000 Izods right.
The present invention adopts the mode of deep trench lateral oxidation, rationalize the Primary Oxidation of silicon trench size and silicon substrate, introduce the oxidation again that follow-up polysilicon fills deep trench and polycrystalline silicon, finally complete deep-trench polysilicon fill and be oxidized sealing and planarization, the final bulk oxidation forming low stress completely cuts off district.Wherein, silicon chip topography scan Electronic Speculum (SEM) figure adopting method of the present invention finally to be formed, as shown in Figure 9.As shown in Figure 9, lattice dislocation is not had in figure.
Thus, the present invention can not only meet the requirement of dark field oxygen isolation, reduces device parasitic capacitance, can also guarantee that silicon substrate (silicon chip) does not have the lattice dislocation caused because of the introducing of dark field oxygen, ensure that other parameters of device are not worsened.
Claims (13)
1. a growing method for radio frequency horizontal proliferation transistor zero defect dark field oxygen isolation, is characterized in that, comprise step:
1) on silicon chip, groove is etched;
2) oxidation processes is carried out to the fluted silicon chip surface of tool, form the first oxide layer;
3) the first un-doped polysilicon layer in the first oxide layer on the surface, is deposited;
4) oxidation processes is carried out to the silicon chip surface that deposited the first un-doped polysilicon layer, form polysilicon oxide layer;
5) in groove, deposit the second un-doped polysilicon layer, complete the seamless filled of groove, and there is un-doped polysilicon by returning to guarantee to only have in groove quarter;
6) oxidation processes is carried out to the silicon chip surface that deposited the second un-doped polysilicon layer, make the oxidized isolation in surface of the un-doped polysilicon in groove, then, planarization is carried out to silicon chip surface, thus form dark field oxygen isolated area.
2. the method for claim 1, is characterized in that: in described step 1), and the method for etching is dry etching; Spacing/live width in the critical size of groove is 0.5 ~ 3.0.
3. method as claimed in claim 2, is characterized in that: the spacing/live width in the critical size of described groove is 1.8/2.4.
4. the method for claim 1, is characterized in that: described step 2) in, the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours;
The thickness of the first oxide layer is 500 ~ 2500 dusts, is preferably 2000 dusts.
5. method as claimed in claim 4, is characterized in that: the thickness of described first oxide layer is 2000 dusts.
6. the method for claim 1, is characterized in that: in described step 3), and the method for polysilicon deposition comprises: chemical vapour deposition technique;
The temperature of deposition is 500 ~ 700 DEG C, and the time of deposition is 5 minutes ~ 5 hours;
The thickness of the first un-doped polysilicon layer is 1000 ~ 10000 dusts.
7. method as claimed in claim 6, is characterized in that: the thickness of described first un-doped polysilicon layer is 2500 dusts.
8. the method for claim 1, is characterized in that: in described step 4), and the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours;
The thickness of polysilicon oxide layer is 1000 ~ 20000 dusts.
9. method as claimed in claim 8, is characterized in that: the thickness of described polysilicon oxide layer is 6000 dusts.
10. the method for claim 1, is characterized in that: in described step 5), and the method for polysilicon deposition comprises: chemical vapour deposition technique;
The temperature of deposition is 500 ~ 700 DEG C, and the time of deposition is 5 minutes ~ 5 hours;
The thickness of the second un-doped polysilicon layer is 1000 ~ 20000 dusts;
Returning the method for carving is that dry back is carved.
11. methods as claimed in claim 10, is characterized in that: the thickness of described second un-doped polysilicon layer is 12000 dusts.
12. the method for claim 1, is characterized in that: in described step 6), and the temperature of oxidation processes is 800 ~ 1200 DEG C, and the time of oxidation processes is 10 minutes ~ 5 hours;
The oxidized thickness in un-doped polysilicon surface in groove is 1000 ~ 20000 dusts;
The method of planarization comprises: chemical mechanical milling method.
13. methods as claimed in claim 12, is characterized in that: the oxidized thickness in un-doped polysilicon surface in described groove is 6000 dusts.
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| CN1531057A (en) * | 2003-03-12 | 2004-09-22 | 矽统科技股份有限公司 | Method for producing shallow ridges separating structure (STI) |
| US20110140228A1 (en) * | 2009-12-15 | 2011-06-16 | Xiaobin Wang | Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices |
| US20110175191A1 (en) * | 2009-12-21 | 2011-07-21 | Stmicroelectronics S.R.L. | Isolation trenches for semiconductor layers |
| CN103011048A (en) * | 2011-09-26 | 2013-04-03 | 美格纳半导体有限公司 | Isolation structure, semiconductor device having the same, and method for fabricating the isolation structure |
| CN103035514A (en) * | 2012-05-16 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method for forming thick silicon oxide isolation layer in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN103050534A (en) * | 2012-08-20 | 2013-04-17 | 上海华虹Nec电子有限公司 | Structure and manufacture method of RFLDMOS (ratio frequency laterally diffused metal oxide semiconductor) thick field oxygen isolation medium layer |
| CN103137540A (en) * | 2011-11-29 | 2013-06-05 | 上海华虹Nec电子有限公司 | Manufacturing method of thick isolation dielectric medium layer structure of RFLDMOS |
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2013
- 2013-08-14 CN CN201310354097.1A patent/CN104377134B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531057A (en) * | 2003-03-12 | 2004-09-22 | 矽统科技股份有限公司 | Method for producing shallow ridges separating structure (STI) |
| US20110140228A1 (en) * | 2009-12-15 | 2011-06-16 | Xiaobin Wang | Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices |
| US20110175191A1 (en) * | 2009-12-21 | 2011-07-21 | Stmicroelectronics S.R.L. | Isolation trenches for semiconductor layers |
| CN103011048A (en) * | 2011-09-26 | 2013-04-03 | 美格纳半导体有限公司 | Isolation structure, semiconductor device having the same, and method for fabricating the isolation structure |
| CN103137540A (en) * | 2011-11-29 | 2013-06-05 | 上海华虹Nec电子有限公司 | Manufacturing method of thick isolation dielectric medium layer structure of RFLDMOS |
| CN103035514A (en) * | 2012-05-16 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method for forming thick silicon oxide isolation layer in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
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