US20120142121A1 - Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication - Google Patents

Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication Download PDF

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US20120142121A1
US20120142121A1 US12/960,736 US96073610A US2012142121A1 US 20120142121 A1 US20120142121 A1 US 20120142121A1 US 96073610 A US96073610 A US 96073610A US 2012142121 A1 US2012142121 A1 US 2012142121A1
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epitaxial growth
semiconductor structure
source
etch
drain
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US8187975B1 (en
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Prasanna Khare
Nicolas Loubet
Qing Liu
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STMICROELECTRONICS INTERNATIONAL NV
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STMicroelectronics lnc USA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Definitions

  • the present invention relates generally to semiconductor fabrication processes and, more particularly, to a semiconductor fabrication process useful in building a transistor having a raised source-drain structure.
  • a transistor having a raised source-drain structure is well known in the art. There are a number of recognized fabrication processes for building such a transistor. These processes share in common a fabrication step for selectively depositing semiconductor material above the source region and drain region of a partially constructed transistor. This selective deposition of semiconductor material to form the raised source-drain structure is commonly accomplished through selective epitaxial growth.
  • FIG. 1 shows a cross-section of semiconductor structure for a partially constructed MOS-type transistor.
  • the semiconductor structure includes a transistor gate 10 formed above a substrate 12 (for example, a silicon substrate including, if desired, doping).
  • the transistor gate 10 includes, for example, a gate oxide 14 , a gate conductor 16 , an off-set spacer 18 , a liner 20 and a sidewall spacer 22 .
  • the substrate 12 includes doped regions 24 on either side of the transistor gate 10 defining the source region and drain region (such regions including, although not specifically illustrated, lightly doped structures, heavily doped structures, extensions and/or halo implants as known in the art).
  • a channel region 26 of the transistor is positioned between the doped regions 24 and underneath the transistor gate 10 .
  • the upper surface 28 of the substrate 12 at the doped regions 24 can become damaged.
  • this damage could be the result of the performance of one or more plasma etching operations or other fabrication or treatment processes used to define the transistor gate 10 .
  • FIG. 2 shows a cross-section of the semiconductor structure with the partially constructed MOS-type transistor following processing in the first chamber to remove the damaged surface layer 30 .
  • the advantage of performing RIE etching along with the other treatment and cleaning processes (such as an O 2 plasma flash with oxide and H 2 cleaning), as opposed to solely using the other treatment and cleaning processes, to remove damaged surface layer 30 at each of the doped regions 24 , is that the use of the RIE etch process produces a clean interface surface 32 suitable for supporting subsequent epitaxial growth to form the overlying raised source-drain structure.
  • An additional advantage to using the RIE etch process is that the subsequent epitaxial growth to form the overlying raised source-drain structure has a growth rate that is doping independent.
  • a disadvantage of performing RIE etching (and with respect to the use of other treatment and cleaning processes, as well) to remove damaged surface layer 30 is that a subsequent high temperature pre-bake process is required to prepare the interface surface 32 of the doped regions 24 before beginning epitaxial growth and forming the overlying raised source-drain structure.
  • a next step in the prior art fabrication process comprises subjecting the semiconductor structure as shown in FIG. 2 to a pre-bake treatment 82 .
  • the pre-bake treatment 82 with a high thermal budget results in a significant diffusion of dopants for the source-drain extensions and halo implants.
  • the pre-bake operation is typically performed at a relatively high temperature at or exceeding approximately 800° C., and some undesired dopant diffusion will necessarily occur.
  • FIG. 3 shows a cross-section of a semiconductor structure with a partially constructed MOS-type transistor following processing in the second chamber 84 to epitaxially grow the raised source-drain structures 34 from the interface surface 32 .
  • RIE etching to remove the damaged surface layer 30 and prepare the interface surface 32 for epitaxial growth is preferred because the resulting semiconductor structure does not exhibit a “seam” (or there is only a minimal seam) or interface at the interface surface 32 between the doped regions 24 and the raised source-drain structures 34 .
  • a lower temperature cleaning and a lower temperature pre-bake may address issues with respect to excessive undesired dopant diffusion of the source-drain extensions and halo implants, but produce a lower quality interface surface 32 for epitaxial growth of the raised source-drain regions with a distinct “seam” interface exhibiting oxygen and/or carbon concentrations.
  • a high temperature pre-bake may produce a cleaner interface surface for satisfactory epitaxial growth of the raised source-drain regions, but produce an unacceptable degree of extension and halo implant dopant diffusion.
  • a process comprises: receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer; preparing a controlled atmosphere within the process chamber; performing an etch to remove the damaged surface layers from the source and drain regions and expose an interface surface; and without releasing the controlled atmosphere, and within the same process chamber, performing an epitaxial growth to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
  • a process comprises: receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer; preparing a controlled atmosphere within the process chamber; setting a temperature within the process chamber at less than 800° C.; performing, at the controlled atmosphere and at the set temperature, an etch with hydrochloric acid to remove the damaged surface layers from the source and drain regions and expose an interface surface; and without releasing the controlled atmosphere and with maintaining the set temperature, performing within the same process chamber a cyclical epitaxial growth to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
  • a process comprises: receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer; drawing substantially a vacuum within the process chamber; using the process chamber at the drawn vacuum and the supported etching process to remove the damaged surface layers and expose an etched interface surface at each of the source region and drain region; and using the process chamber maintained at the drawn vacuum and the supported epitaxial growth process to grow from the exposed etched interface surface a raised region above each of the source and drain regions.
  • FIGS. 1 to 3 illustrate a cross-section of a partially constructed MOS-type transistor in accordance with a prior art process for fabricating a raised source-drain structure
  • FIGS. 4 to 6 illustrate a cross-section of a partially constructed MOS-type transistor in accordance with an exemplary process of the present invention for fabricating a raised source-drain structure on a semiconductor structure.
  • FIGS. 4 to 6 illustrate a cross-section of a partially constructed MOS-type transistor in accordance with an exemplary process of the present invention for fabricating a raised source-drain structure on a semiconductor structure.
  • a semiconductor structure 100 is shown for a partially constructed MOS-type transistor.
  • the structure 100 includes a transistor gate 110 formed above a substrate 112 (for example, a silicon substrate including, if desired, doping).
  • the transistor gate 110 includes, for example, a gate oxide 114 , a gate conductor 116 , an off-set spacer 118 , a liner 120 and a sidewall spacer 122 .
  • the substrate 112 includes doped regions 124 on either side of the transistor gate 110 defining the source region and drain region (such regions including, although not specifically illustrated, lightly doped structures, heavily doped structures, extensions and/or halo implants as known in the art).
  • a channel region 126 is positioned between the doped regions 124 and underneath the transistor gate 110 .
  • the upper surface 128 of the substrate 112 at the doped regions 124 can become damaged.
  • this damage could be the result of the performance of one or more plasma etching operations or other fabrication or treatment processes used to define the transistor gate 110 .
  • the semiconductor structure 100 shown in FIG. 4 is placed within a process chamber 200 .
  • the process chamber 200 is of the type configured and suited to perform an in-situ etch and epitaxial growth.
  • the process chamber 200 is capable of receiving a structure, producing a controlled atmosphere (such as a vacuum), performing an etch on the received structure, and performing an epitaxial growth on the received structure after etching, in a sequential fashion without breaking the controlled atmosphere (vacuum) and while maintaining certain process temperature settings.
  • a controlled atmosphere such as a vacuum
  • the process chamber 200 implements an etching process.
  • the etching process is performed as an in-situ etch of the doped regions 124 (for example, a silicon etch) using hydrochloric acid (HCl) 204 with a carrier gas (such as hydrogen). This etch is selective as to the doped regions 124 , and thus does not affect the structure of the transistor gate 110 (for example, if a standard dielectric hard-mask is used on the transistor gate structure).
  • the etch 204 does, however, remove (at least) the damaged surface layer 130 at each of the doped regions 124 .
  • any suitable standard surface preparation process such as HF-last (i.e., hydrofluoric acid last surface preparation process) or COR-last (i.e. chemical oxide removal last surface preparation process), may be performed on the semiconductor structure 100 within the chamber 200 .
  • the etch is performed at a set chamber temperature of, for example, 650-750° C. (it being recognized that setting the temperature in this manner has a negligible effect on dopant diffusion).
  • FIG. 5 shows a cross-section of the semiconductor structure 100 for the partially constructed MOS-type transistor following processing in the chamber 200 to remove damaged surface layer 130 .
  • the etch 204 FIG. 4
  • the vacuum 202 FIG. 4
  • the temperature is also maintained.
  • the removal of the damaged surface layer 130 at each of the doped regions 124 using the etch 204 produces a clean interface surface 132 upon which subsequent epitaxial growth may occur to form an overlying raised source-drain structure.
  • An additional advantage to using the etch 204 process is that the subsequent epitaxial growth to form the overlying raised source-drain structure has growth rate which is doping independent. Still further, use of the etch 204 , along with continued processing in the chamber 200 , obviates the need to perform a pre-bake prior to epitaxial growth (and thus unacceptably expose the substrate to an undesired dopant diffusing higher thermal budget).
  • a selective epitaxial growth 208 (in a cyclical process) is then performed within the chamber 200 so as to deposit semiconductor material forming the raised source-drain structures 134 over the doped regions 124 by means of growth (for example, silicon growth) from the clean interface surface 132 of the substrate. It is important to note that the process for selective epitaxial growth is performed in the same process chamber 200 as was used to perform the selective etch 204 for removing the damaged surface layer 130 .
  • FIG. 6 shows a cross-section of the semiconductor structure 100 for the partially constructed MOS-type transistor following processing in the second chamber to epitaxially grow the raised source-drain structures 134 .
  • etching 204 to remove the damaged surface layer 130 prepares the structure 100 for an epitaxial growth that does not exhibit a “seam” (or there is only a minimal seam) or interface at the interface surface 132 between the doped regions 124 and the raised source-drain structures 134 .
  • the vacuum 202 FIG. 4
  • the temperature is also maintained.
  • the selective epitaxial growth 208 is performed at the same temperature of, for example, 650-750° C., as the etch 204 (and thus has a negligible effect on dopant diffusion).
  • the interface surface 132 is a very clean interface because the in-situ etch and epitaxial growth are performed in the same chamber 200 (reactor).
  • the resulting transistor will exhibit lower leakage and lower resistance than a comparable transistor formed in accordance with the prior art process shown in FIGS. 1 to 3 .
  • the use of a lower temperature epitaxial growth process to produce the raised source-drain structures 134 serves to suppress dopant diffusion as a result of the epitaxial process. This results in a significantly improved raised source-drain structure than could be obtained with the high thermal budget process for epitaxial growth used with the prior art process shown in FIGS. 1 to 3 .
  • the suppression of dopant diffusion with the raised source-drain process described above produces a transistor with better electrostatics (short channel effects—SCE).
  • Performing epitaxial growth immediately after performing the etch in the same chamber advantageously results in seamless growth from the interface surface at the source and drain regions.

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Abstract

A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

Description

    BACKGROUND
  • 1. Technical Field
  • The present invention relates generally to semiconductor fabrication processes and, more particularly, to a semiconductor fabrication process useful in building a transistor having a raised source-drain structure.
  • 2. Description of Related Art
  • A transistor having a raised source-drain structure is well known in the art. There are a number of recognized fabrication processes for building such a transistor. These processes share in common a fabrication step for selectively depositing semiconductor material above the source region and drain region of a partially constructed transistor. This selective deposition of semiconductor material to form the raised source-drain structure is commonly accomplished through selective epitaxial growth.
  • FIG. 1 shows a cross-section of semiconductor structure for a partially constructed MOS-type transistor. The semiconductor structure includes a transistor gate 10 formed above a substrate 12 (for example, a silicon substrate including, if desired, doping). The transistor gate 10 includes, for example, a gate oxide 14, a gate conductor 16, an off-set spacer 18, a liner 20 and a sidewall spacer 22. The substrate 12 includes doped regions 24 on either side of the transistor gate 10 defining the source region and drain region (such regions including, although not specifically illustrated, lightly doped structures, heavily doped structures, extensions and/or halo implants as known in the art). A channel region 26 of the transistor is positioned between the doped regions 24 and underneath the transistor gate 10. Those skilled in the art are well aware of suitable fabrication processes for forming the semiconductor structure with the partially constructed MOS-type transistor shown in FIG. 1.
  • As a result of the fabrication processes used to reach the partially constructed MOS-type transistor shown in FIG. 1, those skilled in the art recognize that the upper surface 28 of the substrate 12 at the doped regions 24 (comprising the source region and the drain region) can become damaged. For example, this damage could be the result of the performance of one or more plasma etching operations or other fabrication or treatment processes used to define the transistor gate 10. This results in the presence of a damaged surface layer 30 at the upper surface 28 of each of the doped regions 24.
  • In the context of forming a raised source-drain structure above the doped regions 24, it is important to provide a high quality interface between the doped regions 24 and the overlying raised source-drain structure produced by subsequent epitaxial growth. The damaged surface layer 30 is not considered by those skilled in the art to present an acceptable high quality interface for a raised source-drain structure. Prior art semiconductor transistor fabrication processes accordingly teach placing the semiconductor structure of FIG. 1 in a first process chamber 80 and subjecting the semiconductor structure to a treatment and cleaning process (such as an O2 plasma flash with oxide and H2 cleaning) so as to remove damaged surface layer 30 at each of the doped regions 24. The prior art further teaches using the first process chamber 80 to further subject the semiconductor structure to a reactive ion etch (RIE) so as to remove damaged surface layer 30 at each of the doped regions 24. FIG. 2 shows a cross-section of the semiconductor structure with the partially constructed MOS-type transistor following processing in the first chamber to remove the damaged surface layer 30.
  • The advantage of performing RIE etching along with the other treatment and cleaning processes (such as an O2 plasma flash with oxide and H2 cleaning), as opposed to solely using the other treatment and cleaning processes, to remove damaged surface layer 30 at each of the doped regions 24, is that the use of the RIE etch process produces a clean interface surface 32 suitable for supporting subsequent epitaxial growth to form the overlying raised source-drain structure. An additional advantage to using the RIE etch process is that the subsequent epitaxial growth to form the overlying raised source-drain structure has a growth rate that is doping independent.
  • A disadvantage of performing RIE etching (and with respect to the use of other treatment and cleaning processes, as well) to remove damaged surface layer 30 is that a subsequent high temperature pre-bake process is required to prepare the interface surface 32 of the doped regions 24 before beginning epitaxial growth and forming the overlying raised source-drain structure. So, a next step in the prior art fabrication process comprises subjecting the semiconductor structure as shown in FIG. 2 to a pre-bake treatment 82. It is recognized, however, that the pre-bake treatment 82 with a high thermal budget results in a significant diffusion of dopants for the source-drain extensions and halo implants. Thus, it is desired to minimize that the thermal budget preparing the interface surface 32 as much as possible. Nonetheless, the pre-bake operation is typically performed at a relatively high temperature at or exceeding approximately 800° C., and some undesired dopant diffusion will necessarily occur.
  • Following completion of the pre-bake and preparation of the interface surface 32, a selective epitaxial growth is performed so as to deposit semiconductor material forming the raised source-drain structures 34 over the doped regions 24. It is important to note that the process for selective epitaxial growth from the interface surface 32 is performed in a second process chamber 84 (i.e., a process chamber 84 different from the first process chamber 80 used RIE etching and the removal of damaged surface layer 30). FIG. 3 shows a cross-section of a semiconductor structure with a partially constructed MOS-type transistor following processing in the second chamber 84 to epitaxially grow the raised source-drain structures 34 from the interface surface 32. Then use of RIE etching to remove the damaged surface layer 30 and prepare the interface surface 32 for epitaxial growth is preferred because the resulting semiconductor structure does not exhibit a “seam” (or there is only a minimal seam) or interface at the interface surface 32 between the doped regions 24 and the raised source-drain structures 34.
  • The higher the thermal budget for the pre-bake, the higher the quality of the clean interface surface 32. However, the higher the thermal budget the greater the undesired degree of dopant diffusion with respect to the source-drain extensions and halo implants. Thus, those skilled in the art using the known prior art processes for fabricating transistors with raised source-drain structures must trade-off the advantage of a clean interface surface 32 against the disadvantage of higher dopant diffusion. For example, a lower temperature cleaning and a lower temperature pre-bake may address issues with respect to excessive undesired dopant diffusion of the source-drain extensions and halo implants, but produce a lower quality interface surface 32 for epitaxial growth of the raised source-drain regions with a distinct “seam” interface exhibiting oxygen and/or carbon concentrations. Conversely, a high temperature pre-bake may produce a cleaner interface surface for satisfactory epitaxial growth of the raised source-drain regions, but produce an unacceptable degree of extension and halo implant dopant diffusion.
  • There is a need in the art for an improved process for fabricating raised source-drain structures that addresses the foregoing, and other, deficiencies, limitations and trade-offs noted with respect to the prior art processes and fabrication techniques. In particular, there would be an advantage to a process for forming raised source-drain structures with clean interface surfaces using a lower thermal budget that did not produce unacceptable dopant diffusion.
    • SUMMARY
  • In an embodiment, a process comprises: receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer; preparing a controlled atmosphere within the process chamber; performing an etch to remove the damaged surface layers from the source and drain regions and expose an interface surface; and without releasing the controlled atmosphere, and within the same process chamber, performing an epitaxial growth to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
  • In an embodiment, a process comprises: receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer; preparing a controlled atmosphere within the process chamber; setting a temperature within the process chamber at less than 800° C.; performing, at the controlled atmosphere and at the set temperature, an etch with hydrochloric acid to remove the damaged surface layers from the source and drain regions and expose an interface surface; and without releasing the controlled atmosphere and with maintaining the set temperature, performing within the same process chamber a cyclical epitaxial growth to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
  • In an embodiment, a process comprises: receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer; drawing substantially a vacuum within the process chamber; using the process chamber at the drawn vacuum and the supported etching process to remove the damaged surface layers and expose an etched interface surface at each of the source region and drain region; and using the process chamber maintained at the drawn vacuum and the supported epitaxial growth process to grow from the exposed etched interface surface a raised region above each of the source and drain regions.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • A more complete understanding of the method and apparatus of the present invention may be acquired by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:
  • FIGS. 1 to 3 illustrate a cross-section of a partially constructed MOS-type transistor in accordance with a prior art process for fabricating a raised source-drain structure; and
  • FIGS. 4 to 6 illustrate a cross-section of a partially constructed MOS-type transistor in accordance with an exemplary process of the present invention for fabricating a raised source-drain structure on a semiconductor structure.
    •  DETAILED DESCRIPTION OF THE DRAWINGS
  • Reference is now made to FIGS. 4 to 6 which illustrate a cross-section of a partially constructed MOS-type transistor in accordance with an exemplary process of the present invention for fabricating a raised source-drain structure on a semiconductor structure.
  • A semiconductor structure 100 is shown for a partially constructed MOS-type transistor. The structure 100 includes a transistor gate 110 formed above a substrate 112 (for example, a silicon substrate including, if desired, doping). The transistor gate 110 includes, for example, a gate oxide 114, a gate conductor 116, an off-set spacer 118, a liner 120 and a sidewall spacer 122. The substrate 112 includes doped regions 124 on either side of the transistor gate 110 defining the source region and drain region (such regions including, although not specifically illustrated, lightly doped structures, heavily doped structures, extensions and/or halo implants as known in the art). A channel region 126 is positioned between the doped regions 124 and underneath the transistor gate 110. Those skilled in the art are well aware of suitable fabrication processes for forming the partially constructed MOS-type transistor for the semiconductor structure 100 shown in FIG. 3.
  • As a result of the fabrication processes used to reach the partially constructed MOS-type transistor with the semiconductor structure 100 shown in FIG. 4, those skilled in the art recognize that the upper surface 128 of the substrate 112 at the doped regions 124 (for the source region and the drain region) can become damaged. For example, this damage could be the result of the performance of one or more plasma etching operations or other fabrication or treatment processes used to define the transistor gate 110. This results in the presence of a damaged surface layer 130 at the upper surface 128 of each of the doped regions 124.
  • The semiconductor structure 100 shown in FIG. 4 is placed within a process chamber 200. The process chamber 200 is of the type configured and suited to perform an in-situ etch and epitaxial growth. In other words, the process chamber 200 is capable of receiving a structure, producing a controlled atmosphere (such as a vacuum), performing an etch on the received structure, and performing an epitaxial growth on the received structure after etching, in a sequential fashion without breaking the controlled atmosphere (vacuum) and while maintaining certain process temperature settings.
  • Once the semiconductor structure 100 is received within the process chamber 200, the chamber is sealed and a controlled atmosphere is created (for example, by drawing a vacuum 202). After the controlled atmosphere has been successfully created, the process chamber 200 implements an etching process. In a preferred implementation, the etching process is performed as an in-situ etch of the doped regions 124 (for example, a silicon etch) using hydrochloric acid (HCl) 204 with a carrier gas (such as hydrogen). This etch is selective as to the doped regions 124, and thus does not affect the structure of the transistor gate 110 (for example, if a standard dielectric hard-mask is used on the transistor gate structure). The etch 204 does, however, remove (at least) the damaged surface layer 130 at each of the doped regions 124. Prior to performing the etch 204, any suitable standard surface preparation process, such as HF-last (i.e., hydrofluoric acid last surface preparation process) or COR-last (i.e. chemical oxide removal last surface preparation process), may be performed on the semiconductor structure 100 within the chamber 200. The etch is performed at a set chamber temperature of, for example, 650-750° C. (it being recognized that setting the temperature in this manner has a negligible effect on dopant diffusion).
  • FIG. 5 shows a cross-section of the semiconductor structure 100 for the partially constructed MOS-type transistor following processing in the chamber 200 to remove damaged surface layer 130. It will be noted that the etch 204 (FIG. 4) has been terminated, but the vacuum 202 (FIG. 4) has been maintained 206 (i.e., there is no break in the controlled atmosphere following completion of the etch 204). Preferably, the temperature is also maintained. The removal of the damaged surface layer 130 at each of the doped regions 124 using the etch 204 produces a clean interface surface 132 upon which subsequent epitaxial growth may occur to form an overlying raised source-drain structure. An additional advantage to using the etch 204 process is that the subsequent epitaxial growth to form the overlying raised source-drain structure has growth rate which is doping independent. Still further, use of the etch 204, along with continued processing in the chamber 200, obviates the need to perform a pre-bake prior to epitaxial growth (and thus unacceptably expose the substrate to an undesired dopant diffusing higher thermal budget).
  • A selective epitaxial growth 208 (in a cyclical process) is then performed within the chamber 200 so as to deposit semiconductor material forming the raised source-drain structures 134 over the doped regions 124 by means of growth (for example, silicon growth) from the clean interface surface 132 of the substrate. It is important to note that the process for selective epitaxial growth is performed in the same process chamber 200 as was used to perform the selective etch 204 for removing the damaged surface layer 130. FIG. 6 shows a cross-section of the semiconductor structure 100 for the partially constructed MOS-type transistor following processing in the second chamber to epitaxially grow the raised source-drain structures 134. The use of etching 204 to remove the damaged surface layer 130 prepares the structure 100 for an epitaxial growth that does not exhibit a “seam” (or there is only a minimal seam) or interface at the interface surface 132 between the doped regions 124 and the raised source-drain structures 134. It will be noted that the vacuum 202 (FIG. 4) continues to be maintained 206 (i.e., there is no break in the controlled atmosphere) at least until completion of the selective epitaxial growth 208 operation. Preferably, the temperature is also maintained. Thus, the selective epitaxial growth 208 is performed at the same temperature of, for example, 650-750° C., as the etch 204 (and thus has a negligible effect on dopant diffusion).
  • The interface surface 132 is a very clean interface because the in-situ etch and epitaxial growth are performed in the same chamber 200 (reactor). The resulting transistor will exhibit lower leakage and lower resistance than a comparable transistor formed in accordance with the prior art process shown in FIGS. 1 to 3.
  • The use of a cyclic process for the selective epitaxial growth 208 advantageously results in no parasitic growth at the corners of the transistor gate 110 (even if the protective hard mask coverage is weak at those corners).
  • The use of a lower temperature epitaxial growth process to produce the raised source-drain structures 134 serves to suppress dopant diffusion as a result of the epitaxial process. This results in a significantly improved raised source-drain structure than could be obtained with the high thermal budget process for epitaxial growth used with the prior art process shown in FIGS. 1 to 3. The suppression of dopant diffusion with the raised source-drain process described above produces a transistor with better electrostatics (short channel effects—SCE).
  • Performing epitaxial growth immediately after performing the etch in the same chamber advantageously results in seamless growth from the interface surface at the source and drain regions.
  • The remaining process steps for completing fabrication of the transistor, such as adding the dielectric layer, forming contacts to the source, drain and gate, adding metallization layers, and the like are well known to those skilled in the art and will not be discussed.
  • Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.

Claims (21)

1. A process, comprising:
receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer;
preparing a controlled atmosphere within the process chamber;
performing an etch to remove the damaged surface layers from the source and drain regions and expose an interface surface; and
without releasing the controlled atmosphere, and within the same process chamber, performing an epitaxial growth to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
2. The process of claim 1, further comprising, prior to performing the etch, performing a surface preparation on the semiconductor structure.
3. The process of claim 2, wherein the surface preparation comprises a selected one of an HF-last process or a COR-last process.
4. The process of claim 1, wherein performing the etch and performing the epitaxial growth are performed within the same process chamber at substantially a same controlled atmosphere.
5. The process of claim 4, wherein the controlled atmosphere is substantially a vacuum.
6. The process of claim 1, wherein performing the etch and performing the epitaxial growth are performed within the same process chamber at substantially a same temperature.
7. The process of claim 6, wherein the same temperature is about between 650-750° C.
8. The process of claim 1, wherein performing the etch comprises exposing the semiconductor structure to hydrochloric acid.
9. The process of claim 1, wherein performing the epitaxial growth comprises performing a cyclic epitaxial growth.
10. The process of claim 1, wherein the process does not include performing pre-bake of the semiconductor structure prior to performing the epitaxial growth.
11. The process of claim 1, wherein the process does not include exposing the semiconductor structure to a temperature within the chamber in excess of 800° C. prior to performing the epitaxial growth.
12. A process, comprising:
receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer;
preparing a controlled atmosphere within the process chamber;
setting a temperature within the process chamber at less than 800° C.;
performing, at the controlled atmosphere and at the set temperature, an etch with hydrochloric acid to remove the damaged surface layers from the source and drain regions and expose an interface surface; and
without releasing the controlled atmosphere and with maintaining the set temperature, performing within the same process chamber a cyclical epitaxial growth to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
13. The process of claim 12, wherein the controlled atmosphere is substantially a vacuum, and wherein the set temperature is about between 650-750° C.
14. The process of claim 12, further comprising, prior to performing the etch, performing a surface preparation on the semiconductor structure.
15. The process of claim 14, wherein the surface preparation comprises a selected one of an HF-last process or a COR-last process.
16. The process of claim 12, wherein the process does not include performing pre-bake of the semiconductor structure prior to performing the epitaxial growth.
17. A process, comprising:
receiving a semiconductor structure in a process chamber adapted to support both an etching process and an epitaxial growth process, the semiconductor structure including a source region and a drain region, wherein the source and drain regions each include a damaged surface layer;
drawing substantially a vacuum within the process chamber;
using the process chamber at the drawn vacuum and the supported etching process to remove the damaged surface layers and expose an etched interface surface at each of the source region and drain region; and
using the process chamber maintained at the drawn vacuum and the supported epitaxial growth process to grow from the exposed etched interface surface a raised region above each of the source and drain regions.
18. The process of claim 17, further comprising, prior to performing the etch, performing a surface preparation on the semiconductor structure.
19. The process of claim 17, wherein performing the etch and performing the epitaxial growth are performed within the same process chamber maintained at the drawn vacuum and at substantially a same temperature.
20. The process of claim 19, wherein the same temperature is about between 650-750° C.
21. The process of claim 17, wherein the process does not include performing pre-bake of the semiconductor structure prior to performing the epitaxial growth.
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