CN104377134B - The growing method of radio frequency horizontal proliferation transistor zero defect depth field oxygen isolation - Google Patents
The growing method of radio frequency horizontal proliferation transistor zero defect depth field oxygen isolation Download PDFInfo
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- CN104377134B CN104377134B CN201310354097.1A CN201310354097A CN104377134B CN 104377134 B CN104377134 B CN 104377134B CN 201310354097 A CN201310354097 A CN 201310354097A CN 104377134 B CN104377134 B CN 104377134B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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Abstract
The invention discloses a kind of growing method of the deep field oxygen isolation of radio frequency horizontal proliferation transistor zero defect, including step：1）On silicon chip, groove is etched；2）Oxidation processes are carried out to silicon chip surface, the first oxide layer is formed；3）In the first oxidation layer surface, the first non-doped polysilicon layer is deposited；4）Oxidation processes are carried out to silicon chip surface, polysilicon oxide layer is formed；5）In groove, the second non-doped polysilicon layer is deposited, the seamless filled of groove is completed, and ensure there is un-doped polysilicon in only groove quarter by returning；6）Oxidation processes are carried out to silicon chip surface, the un-doped polysilicon surface in groove is oxidized isolation, then, silicon chip surface is planarized, so as to form deep field oxygen isolation area.The present invention can meet the requirement of deep field oxygen isolation, reduce device parasitic electric capacity, it is ensured that silicon substrate is without lattice dislocation caused by the introducing because of deep field oxygen, it is ensured that the other specification of device is not deteriorated.
Description
Technical field
The present invention relates to a kind of growing method of the isolation of the deep field oxygen in semiconductor applications, more particularly to a kind of radio frequency is horizontal
To the growing method of the deep field oxygen isolation of diffusion transistor zero defect.
Background technology
Radio frequency laterally diffused MOS pipe（RFLDMOS）It is 0.9~3.8GHz wireless base station high power amplifier（PA）Master
Device technology is wanted, is introduced into extensively in portable high power wireless base station PA applications since the nineties, its power output is all non-
Chang Gao, is particularly suitable for covering the wireless telecommunications of long range, and application field includes：2G/3G/LTE base stations PA, broadcast television transmitters
（Particularly DTV）、ISM（industrial,scientific and medical）, wideband frequency modulation emitter, machine
Carry transponder, radar system and military communication etc..Compared with the double pole triode of silicon substrate, RFLDMOS has very high linear
Degree, high efficiency and high-gain.
In RFLDMOS numerous Particular crafts, because deep field oxygen isolates the oxide layer with longitudinal direction, device is separated at a distance
Source and drain terminal, effectively reduce its parasitic capacitance.The reduction RFLMDMOS of industry peer company exploitation（Radio frequency horizontal proliferation is brilliant
Body pipe）The method of parasitic capacitance is generally comprised：Deep field oxygen and thick intermetallic dielectric layer.Thick intermetallic dielectric layer is many due to existing
PECVD（Plasma enhanced chemical vapor deposition method）Silicon warp caused by technique and thickness, into membrane granule, cost etc. is asked
Topic（As shown in Figure 1）, thus, the problem of there is many technique volume productions, and when using the technique of deep field oxygen, due to amount of oxidation mistake
Greatly, cause stress to deteriorate, introduce crystal dislocation（As shown in Figure 2）.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of deep field oxygen isolation of radio frequency horizontal proliferation transistor zero defect
Growing method.By means of the invention it is also possible to meet the requirement of deep field oxygen isolation and can solve of the prior art because adopting
With caused by deep field oxygen technique the problems such as lattice dislocation.
In order to solve the above technical problems, the radio frequency horizontal proliferation transistor of the present invention（RFLMDMOS）Zero defect depth field oxygen every
From growing method, including step：
1）On silicon chip, groove is etched；
2）Oxidation processes are carried out to having fluted silicon chip surface, the first oxide layer is formed；
3）In the first oxidation layer surface, the first non-doped polysilicon layer is deposited；
4）Oxidation processes are carried out to the silicon chip surface that deposited the first non-doped polysilicon layer, polysilicon oxide layer is formed；
5）In groove, the second non-doped polysilicon layer is deposited, the seamless filled of groove is completed, and ensure at quarter only by returning
Have and there is un-doped polysilicon in groove；
6）Oxidation processes are carried out to the silicon chip surface that deposited the second non-doped polysilicon layer, make the undoped in groove many
Crystal silicon surface is oxidized isolation, then, silicon chip surface is planarized, so as to form deep field oxygen isolation area.
The step 1）In, the method for etching is dry etching；The CD of groove（Critical size）In Space/line（Between
Away from/line width）For 0.5~3.0, preferably 1.8/2.4（It is preferably 0.75）.
The step 2）In, the temperature of oxidation processes is 800~1200 DEG C, and the time of oxidation processes is small for 10 minutes~5
When；The thickness of first oxide layer is 500~2500 angstroms, preferably 2000 angstroms.
The step 3）In, the method for the deposition of polysilicon includes：Chemical vapour deposition technique etc.；The temperature of deposition is 500
~700 DEG C, the time of deposition is 5 minutes~5 hours；The thickness of first non-doped polysilicon layer is 1000~10000 angstroms, preferably
For 2500 angstroms.
The step 4）In, the temperature of oxidation processes is 800~1200 DEG C, and the time of oxidation processes is small for 10 minutes~5
When；The thickness of polysilicon oxide layer is 1000~20000 angstroms, preferably 6000 angstroms.
The step 5）In, the method for the deposition of polysilicon includes：Chemical vapour deposition technique etc.；The temperature of deposition is 500
~700 DEG C, the time of deposition is 5 minutes~5 hours；The thickness of second non-doped polysilicon layer is 1000~20000 angstroms, preferably
For 12000 angstroms；It is preferably that dry back is carved to return the method carved.
The step 6）In, the temperature of oxidation processes is 800~1200 DEG C, and the time of oxidation processes is small for 10 minutes~5
When；The thickness that un-doped polysilicon surface in groove is oxidized is 1000~20000 angstroms, preferably 6000 angstroms；Planarization
Method includes：Cmp（CMP）Method.
Using the method for the present invention, the requirement of deep field oxygen isolation can be met, device parasitic electric capacity is reduced；Simultaneously, it is ensured that
Silicon substrate is without because lattice dislocation caused by the introducing of deep field oxygen, it is ensured that the other specification of device is not deteriorated.
Brief description of the drawings
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is profile scanning Electronic Speculum (SEM) figure of current technique；
Fig. 2 is profile scanning Electronic Speculum (SEM) figure of current technique；Wherein, there are a large amount of Dislocation in the figure (brilliant
Case is wrong)；
Fig. 3 be it is deep plough groove etched after schematic diagram；
Fig. 4 is the schematic diagram after first thin oxidation；
Fig. 5 is the schematic diagram after first un-doped polysilicon filling；
Fig. 6 is the schematic diagram after un-doped polysilicon oxidation again；
Fig. 7 is un-doped polysilicon filling again and the schematic diagram after time quarter；
Fig. 8 is the schematic diagram after deep trench un-doped polysilicon surface oxidation and planarization；
Fig. 9 is silicon chip topography scan Electronic Speculum (SEM) figure of the method formation using the present invention.
Description of reference numerals is as follows in figure：
1 is silicon chip, and 2 be deep trench, and 3 be the first oxide layer, and 4 be the first non-doped polysilicon layer, and 5 be main separation layer, and 6 are
Second non-doped polysilicon layer, 7 be isolated area.
Embodiment
The radio frequency horizontal proliferation transistor of the present invention（RFLMDMOS）The growing method of zero defect depth field oxygen isolation, including step
Suddenly：
1）Using dry etching, in silicon chip 1（Silicon substrate）On, groove is etched, groove herein is deep trench 2（Such as Fig. 3
It is shown）；
Wherein, the Space/line of deep trench 2（Spacing/line width）Ratio is critically important, can use 0.5~3.0, general use
1.8/2.4（I.e. 0.75）, so ensure follow-up silicon warp in acceptable scope；
2）Oxidation processes are carried out to the surface of silicon chip 1 with deep trench 2, the first oxide layer 3 is formed（As shown in Figure 4）, with
For forming first isolation and repairing front layer etching injury；
Wherein, the temperature of oxidation processes is 800~1200 DEG C, and the time of oxidation processes is 10 minutes~5 hours；First oxygen
The thickness for changing layer 3 is 500~2500 angstroms, and preferably 2000 Izods are right.
3）By chemical vapour deposition technique etc. on the surface of the first oxide layer 3, the first non-doped polysilicon layer 4 is deposited（Such as
Shown in Fig. 5）；
Wherein, the temperature of deposition is 500~700 DEG C, and the time of deposition is 5 minutes~5 hours；First un-doped polysilicon
The thickness of layer 4 is 1000~10000 angstroms, and preferably 2500 Izods are right.
4）Oxidation processes are carried out to the surface of silicon chip 1 that deposited the first non-doped polysilicon layer 4, polysilicon oxide layer is formed
（As shown in Figure 6）, so as to form main separation layer 5；
Wherein, the temperature of oxidation processes is 800~1200 DEG C, and the time of oxidation processes is 10 minutes~5 hours；Polysilicon
The thickness of oxide layer is 1000~20000 angstroms, and preferably 6000 Izods are right.
5）Second non-doped polysilicon layer 6 is deposited in deep trench 2 by chemical vapour deposition technique etc., deep trench 2 is completed
It is seamless filled, and by dry back carve ensure there is un-doped polysilicon in only deep trench 2（As shown in Figure 7）；
Wherein, the temperature of deposition is 500~700 DEG C, and the time of deposition is 5 minutes~5 hours；Second un-doped polysilicon
The thickness of layer 6 is 1000~20000 angstroms, and preferably 12000 Izods are right；
6）Oxidation processes are carried out to the surface of silicon chip 1 that deposited the second non-doped polysilicon layer 6, it is ensured that make in deep trench 2
Un-doped polysilicon surface be oxidized isolation, then, using to cmp（CMP）The surface of method silicon chip 1 carries out flat
Change, finally into so as to form the integral isolated area 7 of bulk（Deep field oxygen isolation area）（As shown in Figure 8）.
Wherein, the temperature of oxidation processes is 800~1200 DEG C, and the time of oxidation processes is 10 minutes~5 hours；Deep trench
The oxidized thickness in interior un-doped polysilicon surface is 1000~20000 angstroms, and preferably 6000 Izods are right.
The present invention is rationalized the Primary Oxidation of silicon trench size and silicon substrate, drawn by the way of deep trench lateral oxidation
Enter follow-up polysilicon filling deep trench and the re-oxidation of polycrystalline silicon, finally complete deep-trench polysilicon filling and oxidation sealing
And planarization, ultimately form the bulk oxidation isolation area of low stress.Wherein, the silicon chip ultimately formed using the method for the present invention
Topography scan Electronic Speculum (SEM) figure, as shown in Figure 9.As shown in Figure 9, there is no lattice dislocation in figure.
Thus, the present invention can not only meet the requirement of deep field oxygen isolation, reduce device parasitic electric capacity, moreover it is possible to ensure silicon substrate
（Silicon chip）Without lattice dislocation caused by the introducing because of deep field oxygen, it is ensured that the other specification of device is not deteriorated.
Claims (13)
1. the growing method of the deep field oxygen isolation of a kind of radio frequency horizontal proliferation transistor zero defect, it is characterised in that including step：
1) on silicon chip, groove is etched, the forming region of deep field oxygen isolation area includes multiple grooves, the pass of the groove
Spacing/line width in key size is that the ratio of spacing/line width in 0.5~3.0, the critical size of the groove makes subsequent technique
Described in the warpage of silicon chip controlled；The silicon chip surface that the groove is formed outside the rear groove exposes；
2) oxidation processes are carried out to having fluted silicon chip surface, the first oxide layer is formed, in the shape of the deep field oxygen isolation area
Into region, the oxidation processing technique of first oxide layer is carried out from side and from top to the silicon between the groove simultaneously
Aoxidize and ensure that the silicon between the groove has residue, first oxide layer is used to form first isolation and repair front layer to carve
Deteriorate and hinder and reduce stress by retaining the silicon between the groove and prevent lattice dislocation defect from occurring；Described first
The thickness of oxide layer is 500~2500 angstroms；
3) in the first oxidation layer surface, the first non-doped polysilicon layer is deposited；
4) oxidation processes are carried out to the silicon chip surface that deposited the first non-doped polysilicon layer, forms polysilicon oxide layer；It is described
Polysilicon oxide layer forms main separation layer；
5) in groove, the second non-doped polysilicon layer is deposited, the seamless filled of groove is completed, and ensure only ditch quarter by returning
There is un-doped polysilicon in groove；
6) oxidation processes are carried out to the silicon chip surface that deposited the second non-doped polysilicon layer, makes the un-doped polysilicon in groove
Surface is oxidized isolation, then, silicon chip surface is planarized, so as to form deep field oxygen isolation area.
2. the method as described in claim 1, it is characterised in that：The step 1) in, the method for etching is dry etching.
3. method as claimed in claim 2, it is characterised in that：Spacing/line width in the critical size of the groove is 1.8/
2.4。
4. the method as described in claim 1, it is characterised in that：The step 2) in, the temperature of oxidation processes is 800~1200
DEG C, the time of oxidation processes is 10 minutes~5 hours.
5. method as claimed in claim 4, it is characterised in that：The thickness of first oxide layer is 2000 angstroms.
6. the method as described in claim 1, it is characterised in that：The step 3) in, the method for polysilicon deposition includes：Chemistry
Vapour deposition process；
The temperature of deposition is 500~700 DEG C, and the time of deposition is 5 minutes~5 hours；
The thickness of first non-doped polysilicon layer is 1000~10000 angstroms.
7. method as claimed in claim 6, it is characterised in that：The thickness of first non-doped polysilicon layer is 2500 angstroms.
8. the method as described in claim 1, it is characterised in that：The step 4) in, the temperature of oxidation processes is 800~1200
DEG C, the time of oxidation processes is 10 minutes~5 hours；
The thickness of polysilicon oxide layer is 1000~20000 angstroms.
9. method as claimed in claim 8, it is characterised in that：The thickness of the polysilicon oxide layer is 6000 angstroms.
10. the method as described in claim 1, it is characterised in that：The step 5) in, the method for polysilicon deposition includes：Change
Learn vapour deposition process；
The temperature of deposition is 500~700 DEG C, and the time of deposition is 5 minutes~5 hours；
The thickness of second non-doped polysilicon layer is 1000~20000 angstroms；
The method carved is returned to carve for dry back.
11. method as claimed in claim 10, it is characterised in that：The thickness of second non-doped polysilicon layer is 12000
Angstrom.
12. the method as described in claim 1, it is characterised in that：The step 6) in, the temperature of oxidation processes for 800~
1200 DEG C, the time of oxidation processes is 10 minutes~5 hours；
The thickness that un-doped polysilicon surface in groove is oxidized is 1000~20000 angstroms；
The method of planarization includes：Chemical mechanical milling method.
13. method as claimed in claim 12, it is characterised in that：What the un-doped polysilicon surface in the groove was oxidized
Thickness is 6000 angstroms.
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|---|---|---|---|---|
| CN1531057A (en) * | 2003-03-12 | 2004-09-22 | 矽统科技股份有限公司 | Method for producing shallow ridges separating structure (STI) |
| CN103011048A (en) * | 2011-09-26 | 2013-04-03 | 美格纳半导体有限公司 | Isolation structure, semiconductor device having the same, and method for fabricating the isolation structure |
| CN103035514A (en) * | 2012-05-16 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method for forming thick silicon oxide isolation layer in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN103050534A (en) * | 2012-08-20 | 2013-04-17 | 上海华虹Nec电子有限公司 | Structure and manufacture method of RFLDMOS (ratio frequency laterally diffused metal oxide semiconductor) thick field oxygen isolation medium layer |
| CN103137540A (en) * | 2011-11-29 | 2013-06-05 | 上海华虹Nec电子有限公司 | Manufacturing method of thick isolation dielectric medium layer structure of RFLDMOS |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8247297B2 (en) * | 2009-12-15 | 2012-08-21 | Alpha & Omega Semiconductor Inc. | Method of filling large deep trench with high quality oxide for semiconductor devices |
| IT1397603B1 (en) * | 2009-12-21 | 2013-01-16 | St Microelectronics Srl | INSULATION TRINCES FOR LAYER SEMICONDUCTORS. |
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- 2013-08-14 CN CN201310354097.1A patent/CN104377134B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531057A (en) * | 2003-03-12 | 2004-09-22 | 矽统科技股份有限公司 | Method for producing shallow ridges separating structure (STI) |
| CN103011048A (en) * | 2011-09-26 | 2013-04-03 | 美格纳半导体有限公司 | Isolation structure, semiconductor device having the same, and method for fabricating the isolation structure |
| CN103137540A (en) * | 2011-11-29 | 2013-06-05 | 上海华虹Nec电子有限公司 | Manufacturing method of thick isolation dielectric medium layer structure of RFLDMOS |
| CN103035514A (en) * | 2012-05-16 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method for forming thick silicon oxide isolation layer in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN103050534A (en) * | 2012-08-20 | 2013-04-17 | 上海华虹Nec电子有限公司 | Structure and manufacture method of RFLDMOS (ratio frequency laterally diffused metal oxide semiconductor) thick field oxygen isolation medium layer |
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