US20040072400A1 - Method of forming a shallow trench isolation structure - Google Patents
Method of forming a shallow trench isolation structure Download PDFInfo
- Publication number
- US20040072400A1 US20040072400A1 US10/270,348 US27034802A US2004072400A1 US 20040072400 A1 US20040072400 A1 US 20040072400A1 US 27034802 A US27034802 A US 27034802A US 2004072400 A1 US2004072400 A1 US 2004072400A1
- Authority
- US
- United States
- Prior art keywords
- oxide layer
- layer
- trench
- substrate
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Definitions
- the present invention relates in general to a semiconductor technology. More particularly, it relates to a method of forming a shallow trench isolation (STI) structure.
- STI shallow trench isolation
- An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions thereof and preventing carriers from penetrating the substrate to neighboring devices.
- LOCOS and shallow trench isolation manufacturing methods are the two most used methods.
- the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.
- FIG. 1 is a schematic cross-section showing a conventional shallow trench isolation structure.
- a pad oxide layer and a silicon nitride layer (not shown) are formed on a silicon substrate 10 .
- the silicon nitride layer and the pad oxide layer are patterned by lithography and etching, and a trench is then formed in the substrate 10 by etching using the silicon nitride layer as a mask.
- a liner oxide layer 14 is formed by thermal oxidation on the surface of the trench.
- Chemical vapor deposition (CVD) oxide layer is deposited and filled into the trench.
- the excess oxide layer over the silicon nitride layer is removed by chemical mechanical polishing (CMP) to complete the shallow trench isolation structure 16 .
- CMP chemical mechanical polishing
- the property of the element isolation structure 16 is similar to that of the pad oxide layer and liner oxide layer 14 , when etching liquid is used to remove pad oxide layer, the element isolation structure 16 is inevitably etched so that the liner oxide layer 14 at the top corner 20 of the trench develops a sharp edge, increasingly attracting the focus of the electric field, hence the the insulating properties of the top corner 20 degrades, resulting in abnormal element characteristics.
- the etching used for forming the trench in the substrate 10 and the thermally grown liner oxide layer 14 induce stresses into the substrate 10 .
- the stresses concentrate at the top corner 20 and bottom corner 22 of the trench, resulting in inducing leakage current.
- more operation time is required for growing liner oxide by thermal oxidation, thus reducing the throughput.
- typical semiconductor factories use batch furnaces for thermal oxidation, the thin film uniformity is varied, reducing the reliability of the devices.
- an object of the invention is to provide a method of forming a shallow trench isolation structure, wherein a liner oxide layer is formed by wet oxidation using single wafer process at high temperatures to obtain a rounder liner oxide layer at the top corner of the trench and increase the uniformity of the liner oxide layers in each wafer to be fabricated.
- Another object of the invention is to provide a method of forming a shallow trench isolation structure, wherein in-situ annealing is performed after the liner oxide growth to release stress and prevent dopant diffusion to the STI structure from the device region.
- the invention provides a method of forming a shallow trench isolation structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.
- the silicon oxide layer has a thickness of about 150 ⁇ 250 ⁇ and can be formed at about 1100 ⁇ 1200° C. using hydrogen and oxygen as reaction gases. Moreover, the flow rates of the hydrogen and oxygen are about 10 ⁇ 16 slm and 5 ⁇ 8 slm, respectively.
- the annealing is performed in an atmosphere of nitrogen or nitrous oxide at about 1100 ⁇ 1200° C. for 20 ⁇ 60 sec.
- the insulating layer is high density plasma oxide.
- FIG. 1 is a schematic cross-section showing a conventional shallow trench isolation structure
- FIGS. 2 a through 2 g are cross-sections showing a method of forming a shallow trench isolation structure according to the present invention.
- FIGS. 2 a through 2 g A preferred embodiment of the present invention is now described with reference to FIGS. 2 a through 2 g.
- a semiconductor substrate such as a silicon wafer 30 .
- a mask layer 35 is formed on the substrate 30 .
- the mask layer 35 preferably has a thickness of about 200 ⁇ 3500 ⁇ and can be a single layer or a plurality of layers.
- the mask layer 35 is preferably composed of a pad oxide layer 32 and a thicker silicon nitride layer 34 .
- the pad oxide layer 32 has a thickness of about 100 ⁇ and can be formed by thermal oxidation or conventional CVD, such as atmospheric pressure CVD (APCVD) and low pressure CVD (LPCVD).
- APCVD atmospheric pressure CVD
- LPCVD low pressure CVD
- the silicon nitride layer 34 overlying the pad oxide layer 32 has a thickness of about 1000 ⁇ 2000 ⁇ and can be formed by LPCVD using SiCl 2 H 2 and NH 3 as reaction source.
- a photoresist layer 36 is coated on the mask layer 35 .
- lithography is performed on the photoresist layer 36 to form an opening 37 inside.
- the opening 37 defines shallow trench isolation region.
- the photoresist layer 36 having the opening 37 is used as a mask to anisotropically etch the mask layer 35 , for example, reactive ion etching (RIE), to transfer the opening 37 pattern of the photoresist layer 36 to the mask layer 35 inside.
- RIE reactive ion etching
- suitable wet etching or ashing is performed to remove the photoresist layer 36 .
- anisotropic etching is performed using the mask layer 35 as an etch mask, for example, the RIE, etching silicon substrate 30 under the opening in the mask layer 35 to a predetermined depth, such as about 3000 ⁇ 6000 ⁇ , to form a trench 38 in the silicon substrate 30 .
- FIGS. 2 c to 2 d show the critical steps of the invention.
- a conformable silicon oxide layer 40 with a thickness of about 150 ⁇ 250 ⁇ grows on the surface of the trench 38 to serve as a liner oxide layer.
- the silicon oxide layer 40 is not formed by conventional thermal oxidation using a batch furnace, but is formed by wet oxidation using single wafer system.
- this single wafer process can be performed using Thermal Process Common Centura (TPCC), a deposition apparatus fabricated by APPLIED MATERIAL, using hydrogen and oxygen as reaction gases.
- TPCC Thermal Process Common Centura
- the flow rates of hydrogen and oxygen are 10 ⁇ 16 slm and 5 ⁇ 8 slm, respectively.
- Preferred flow rates of hydrogen and oxygen are 12 slm and 6 slm, respectively.
- the working pressure is about 7 ⁇ 12 Torr, and preferred pressure is 9 ⁇ 10 Torr.
- the growth time of the silicon oxide layer 40 is 60 ⁇ 70 sec.
- TPCC has a higher growth temperature (1000 ⁇ 1200° C.) than conventional thermal furnace (800 ⁇ 900° C.), a higher temperature raising rate, and a higher growth rate to decrease the process time.
- the growth temperature of the invention is 1150° C.
- the substrate 30 and the silicon oxide layer 40 are in-situ annealed 41 in an atmosphere of nitrogen (N 2 ) or nitrous oxide (N 2 O) for 20 ⁇ 60 sec.
- N 2 nitrogen
- N 2 O nitrous oxide
- in-situ here indicates that there is no breach in the chamber vacuum.
- in-situ annealing 41 is performed at the growth temperature mentioned above. That is, the annealing temperature is at 1100 ⁇ 1200° C. and the preferred annealing temperature is held at 1150° C.
- the first is to repair the rough interface between the trench 38 surface and the liner oxide layer 40 through silicon atoms from the substrate 30 completely bonding with the oxygen atoms from the liner oxide layer 40 to enhance the insulating properties of the liner oxide layer 40 .
- the second is to realize stresses formed at the top corner 38 a and bottom corner 38 b of the trench 38 during etching trench 38 and growing liner oxide layer 40 to prevent electric field concentration while devices are operating.
- the third is to diffuse nitrogen atoms into the silicon oxide layer 40 and bond with silicon atoms and oxygen atoms therein.
- the Si—O—N bonds can barrier the dopant in the device region (not shown), diffusing into the STI structure in subsequent process to increase the reliability of the devices.
- the annealing 41 may form a thin sealing layer 39 , such as silicon oxynitride (SiON), over the liner oxide layer 40 to enhance the diffusion barrier effect.
- an insulating layer 42 is formed over the mask layer 35 and completely fills the trench 38 .
- the insulating layer 42 can be doped or undoped silicon oxide.
- Some doped silicon oxides include phosphor-silicate glass (PSG), boro-silicate glass (BSG), phosphorus boron silicate glass (BPSG), and the like.
- Some undoped silicon oxides include thermal tetraethyl orthosilicate (TEOS) and high-density plasma (HDP) silicon oxides.
- the preferred insulating layer 42 is HDP silicon oxide formed by HDPCVD.
- annealing or rapid thermal process is performed to densitize the insulating layer 42 .
- the excess insulating layer 42 over the mask layer 35 is removed to form shallow trench isolation (STI) structure 42 a .
- the method for removing the excess insulating layer 44 is, for example, CMP.
- the mask layer 35 is removed.
- the method of removing the silicon nitride layer 34 for example, is soaking with hot H 3 PO 4
- the method of removing pad oxide layer 32 for example, is soaking with HF liquid.
- part of STI structure 42 a will be removed at the same time to form recess 43 at the top corner 38 a of the STI structure 42 a .
- the recess effect can be minimized to avoid leakage current induced.
- the liner oxide layer of the invention is formed by single wafer process. Accordingly, it can increase the uniformity of the liner oxide layers in each wafer to be fabricated. Moreover, according to the invention, the throughput can be increased due to the shorter process time required. In addition, the step of in-situ annealing of the invention can increase the quality of the line oxide to ensure the insulating properties of the STI structure.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
- 1. Field of the Invention
- The present invention relates in general to a semiconductor technology. More particularly, it relates to a method of forming a shallow trench isolation (STI) structure.
- 2. Description of the Related Art
- An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions thereof and preventing carriers from penetrating the substrate to neighboring devices.
- Among different element isolation techniques, LOCOS and shallow trench isolation manufacturing methods are the two most used methods. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.
- FIG. 1 is a schematic cross-section showing a conventional shallow trench isolation structure. In FIG. 1, a pad oxide layer and a silicon nitride layer (not shown) are formed on a
silicon substrate 10. The silicon nitride layer and the pad oxide layer are patterned by lithography and etching, and a trench is then formed in thesubstrate 10 by etching using the silicon nitride layer as a mask. Aliner oxide layer 14 is formed by thermal oxidation on the surface of the trench. Chemical vapor deposition (CVD) oxide layer is deposited and filled into the trench. The excess oxide layer over the silicon nitride layer is removed by chemical mechanical polishing (CMP) to complete the shallowtrench isolation structure 16. The silicon nitride layer and the pad oxide layer are then removed. - Because the property of the
element isolation structure 16 is similar to that of the pad oxide layer andliner oxide layer 14, when etching liquid is used to remove pad oxide layer, theelement isolation structure 16 is inevitably etched so that theliner oxide layer 14 at thetop corner 20 of the trench develops a sharp edge, increasingly attracting the focus of the electric field, hence the the insulating properties of thetop corner 20 degrades, resulting in abnormal element characteristics. - Moreover, the etching used for forming the trench in the
substrate 10 and the thermally grownliner oxide layer 14 induce stresses into thesubstrate 10. For example, the stresses concentrate at thetop corner 20 andbottom corner 22 of the trench, resulting in inducing leakage current. In addition, more operation time is required for growing liner oxide by thermal oxidation, thus reducing the throughput. Moreover, since typical semiconductor factories use batch furnaces for thermal oxidation, the thin film uniformity is varied, reducing the reliability of the devices. - Accordingly, an object of the invention is to provide a method of forming a shallow trench isolation structure, wherein a liner oxide layer is formed by wet oxidation using single wafer process at high temperatures to obtain a rounder liner oxide layer at the top corner of the trench and increase the uniformity of the liner oxide layers in each wafer to be fabricated.
- Another object of the invention is to provide a method of forming a shallow trench isolation structure, wherein in-situ annealing is performed after the liner oxide growth to release stress and prevent dopant diffusion to the STI structure from the device region.
- To achieve these and other advantages, the invention provides a method of forming a shallow trench isolation structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.
- The silicon oxide layer has a thickness of about 150˜250 Å and can be formed at about 1100˜1200° C. using hydrogen and oxygen as reaction gases. Moreover, the flow rates of the hydrogen and oxygen are about 10˜16 slm and 5˜8 slm, respectively.
- Moreover, the annealing is performed in an atmosphere of nitrogen or nitrous oxide at about 1100˜1200° C. for 20˜60 sec. The insulating layer is high density plasma oxide.
- The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:
- FIG. 1 is a schematic cross-section showing a conventional shallow trench isolation structure; and
- FIGS. 2a through 2 g are cross-sections showing a method of forming a shallow trench isolation structure according to the present invention.
- A preferred embodiment of the present invention is now described with reference to FIGS. 2a through 2 g.
- First, in FIG. 2a, a semiconductor substrate, such as a
silicon wafer 30, is provided. Amask layer 35 is formed on thesubstrate 30. Themask layer 35 preferably has a thickness of about 200˜3500 Å and can be a single layer or a plurality of layers. As shown in FIG. 1, themask layer 35 is preferably composed of apad oxide layer 32 and a thickersilicon nitride layer 34. In this invention, thepad oxide layer 32 has a thickness of about 100 Å and can be formed by thermal oxidation or conventional CVD, such as atmospheric pressure CVD (APCVD) and low pressure CVD (LPCVD). Thesilicon nitride layer 34 overlying thepad oxide layer 32 has a thickness of about 1000˜2000 Å and can be formed by LPCVD using SiCl2H2 and NH3 as reaction source. Next, aphotoresist layer 36 is coated on themask layer 35. Thereafter, lithography is performed on thephotoresist layer 36 to form anopening 37 inside. Theopening 37 defines shallow trench isolation region. - Subsequently, in FIG. 2b, the
photoresist layer 36 having theopening 37 is used as a mask to anisotropically etch themask layer 35, for example, reactive ion etching (RIE), to transfer the opening 37 pattern of thephotoresist layer 36 to themask layer 35 inside. Next, suitable wet etching or ashing is performed to remove thephotoresist layer 36. Next, anisotropic etching is performed using themask layer 35 as an etch mask, for example, the RIE, etchingsilicon substrate 30 under the opening in themask layer 35 to a predetermined depth, such as about 3000˜6000 Å, to form atrench 38 in thesilicon substrate 30. - Next, FIGS. 2c to 2 d show the critical steps of the invention. In FIG. 2c, a conformable
silicon oxide layer 40 with a thickness of about 150˜250 Å grows on the surface of thetrench 38 to serve as a liner oxide layer. In this invention, in order to obtain a rounder portion of thesilicon oxide layer 40 at thetop corner 38 a of thetrench 38, thesilicon oxide layer 40 is not formed by conventional thermal oxidation using a batch furnace, but is formed by wet oxidation using single wafer system. For example, this single wafer process can be performed using Thermal Process Common Centura (TPCC), a deposition apparatus fabricated by APPLIED MATERIAL, using hydrogen and oxygen as reaction gases. The flow rates of hydrogen and oxygen are 10˜16 slm and 5˜8 slm, respectively. Preferred flow rates of hydrogen and oxygen are 12 slm and 6 slm, respectively. The working pressure is about 7˜12 Torr, and preferred pressure is 9˜10 Torr. The growth time of thesilicon oxide layer 40 is 60˜70 sec. In addition, TPCC has a higher growth temperature (1000˜1200° C.) than conventional thermal furnace (800˜900° C.), a higher temperature raising rate, and a higher growth rate to decrease the process time. Preferably, the growth temperature of the invention is 1150° C. - Next, in FIG. 2d, the
substrate 30 and thesilicon oxide layer 40 are in-situ annealed 41 in an atmosphere of nitrogen (N2) or nitrous oxide (N2O) for 20˜60 sec. In-situ here indicates that there is no breach in the chamber vacuum. In this invention, in-situ annealing 41 is performed at the growth temperature mentioned above. That is, the annealing temperature is at 1100˜1200° C. and the preferred annealing temperature is held at 1150° C. Here, there are three purposes for in-situ annealing 41 in an atmosphere of N2 or N2O after growing theliner oxide layer 40. The first is to repair the rough interface between thetrench 38 surface and theliner oxide layer 40 through silicon atoms from thesubstrate 30 completely bonding with the oxygen atoms from theliner oxide layer 40 to enhance the insulating properties of theliner oxide layer 40. The second is to realize stresses formed at thetop corner 38 a andbottom corner 38 b of thetrench 38 duringetching trench 38 and growingliner oxide layer 40 to prevent electric field concentration while devices are operating. The third is to diffuse nitrogen atoms into thesilicon oxide layer 40 and bond with silicon atoms and oxygen atoms therein. The Si—O—N bonds can barrier the dopant in the device region (not shown), diffusing into the STI structure in subsequent process to increase the reliability of the devices. In addition, theannealing 41 may form athin sealing layer 39, such as silicon oxynitride (SiON), over theliner oxide layer 40 to enhance the diffusion barrier effect. - Next, in FIG. 2e, an insulating
layer 42 is formed over themask layer 35 and completely fills thetrench 38. For example, the insulatinglayer 42 can be doped or undoped silicon oxide. Some doped silicon oxides include phosphor-silicate glass (PSG), boro-silicate glass (BSG), phosphorus boron silicate glass (BPSG), and the like. Some undoped silicon oxides include thermal tetraethyl orthosilicate (TEOS) and high-density plasma (HDP) silicon oxides. In this invention, the preferred insulatinglayer 42 is HDP silicon oxide formed by HDPCVD. - Subsequently, annealing or rapid thermal process (RTP) is performed to densitize the insulating
layer 42. - Next, in FIG. 2f, the excess insulating
layer 42 over themask layer 35 is removed to form shallow trench isolation (STI)structure 42 a. The method for removing the excess insulating layer 44 is, for example, CMP. - Finally, in FIG. 2g, the
mask layer 35 is removed. The method of removing thesilicon nitride layer 34, for example, is soaking with hot H3PO4, and the method of removingpad oxide layer 32, for example, is soaking with HF liquid. In addition, when removingpad oxide layer 32, part ofSTI structure 42 a will be removed at the same time to formrecess 43 at thetop corner 38 a of theSTI structure 42 a. However, as mentioned above, since the portion of theliner oxide layer 40 at thetop corner 38 a is rounder, the recess effect can be minimized to avoid leakage current induced. - Compared with the prior art, the liner oxide layer of the invention is formed by single wafer process. Accordingly, it can increase the uniformity of the liner oxide layers in each wafer to be fabricated. Moreover, according to the invention, the throughput can be increased due to the shorter process time required. In addition, the step of in-situ annealing of the invention can increase the quality of the line oxide to ensure the insulating properties of the STI structure.
- The foregoing description has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/270,348 US6727160B1 (en) | 2002-10-15 | 2002-10-15 | Method of forming a shallow trench isolation structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/270,348 US6727160B1 (en) | 2002-10-15 | 2002-10-15 | Method of forming a shallow trench isolation structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040072400A1 true US20040072400A1 (en) | 2004-04-15 |
US6727160B1 US6727160B1 (en) | 2004-04-27 |
Family
ID=32068953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/270,348 Expired - Lifetime US6727160B1 (en) | 2002-10-15 | 2002-10-15 | Method of forming a shallow trench isolation structure |
Country Status (1)
Country | Link |
---|---|
US (1) | US6727160B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080070420A1 (en) * | 2006-09-18 | 2008-03-20 | Lee Joo-Hyun | Method of fabricating image sensor |
CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
CN113972257A (en) * | 2020-07-23 | 2022-01-25 | 华邦电子股份有限公司 | Semiconductor structure and forming method thereof |
CN116525536A (en) * | 2023-06-30 | 2023-08-01 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure for semiconductor device and preparation method thereof |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100672753B1 (en) * | 2003-07-24 | 2007-01-22 | 주식회사 하이닉스반도체 | Method for preventing electron trapping of trench isolation |
US20060054964A1 (en) * | 2004-09-15 | 2006-03-16 | Mark Isler | Semiconductor device and method for fabricating a region thereon |
KR20100106127A (en) * | 2009-03-23 | 2010-10-01 | 삼성전자주식회사 | Method of fabricating of semiconductor device |
KR20220145195A (en) * | 2021-04-21 | 2022-10-28 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780346A (en) * | 1996-12-31 | 1998-07-14 | Intel Corporation | N2 O nitrided-oxide trench sidewalls and method of making isolation structure |
US6140251A (en) * | 1997-12-10 | 2000-10-31 | Intel Corporation | Method of processing a substrate |
US6051478A (en) * | 1997-12-18 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of enhancing trench edge oxide quality |
US6387777B1 (en) * | 1998-09-02 | 2002-05-14 | Kelly T. Hurley | Variable temperature LOCOS process |
US6583025B2 (en) * | 2000-07-10 | 2003-06-24 | Samsung Electronics Co., Ltd. | Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace |
US6503815B1 (en) * | 2001-08-03 | 2003-01-07 | Macronix International Co., Ltd. | Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation |
-
2002
- 2002-10-15 US US10/270,348 patent/US6727160B1/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080070420A1 (en) * | 2006-09-18 | 2008-03-20 | Lee Joo-Hyun | Method of fabricating image sensor |
CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
CN113972257A (en) * | 2020-07-23 | 2022-01-25 | 华邦电子股份有限公司 | Semiconductor structure and forming method thereof |
CN116525536A (en) * | 2023-06-30 | 2023-08-01 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure for semiconductor device and preparation method thereof |
Also Published As
Publication number | Publication date |
---|---|
US6727160B1 (en) | 2004-04-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7442620B2 (en) | Methods for forming a trench isolation structure with rounded corners in a silicon substrate | |
US6214698B1 (en) | Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer | |
US6191004B1 (en) | Method of fabricating shallow trench isolation using high density plasma CVD | |
US6949447B2 (en) | Method for fabricating isolation layer in semiconductor device | |
US20100140681A1 (en) | Semiconductor device and method of manufacturing therefor | |
US6051478A (en) | Method of enhancing trench edge oxide quality | |
US6777336B2 (en) | Method of forming a shallow trench isolation structure | |
US20040005781A1 (en) | HDP SRO liner for beyond 0.18 um STI gap-fill | |
US20040169005A1 (en) | Methods for forming a thin film on an integrated circuit including soft baking a silicon glass film | |
US6727160B1 (en) | Method of forming a shallow trench isolation structure | |
JP2001085511A (en) | Element isolation method | |
KR20010008775A (en) | Method for shallow trench isolation | |
US6794266B2 (en) | Method for forming a trench isolation structure | |
JP2005260177A (en) | Manufacturing method of semiconductor device | |
US7183173B2 (en) | Method for forming isolation film in semiconductor device | |
US6784075B2 (en) | Method of forming shallow trench isolation with silicon oxynitride barrier film | |
US6503815B1 (en) | Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation | |
US6013559A (en) | Method of forming trench isolation | |
JP2953447B2 (en) | Manufacturing method of groove-separated semiconductor device | |
JP2000100926A (en) | Semiconductor device and manufacture thereof | |
US6624041B2 (en) | Method for forming trench type isolation film using annealing | |
KR100596277B1 (en) | Semiconductor device and method of manufacturing dielectric layer thereof | |
KR100492790B1 (en) | Device isolation insulating film formation method of semiconductor device | |
US20030194870A1 (en) | Method for forming sidewall oxide layer of shallow trench isolation with reduced stress and encroachment | |
JP2002057211A (en) | Method for manufacturing semiconductor device having trench element isolation region |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SILICON INTEGRATED SYSTEMS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, CHIAN-KAI;CHENG, FUNG-HSU;LI, JUI-PING;REEL/FRAME:013388/0274;SIGNING DATES FROM 20020918 TO 20020919 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SILICON INTEGRATED SYSTEMS CORP.;REEL/FRAME:015621/0932 Effective date: 20050126 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |