CN1502123A - 机械加固的高度多孔低介电常数薄膜 - Google Patents
机械加固的高度多孔低介电常数薄膜 Download PDFInfo
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- CN1502123A CN1502123A CNA018211798A CN01821179A CN1502123A CN 1502123 A CN1502123 A CN 1502123A CN A018211798 A CNA018211798 A CN A018211798A CN 01821179 A CN01821179 A CN 01821179A CN 1502123 A CN1502123 A CN 1502123A
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一种多孔介质,诸如低介电常数薄膜,可以被制成聚集材料来在提供一个暂时增加的机械强度。这可以通过,例如多孔介质的前序调整处理实现。通过向多孔介质的空隙组分引入辅助成分,机械特性被暂时提高以便使多孔薄膜具有类似于更坚硬的薄膜的机械特性。根据本发明的方法允许对Cu大马士革互连技术中的高度多孔夹层介电质(ILD)的有效处理。一旦处理操作诸如要求比由多孔薄膜单独提供的机械强度大的机械强度的Cu化学机械抛光(CMP)完成之后,可以通过诸如替代或者溶解的方法村除去辅助成分。
Description
技术领域
本发明一般涉及微电子结构和制造方法,并且更具体地涉及构造电气绝缘结构和具有低介电常数的材料。
背景技术
半导体制造技术的进步导致了具有多层互连的集成电路的发展。在此类集成电路中,在一个互连层上的构图的导电材料通过诸如二氧化硅薄膜与在另一个互连层上构图的导电材料电气绝缘。
无论导电材料位于一个层或者多个层上,具有由绝缘材料隔开的构图的导电材料的结果是产生不希望的电容。在微电子设备上由绝缘材料绝缘的构图的导电材料,或者更简单地,互连之间产生的寄生电容将导致诸如RC延迟、功率耗散、以及电容性耦合信号,也就是公知的串音(cross talk)。
减小互连之间不希望的电容的一个方法是增加它们之间的距离。互连之间增加的间隔具有诸如使要求的面积的增加和相应的制造成本的升高的不利结果。另一个减小互连之间不希望的电容的方法是使用具有更低的介电常数的绝缘材料。
需要一种在构图的导体之间提供低的寄生电容的结构,以及制造此结构的方法。
附图说明
图1-3表示现有技术并且图4-10表示本发明的示范例。图1-10表示了介电层的横截面图,但是,为了清晰并且为了使半导体制造领域的技术人员识别,这些示意图中没有包括诸如形成晶体管和二极管的其它层。
图1是表示根据现有技术的方法在具有第一和第二层的复合夹层介电质上形成双大马士革开口的衬底经部分处理后的横截面示意图。
图2是表示表示根据现有技术的方法在具有第一、第二和第三层的复合夹层介电质上形成双大马士革开口的衬底经部分处理后的横截面示意图。
图3是表示根据现有技术的方法在具有第一、第二、第三、第四和第五层的复合夹层介电质上形成双大马士革开口的衬底经部分处理后的横截面示意图。
图4是表示包括具有第一介电常数的第一介电层和更厚的具有第二介电材料的第二介电层的衬底经部分处理后的横截面示意图,第二介电层的特征在于它的相对较高水平的孔隙度。
图5是表示图4所示的结构在第二介电层已经被处理增加孔隙度并且因此减小其介电常数后的横截面示意图。
图6是表示图5所示的结构在第二次介电层已经被处理以便将填充材料引入到第二介电层的孔中后的横截面示意图。
图7是表示图6所示的结构在第一和第二介电层已经被腐蚀来形成双大马士革开口后的横截面示意图。
图8是表示图7所示的结构在Cu势垒层和籽晶层已经被形成、Cu层已经被沉积并且通过化学机械抛光消除多余的Cu之后的横截面示意图。
图9是表示图8所示的结构在填充材料已经被从第二介电层的孔中除去后的横截面示意图。
图10是表示图9所示的结构在已经将Cu扩散势垒沉积在第二介电层和Cu互连线的暴露部分上的横截面示意图。
图11是表示根据本发明的处理的流程图。
图12是表示根据本发明的一个可选处理的流程图。
具体实施方式
下面描述暂时机械加固夹层介电结构和制造此类结构的方法。此类暂时机械加固夹层介电结构被至少用于制造具有高度多孔低k夹层介电质的集成电路。在下面的描述中,为了便于理解本发明,提供了许多具体的细节。但是,很显然,对于本领域的技术人员和从此公开受益的人来说,本发明可以使用与此处这些具体描述不同的装置、组成和工处理实现。
此处指的“一个实施例”、“实施例”或者类似形式表示与实施例相关的特定特征、结构或特性被包括在本发明的至少一个实施例中。因此,此处出现的此类短语或者形式不必参照同一个实施例。并且,可以在一个或多个实施例中以任何合适的方式组合各种特定的特征、结构和特性。
术语芯片、集成电路、单块集成电路装置、半导体装置和微电子设备在此领域通常被互换使用。正如它们通常在本领域是被理解的,本发明适用于上述全部情况。
术语接点和过孔,都涉及用于不同互连层的导体的电气连接的结构。这些术语有时在本领域被使用来描述在其中完成结构的绝缘体上的开口和整个结构本身。对于本发明的公开,接点和过孔指的是整个结构。
表述低介电常数材料,指的是具有小于二氧化硅的低介电常数的材料。例如,有机聚合物、非晶体氟化碳、微化石、包含有机聚合物的硅基绝缘体、掺杂硅的氧化物的碳以及具有小于二氧化硅的低介电常数的掺杂硅的氧化物的氟。
字母k通常被使用来指介电常数。类似地,术语高k和低k在该领域被用来分别指高介电常数和低介电常数,其中高表示大于二氧化硅的介电常数,低表示小于二氧化硅的介电常数。
术语夹层介电质在本领域被理解为指的是在一个给定的互联层的互连线之间沉积的介电材料。即,在邻近的互连线之间而不是在这些互连线的垂直上方或垂直下方发现夹层介电质。
此处使用的术语垂直表示基本垂直于衬底表面。
通过互连线看见的寄生电容是到另一个导体的距离和在其间的材料的介电常数的函数。然而,增加互连线间的间隔增加了物理尺寸,因此增加了集成电路的成本。因此为了制造在互连线之间具有低的寄生电容的集成电路,希望使用具有低介电常数的绝缘体将导体彼此绝缘。
如上所述,一种减小寄生电容的不利影响的方法是在前面的微电子产品(例如:集成电路)中使用低k材料作为绝缘体。为了获得低介电常数,可以使用具有低介电常数的材料和/或向薄膜引入多孔。通过增加薄膜空隙组分,也被称作孔隙度,可以降低材料的热机械特性。在Cu大马士革互联结构上处理集成高度多孔夹层介电质膜(ILD)具有很高的挑战性。结构控制是具有多孔材料的集成电路(IC)制造处理的一个很重要的方面。本发明的示范例包括将高度多孔材料集成到Cu大马士革互连结构上的处理。
可以通过一些公知的方法产生中度多孔(毫微多孔)。例如,此类多孔薄膜可以设计为具有张开或密闭孔结构的气凝胶/干凝胶(溶胶-凝胶、放样处理、CVD等)。在此类薄膜中,可以通过选择前体和调节工艺来调制孔道半径和空隙组分。由于随着孔隙率的增加,薄膜的机械强度有降低的趋势,诸如电子束,或UV泛光曝光已经被使用来增加薄膜的机械强度(诸如硬度/模数或者破裂韧度)。但是,这些处理会通过增加薄膜密度或者低k材料的交联范围导致薄膜的介电常数退化(即:增加介电常数)。因此,高度多孔薄膜不会通过这些处理感到明显的强度的增加。
根据本发明,多孔薄膜可以被制成聚集材料来提供暂时的增加的机械强度。这可以通过例如对多孔介质的预先调整处理来实现。通过置换空隙组分中的辅助成分,暂时改进机械特性以便使多孔薄膜具有类似于坚硬的多的薄膜的机械特性。一旦完成了诸如要求比由多孔薄膜独自提供的机械强度大的Cu CMP工艺,可以通过诸如替代或者溶解来出去辅助成分(也被称作置换阶段、或者第二阶段)。
除去辅助成分保证了保持ILD薄膜的低介电常数的目的。根据选择的材料的类型,可以以多种方式实现除去。第二阶段除去可以通过诸如使用可互溶的成分(溶解后蒸发)除去或者使用诸如用在三元线圈恢复中的替代技术除去。应该避免易变辅助成分的高温分解或热分解除非温度足够的低以便不会对暴露的铜线产生影响。
图1-3表示现有技术的组合低k介电常数和被通常用来形成集成电路上的铜互连线的双大马士革开口的各种方法。更具体地,图1表示典型地由诸如SiN材料形成的腐蚀阻止层102。腐蚀阻止层102覆盖一个低的互联层。较厚的介电层104覆盖腐蚀阻止层102并且具有比腐蚀阻止层102低的介电常数。在图1的例子中,介电层102是掺杂氧的碳。双大马士革结构106a,106b在层102,104中形成。双大马士革结构包括一个沟道部分106a和过孔开口部分106b。图2表示一个可选的现有技术的结构,其中介电层104是自旋聚合物或者高度多孔材料而不是图1中的掺杂氧的碳,并且另一个介电层110被用来提供另外的机械强度来构成机械强度弱于掺杂氧的碳的自旋聚合物或者高度多孔材料的使用。图3表示另一个可选时时列,类似于图2,但是包括一个中间腐蚀阻止层112。所有这些现有技术方法在提供非常低的介电常数和宜于制造方面都一个或者多个不足。
图4-10表示了本发明的一个示范例,更具体地,图4表示了在衬底(未示出)上形成的第一个介电层102,第一个介电层102通常是诸如SiDC、SiC或SiN材料。选择这些材料是因为他们易于有选择地根据随后形成的覆盖层进行腐蚀,并且因为他们有效地阻挡铜原子的扩散,通常,衬底是一个在其上已经执行了其它制造工艺以便形成各种电气元件,包括但不限于晶体管和导电互连的晶片。但是,由于这些其它结构和处理操作(a)在本领域是被公知的,并且(b)与本发明无关,它们将不被进一步地讨论,接着在第一介电层102上形成第二介电层402,第二介电层的特征在于具有特定的在1.8到2.6范围内的低介电常数。本领域的技术人员知道该范围是一个近似值,并且由于包含在用来形成这些介电层的制造过程的误差会发生一些变化,第二介电层402可以通过沉积中度多孔SiO2或者聚合物来形成。
基于氧的多孔薄膜可以通过溶胶-凝胶化学形成,例如,形成基于氧的多孔薄膜的过程可以开始在极性溶剂,诸如,酒精中溶解RSi(OR’)3,其中R可以是H,CH3,或者其它烷基组,R’可以是CH3,CH2CH3或者其它烷基组,连同触媒(例如酸)加入水开始形成Si-O-Si带的凝结反应,酒精作为副产品。R组在此处理期间附着在Si上,其后形成一个碳源,如果R是一个长链烷基,一些碳键就会在形成CO2和H2O的热处理期间断裂。二氧化碳和水的去除导致孔的形成,形成孔受到溶剂或者溶剂混合气压、R组成分和结构、牺牲添加剂(例如,有机成分可以在热处理期间连同R组燃烧)、影响凝结力的反应添加剂和PH的影响。氨的老化还可以通过影响凝结力来影响薄膜的特性。
倍半氧化硅化学是溶胶-凝胶化学的延伸。在此方法形成基于氧的多孔薄膜的过程中,起始材料是(RsiO1.5)n,其是看起来类似RSi(OR’)3的低聚物的笼结构。热处理造成结构的进一步凝结,因此薄膜特性也发生变化。
关于基于聚合物的基多孔薄膜,使用通过成对垫片连接的苯环聚合物(即,碳-碳双键或三键)。热处理在聚合物的终端和中间(即,交叉结合)造成进一步聚合来为增厚的薄膜提供更好的机械特性,通常通过溶解蒸发(即,溶剂混合物的气压)和使用表面活性剂为该薄膜实现多孔。
图5表示图4所示的结构在第二介电层402已经通过硫化或老化处理转换成介电层403后的结构。介电层403具有在1.5到2.2范围内的介电常数。本领域的技术人员可以认识到该范围是近似的并且由于包含在此类工艺中的误差会发生一些变化。
关于硫化或老化,用于处理自旋聚合物,溶胶-凝胶和毫微多孔玻璃的工艺是不同的。下表提供了用于增加已经在晶片上形成的聚合物、溶胶-凝胶和毫微多孔玻璃的多孔性的一般方法的一些例子。
表1
聚合物: 激冷电镀 20℃~25℃,60秒 |
旋涂 2-4kRPM,23C,40%RH |
加热板烘烤 200℃~235℃,N2环境(控制O2≤100ppm),90秒 |
旋转烘烤 325℃,90秒 |
旋转烘烤 460℃,300℃,N2环境 |
激冷电镀 20℃~25℃,60秒 |
溶胶-凝胶:旋涂 2-3kRPM,45秒,23C,40%RH |
预烘烤 80℃,空气环境,90秒 |
预等待 N2环境,60秒 |
软烘烤 200℃,N2环境,180秒 |
后等待 N2环境,60秒 |
预硫化 400℃,300秒,电镀 |
激冷电镀 20℃~25℃,60秒 |
毫微玻璃: 旋涂 2-3kRPM,45秒,23C,40%RH |
冻结 NH3处理 |
烘烤 150℃,N2环境,60秒 |
激冷电镀 20℃~25℃,60秒 |
最终的硫化可以使用诸如熔炉硫化(400℃温度,N2环境,30分钟)或者加热板硫化步骤(420℃~460℃,3~5分钟)
图6表示了图5所示的结构在介电层403被修整成介电层404后的结构。介电层404是通过为介电层403的孔填充一个或多种为聚集介电层404提供机械强度的材料形成的。该机械加固(也被称作机械加强)最好是一个基本上可逆的处理。虽然,额外的机械强度利于介电层404承受随后的处理操作,但是填充材料试图增加介电层404的介电常数,因此对期望的介电特性造成不利影响。应该理解对于“填充”操作,不是每个孔都要被填充,或者孔不必完全填充。即,一些孔可以被完全填充,一些孔可以被部分填充,一些孔根本不必要填充。重要的是要有足够的“填充”来提供承受随后处理操作所需的机械强度。可以通过包括但不限于浸入在液体和填充材料地自旋将填充材料引入到孔中。在此示范例中,随后的处理操作包括化学机械剖光、腐蚀和电镀。本发明不对再机械加强随后执行的操作的种类。
图7表示了图6的结构在半导体制造领域被公知的影印和腐蚀操作后被操作来产生沟道106a和过孔106b。可以从图7中看出,沟道106a形成在介电层404上,而过孔开口106b穿过介电层402和腐蚀阻止层102形成。
图8表示了图7的结构在形成铜扩散阻势垒层406和铜互连线408的处理操作后的结构。扩散势垒形成在包括介电层404和沟道106a的表面以及过孔开孔106b的整个表面的整个衬底上。如半导体制造领域公知的,虽然钽和氮化钽是优选材料,铜扩散势垒还可以包括各种材料。并且如所公知的,通常在势垒层406上形成籽晶层,接着在势垒层上电镀铜直到过孔和沟被填充。当然,接着通常通过化学机械抛光除去介电层404的顶面上的多余的铜层和势垒层材料。图8的结构是通过形成势垒层、籽晶层、铜层和通过化学机械抛光除去衬底顶面的多余的铜和势垒材料形成的。根据本发明的机械加固的介电层,诸如介电层404与金属互连线结构的双大马士革形式匹配。
图9表示了图8所示的结构在进一步将介电层404返回其先前的介电层403的处理后的结构。这些操作试图从介电层403的孔中除去全部或者大部分填充材料。根据填充物的成分和介电层403的组成,可以通过溶解和蒸发,或者替代,或者高温分解除去填充材料。
如上所述,填充物可以通过多种工艺实现。在涉及溶解的除去工艺中,在多孔薄膜和填充物之间的需要具有高对比的溶解性。在一个实施例中,多孔薄膜主要由无机材料组成而填充物为有机的。填充物称为有选择地通过溶剂或水溶液除去的目标溶质。多孔薄膜可以相对不活泼,并且填充物可以是非极性有机材料诸如负抗蚀剂(例如,环化聚异戊二烯聚合物)、正抗蚀剂(例如,酚醛清漆树脂)或者RELACS(日本东京东芝公司的一种商用树脂)。对于负抗蚀剂(不需要光敏剂),可以使用有机萃取剂来粉碎填充物。这些萃取剂可以是基于苯酚的低苯酚或者自由苯酚有机萃取剂。对于作为填充物的正抗蚀剂(例如,不需要光敏材料的便宜的树脂)或者RELACS,可以使用诸如四甲基铵氢氧化物或者乙酸乙酯,可以通过诸如但不限于此的苯、二甲苯、甲苯和IPA溶剂除去其它有机填充物材料。在填充物除去的无水工艺中,使用SO3处理有机抗蚀剂化学改变材料并且使填充物水溶解。在另一工艺中,可以使用氧萃取剂。即,可以使用湿无机溶解诸如例如加热溶解H2SO4和氧化剂诸如H2O2、臭氧或者铵过(二)硫酸盐来除去填充物。在另一个方法中,称作减缩工艺,可以使用或者不使用低频RF等离子发光放电或者微波等离子放电来除去填充物。使用H2、H2/N2、NH3气体(具有可能的较低含量的O2和碳氟化合物)可以便于除去填充物而不腐蚀多孔ILD材料。可以通过低能量RF等离子使室温低于通常后端处理温度实现地温减缩而不管其直接照射、间接照射或者余辉。对于符合标准后端处理温度的相关温度,可以使用直线减缩。在去除填充物的等离子技术中,可以使用H2、H2/N2、NH3等离子放电或者微波放电有选择的除去填充物而不腐蚀多孔ILD材料。在去除填充物的毛细替代方法中,可以使用超临界流体或者表面活性合成流体从ILD材料的孔中除去填充物。此时,优选低粘性以便其可以在合适的压力下移动。
图10表示图9的结构在已经在介电层403、势垒层406和铜层408上形成腐蚀阻止层410后的结构。其中使用铜来形成下互连线,腐蚀阻止层410是使用可以作为铜原子扩散的势垒的材料诸如SiN或SiC形成的。
图11-12表示根据本发明的处理的流程图。图11表示了形成暂时机械加强的夹层介电质的一般方法。图12表示了体现本发明的实施方法,其中在中度过孔的硅的氧化物在其空隙组分中被辅助成分暂时加固,执行多种严格的机械操作,并且通过溶解和蒸发除去辅助组分。上面已经描述了一些去除方法。对于包括湿处理的方法,处理流程将要求在烘干/硫化后进行清洗。对于干处理或者减缩工艺,不需要其它的步骤。
现在参照图11,描述一种方法,其中在衬底上形成一个多孔介电层(1102)。此多孔介电层可以是一个中度多孔的硅的氧化物或者聚合物。在一个实施例中,在其上形成多孔介电层的衬底可以是一个绝缘层诸如氮化硅或者碳化硅。这些材料适于被集成到集成电路制造工艺中因为它们不仅是电气绝缘层还可以作为铜离子扩散的势垒。下面的介电层本身是在形成多个有源、无源和电气互连元件的晶片的其它层上形成。多孔介电层通过迫使辅助成分进入至少一部分介电层空隙组分来机械加固(1104)。通过填充一些或者所有孔的至少一部分,增加了多孔介电层的机械强度。一旦介电层通过该方式加强,就可以执行一个或者多个大压力的以致于不能在未加固的介电层上完成的处理操作(1106)。此类处理操作包括,但不限于化学机械抛光、腐蚀和各种材料的沉积。在执行了一个或多个处理操作后,除去辅助成分(1108)。半导体领域的技术人员可以意识到可以在除去操作之后将残留部分辅助成分。通常,由于将辅助组分驱除出介电层希望减小介电常数,所以要求这些辅助组分的残留物最小。
参照图12,描述了一种在衬底上形成多孔介电层的方法(1202)。多孔介电层具有1.5到2.6范围内的介电常数。介电层接着被硫化来增加其孔隙度并且因此将其介电常数减小到1.5到2.2的范围。不希望的是,增加的孔隙度使介电层的机械强度太弱而不能承受随后处理操作,诸如例如,化学机械抛光。介电层接着被调整通过使用至少一种辅助成分填充介电层的至少一部分孔来增加其机械强度(1206)。介电层的介电常数通过孔的填充操作增加。在本发明的示范例中,加固的介电层接着被构图形成沟道和过孔开口(1208)。如参照图7-10所示,过孔不但在机械加固的介电层上形成,还在下面底的腐蚀阻止层上形成。此类构图在半导体制造领域是公知的并且通常包括在光致抗蚀剂上定义图形并且接着腐蚀下面材料的暴露的部分。在形成沟道和过孔之后,在构图的介电层表面形成一个势垒层(1210)。在该实施例中,势垒层被选择以便基本上防止铜原子的扩散。执行一个电镀处理以便在势垒层上形成一个金属层(1212),虽然可以使用某些铜合金,但金属层通常为铜。实际上,本发明对选择金属不作限制。多于地金属在大马士革处理中通过化学机械抛光除去以便在沟道和过孔中形成单独地互连线(1214)。接着除去辅助成分(1216)。在除去辅助成分之后,介电层的介电常数回复到一个较低的值。如上所述,可以通过溶解和蒸发、替代或者高温分解除去辅助成分。
通常,本发明的实施例在集成电路上提供低介电常数绝缘体。根据本发明的一个方面的方法通过暂时调整多孔ILD材料的机械特性允许高度多孔的ILD材料集成到Cu大马士革互连结构。
本发明的实施例的一些优点在于可以得到具有必需的机械强度来承受随后的诸如例如电化学抛光处理的低介电常数绝缘体。
本发明可以以各种变化和说明的实施例的替代物实现。例如,本发明可以在包括除了硅,诸如例如砷化镓、绝缘体硅(SOI)或者蓝宝石的衬底上形成。此外,实施例描述了大马士革多孔氧化硅和聚合物,但是本发明可以使用其它具有低k介电常数的材料实现。
本领域的技术人员应该理解对各部分和操作的细节、材料和结构上的各种变化的描述和说明是为了在不背离如附加的权利要求表述的本发明的原理和范围内说明本发明的本质。
Claims (24)
1.一种处理方法,包括:
在衬底上形成多孔介电材料,多孔材料具有多个孔;
使用至少一种材料填充至少一部分孔;
随后在介电材料上执行一个操作;和
除去至少一种材料的至少一部分。
2.根据权利要求1的处理方法,其中执行一个操作包括形成至少一个大马士革开口。
3.根据权利要求2的处理方法,还包括在所述介电层和所述至少一个大马士革开口上形成一个金属层。
4.根据权利要求3的处理方法,还包括抛光金属层以便除去所述大马士革开口外部的所述金属部分。
5.根据权利要求1的处理方法,其中所述至少一种金属包括可溶合的材料。
6.根据权利要求1的处理方法,其中除去包括溶解和蒸发。
7.根据权利要求1的处理方法,其中除去包括替代。
8.根据权利要求1的处理方法,其中除去包括高温分解。
9.根据权利要求1的处理方法,其中多孔介电材料包括中度多孔二氧化硅。
10.根据权利要求1的处理方法,其中多孔介电材料包括聚合物。
11.根据权利要求1的处理方法,其中至少一种材料包括非极性有机材料。
12.根据权利要求1的处理方法,其中至少一种材料包括树脂。
13.一种形成双大马士革铜互连结构的方法,包括:
沉积具有孔的低k介电层;
硫化所述低k介电层;
使用第一材料填充所述低k介电层的至少一部分孔;
构图所述低k介电层以便形成至少一个大马士革开口;
在构图的介电层上形成一个Cu扩散势垒层;
在Cu扩散势垒层的至少一部分上形成一个Cu籽晶层;
在所述籽晶层和所述扩散势垒层上形成一个金属层,所述金属包括Cu;
通过化学机械抛光除去一部分金属层;和
从填充的孔中除去至少一部分第一材料。
14.根据权利要求13的方法,其中所述低k介电层包括硅的氧化物。
15.根据权利要求13的方法,其中除去包括蒸发。
16.根据权利要求13的方法,其中除去包括替代。
17.一种暂时增加多孔薄膜的机械强度的方法,包括:
在一个衬底上沉积多孔薄膜,所述多孔薄膜具有多个孔,孔的尺寸和密度限定薄膜的孔隙率;
处理所述多孔薄膜来增加其孔隙率;
将一个或多种填充材料引入到所述多个孔的至少第一部分;和
随后从所述多个孔的至少第二部分除去至少一部分所述一种或多种填充材料。
18.根据权利要求17的方法,其中所述多孔薄膜包括中度多孔二氧化硅。
19.根据权利要求17的方法,其中所述多孔薄膜包括聚合物。
20.根据权利要求17的方法,其中处理所述多孔薄膜来增加其孔隙率包括硫化处理。
21.根据权利要求17的方法,其中处理所述多孔薄膜来增加其孔隙率包括老化处理。
22.一种形成用于集成电路的夹层介电质的方法,包括:
在一个衬底上形成介电材料,所述介电材料具有多个孔;
将材料引入到所述多个孔的每个的至少一部分中;
在介电材料上腐蚀一个图形;和
从所述多个孔的至少一部分除去至少一部分材料。
23.根据权利要求22的方法,其中引入一种材料包括将介电材料浸入液体中。
24.根据权利要求23的方法,其中除去至少一部分材料包括将介电材料放置在一个环境中以便使材料蒸发。
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WO2015182581A1 (ja) * | 2014-05-29 | 2015-12-03 | アーゼット・エレクトロニック・マテリアルズ(ルクセンブルグ) ソシエテ・ア・レスポンサビリテ・リミテ | 空隙形成用組成物、その組成物を用いて形成された空隙を具備した半導体装置、およびその組成物を用いた半導体装置の製造方法 |
US9514929B2 (en) * | 2015-04-02 | 2016-12-06 | International Business Machines Corporation | Dielectric filling materials with ionic compounds |
JP6997092B2 (ja) * | 2016-02-19 | 2022-01-17 | ダウ シリコーンズ コーポレーション | エージングしたシルセスキオキサンポリマー |
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JPH01235254A (ja) | 1988-03-15 | 1989-09-20 | Nec Corp | 半導体装置及びその製造方法 |
US5470802A (en) * | 1994-05-20 | 1995-11-28 | Texas Instruments Incorporated | Method of making a semiconductor device using a low dielectric constant material |
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US5955140A (en) | 1995-11-16 | 1999-09-21 | Texas Instruments Incorporated | Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates |
US5895263A (en) | 1996-12-19 | 1999-04-20 | International Business Machines Corporation | Process for manufacture of integrated circuit device |
EP0881678A3 (en) | 1997-05-28 | 2000-12-13 | Texas Instruments Incorporated | Improvements in or relating to porous dielectric structures |
TWI222426B (en) * | 1998-04-01 | 2004-10-21 | Asahi Kasei Corp | Method for producing a circuit structure |
AU756688B2 (en) | 1998-06-05 | 2003-01-23 | Georgia Tech Research Corporation | Porous insulating compounds and method for making same |
US6390291B1 (en) * | 1998-12-18 | 2002-05-21 | Smithkline Beecham Corporation | Method and package for storing a pressurized container containing a drug |
US6329017B1 (en) * | 1998-12-23 | 2001-12-11 | Battelle Memorial Institute | Mesoporous silica film from a solution containing a surfactant and methods of making same |
US6280794B1 (en) * | 1999-03-10 | 2001-08-28 | Conexant Systems, Inc. | Method of forming dielectric material suitable for microelectronic circuits |
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2000
- 2000-12-21 US US09/745,397 patent/US6703324B2/en not_active Expired - Lifetime
-
2001
- 2001-11-13 EP EP01272453A patent/EP1344248A2/en not_active Ceased
- 2001-11-13 WO PCT/US2001/043646 patent/WO2002052629A2/en not_active Application Discontinuation
- 2001-11-13 CN CNB018211798A patent/CN1238887C/zh not_active Expired - Fee Related
- 2001-11-13 AU AU2002217802A patent/AU2002217802A1/en not_active Abandoned
- 2001-11-16 TW TW090128503A patent/TW543116B/zh not_active IP Right Cessation
-
2003
- 2003-09-02 US US10/654,299 patent/US20040157436A1/en not_active Abandoned
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2004
- 2004-10-19 HK HK04108172A patent/HK1065402A1/xx not_active IP Right Cessation
Cited By (7)
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US8445382B2 (en) | 2005-03-22 | 2013-05-21 | Nxp B.V. | Side wall pore sealing for low-k dielectrics |
CN100589231C (zh) * | 2006-04-21 | 2010-02-10 | 台湾积体电路制造股份有限公司 | 低介电常数的介电薄膜的形成方法 |
US8043959B2 (en) | 2006-04-21 | 2011-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a low-k dielectric layer with improved damage resistance and chemical integrity |
CN102762039A (zh) * | 2011-04-27 | 2012-10-31 | 欣兴电子股份有限公司 | 线路板及其制作方法 |
CN102762039B (zh) * | 2011-04-27 | 2015-04-01 | 欣兴电子股份有限公司 | 线路板及其制作方法 |
CN103943557A (zh) * | 2014-04-28 | 2014-07-23 | 华进半导体封装先导技术研发中心有限公司 | 利用cmp对重布线层中聚合物介质层表面进行平坦化的方法 |
CN103943557B (zh) * | 2014-04-28 | 2017-01-11 | 华进半导体封装先导技术研发中心有限公司 | 利用cmp对重布线层中聚合物介质层表面进行平坦化的方法 |
Also Published As
Publication number | Publication date |
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WO2002052629A3 (en) | 2003-03-20 |
TW543116B (en) | 2003-07-21 |
US6703324B2 (en) | 2004-03-09 |
AU2002217802A1 (en) | 2002-07-08 |
US20020115285A1 (en) | 2002-08-22 |
US20040157436A1 (en) | 2004-08-12 |
HK1065402A1 (en) | 2005-02-18 |
EP1344248A2 (en) | 2003-09-17 |
CN1238887C (zh) | 2006-01-25 |
WO2002052629A2 (en) | 2002-07-04 |
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