CN1501757A - Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor - Google Patents
Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor Download PDFInfo
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- CN1501757A CN1501757A CNA021513414A CN02151341A CN1501757A CN 1501757 A CN1501757 A CN 1501757A CN A021513414 A CNA021513414 A CN A021513414A CN 02151341 A CN02151341 A CN 02151341A CN 1501757 A CN1501757 A CN 1501757A
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Abstract
The invention relates to a power supply line static protection circuit using gate-coupled MOSFET, wherein the gate potential of the MOSFET includes a reversing device and a defer time sequence control circuit. The invention uses a voltage-divider circuit formed by a pull-down assembly, when static electricity occurs, the grid potential of the MOSFET is limited to 1 to 2V.
Description
Technical field
The present invention relates to a kind of electrostatic discharge protective circuit, the power bus electrostatic discharge protective circuit of particularly a kind of use gate coupled metal-oxide half field effect transistor (Gate-Coupled MOSFET).
Background technology
In the static discharge process of manikin (Human-Body-Model), the electric capacity of a 100pF can be charged to electrostatic potential earlier, then via conductive discharge to an IC bond (ICpin) of a 1.5k Ω.When test one packaged integrated circuits, can use the electrostatic potential of 2KV size usually.Are about initial current value and current rise time 1.2A and 10nsec.In packaged integrated circuits, high potential VDD is general all greater than 1nF to the electric capacity between electronegative potential VSS.If the static discharge energy directly absorbs (direct static discharge by VDD to VSS pin) by power bus, perhaps (static discharge of forward betides has the device of drawing high by the power bus absorption indirectly, as the output of p+/nwell or P type metal-oxide half field effect transistor, go on the weld pad), when to carry out voltage be 2 to 3KV manikin static discharge, the voltage climbing speed of packaged integrated circuits inside will reach 1--2KV/nsec.
Transistor generally is used as the main electrostatic protection assembly of integrated circuit at present as gate coupled N type gold oxygen half (GCNMOS) transistor, an oxidation metal-oxide half field effect transistor (field-oxide MOSFET) or output buffer transistor.
Concerning the pin or power bus of integrated circuit, GCNMOS can be used for as main electrostatic protection assembly.Nmos transistor drain wherein is coupled to VDD or pin, and source electrode then is coupled to VSS.Its grid can ground connection, be coupled to VDD or be coupled to VSS via a resistance via an electric capacity.
Static discharge voltage is clamped down on device
The transistor that one use one of common ESD protection circuit is controlled by resistance-capacitance circuit (RC circuit) is to shunt static discharge current between protected weld pad and power supply supply weld pad (as the VSS weld pad).
Fig. 1 has shown that tradition clamps down on circuit (voltageclamping circuit) by the active MOSFET static discharge that RC triggers.This clamps down on circuit when the forward static discharge of a VDD to VSS takes place, and provides a shunt paths to protect internal circuit.On node G, produce reverse current potential by the current potential of the reverser 11 receiving node E that transistor N1, P1 constituted, but so make transistor N1 conducting a period of time, and this ON time is determined by R1 and the formed RC time constant of C1.This RC time constant is the static discharge time long (in general being approximately more than 50 to hundreds of nanoseconds) of expection, and also can not be long when avoiding rising (being generally several milliseconds) in normal VDD power bus voltage, mistake is touched this and is clamped down on circuit.Fix at VDD power supply supply voltage, during the integrated circuit normal running, reduce to low-potential state, make transistor N1 be biased under the nonconducting state because resistance R 1 is drawn high the current potential of node E to draw to the current potential of high potential state, node G.
Above-mentioned static discharge voltage is clamped down on device and can be used between VDD and VSS lead.Yet it has following shortcoming: (1) area is excessive, and its total channel width is between 4000 to 10000 μ m.(2) reverser 11 can amplify the noise on the VDD power bus, can produce bad leakage current at transistor N2 when causing circuit operation.
The electrostatic protection device of collapse (Avalanche Breakdown) formula
Another kind of common electrostatic protection mode is to utilize the collapse of MOSFET and logical (snap back) phenomenon of jumping to reach.This kind phenomenon is when initial, and the caused impact ionization of big electric field (impact ionization) phenomenon that is positioned at drain junction can produce majority (majority) and minority (minority) carrier simultaneously.Minority carrier can be collected in drain electrode, and most carriers then flow to the contact hole (contact) of substrate or P wellblock and form a local potential in the P wellblock.When the contiguous N+ source potential of the local potential of substrate exceeded 0.8V, source junction just formed forward bias voltage drop.Can inject minority carrier to the P wellblock along inclined to one side source junction.Partly by combination (recombined) again, other then arrival drain junction has strengthened impacting Ionized phenomenon to the minority carrier that injects further in substrate.Xun Huan result according to this, MOSFET just can enter the logical state of a kind of low-impedance jumping, and a large amount of static discharge current of beginning conducting.
In the static discharge generating process, if can reduce the shake-up voltage of MOSFET conducting great benefit will be arranged, can make the reaction of electrostatic protection faster, add all in output, go into end and internal circuit instantaneous voltage lower.
The mode of traditional use gate coupled that shown Fig. 2 reduces the electrostatic discharge protective circuit that touches voltage.Wherein, the size of R1, C1 is chosen in the RC time constant that makes its formation can allow the current potential of node G arrive 1 to 2V in the static discharge process, to reduce in order to touch the magnitude of voltage that transistor N2 enters collapse and jumps logical state.
In above-mentioned traditional gate coupled transistor, because the discharge of electrostatic induced current is reached via the double carriers between transistor drain/substrate/source electrode (bipolar) behavior, it can be clamped down on circuit than electrostatic potential and use area still less to come the bigger electrostatic induced current of conducting.Electrostatic protection with the VDD power bus is an example, and its total channel width only needs 600 to 1200 μ m can reach enough electrostatic protection effects usually.
Yet tradition is used the transistorized electrostatic discharge protective circuit of gate coupled still to have because of ESD intensity (voltage) to differ and the transient voltage climbing differs and causes best RC time constant to be difficult for the shortcoming of selecting.
Summary of the invention
In order to address the above problem, the invention provides a kind of electrostatic discharge protective circuit, use the gate coupled transistor after improvement, when taking place, the positive voltage static discharge can make transistor have more stable Instantaneous Grid bias voltage.
A purpose of the present invention is to provide a kind of electrostatic discharge protective circuit that uses the gate coupled metal-oxide half field effect transistor; when an electrostatic potential produces on a first node; in order to the discharge path from this first node to one Section Point to be provided, comprise a delay circuit, a voltage divider and a shunting transistor.Delay circuit is exported a current potential when this electrostatic potential produces.Voltage divider receives this electrostatic potential, and touches a dividing potential drop of this electrostatic potential of back output via the current potential of this delay circuit output.The drain electrode of shunting transistor is coupled to this first node, source electrode is coupled to this Section Point, when this electrostatic potential produces, drain electrode receives this electrostatic potential from this first node, grid receives the dividing potential drop of this electrostatic potential from this voltage divider, makes this shunting transistor enter one and jumps logical state and produce this discharge path.
By this; the present invention has and surmounts the advantage that electric current shunting static discharge is clamped down on device and traditional gate coupled device simultaneously; not only have than electric current shunting static discharge and clamp down on the little size of circuit, also the electrostatic discharge protective circuit of more traditional gate coupled is better in the control of the instantaneous bias voltage of grid.
Below, accompanying drawings a kind of embodiment that uses the electrostatic discharge protective circuit of gate coupled metal-oxide half field effect transistor of the present invention.
Description of drawings
Fig. 1 shows that tradition clamps down on circuit by the active MOSFET static discharge that RC triggers;
Fig. 2 shows that the mode of tradition use gate coupled reduces the electrostatic discharge protective circuit that touches voltage;
Fig. 3 shows the electrostatic discharge protective circuit in the first embodiment of the invention;
Fig. 4 A shows the electrostatic discharge protective circuit in the second embodiment of the invention;
Fig. 4 B shows the electrostatic discharge protective circuit in the third embodiment of the invention;
Fig. 5 shows the electrostatic discharge protective circuit in the fourth embodiment of the invention;
Fig. 6 shows the electrostatic discharge protective circuit in the fifth embodiment of the invention;
Fig. 7 shows the electrostatic discharge protective circuit in the sixth embodiment of the invention;
Fig. 8 shows the electrostatic discharge protective circuit in the seventh embodiment of the invention.
Symbol description
11,31,51--reverser;
33,53,63--delay circuit;
The 35--voltage divider;
The 41--weld pad;
N1, N2, P1, P2, N3, N4--transistor;
The D1--diode;
R1, R2, R3--resistance;
C1--electric capacity.
Embodiment
Fig. 3 has shown the electrostatic discharge protective circuit in the first embodiment of the invention.Present embodiment provides the discharge path to Node B from node A in order to when an electrostatic potential produces on node A.The voltage divider of forming by transistor P1, P2 and resistance R 2, R3 comprising a delay circuit of forming by resistance R 1 and capacitor C 1 33, one 35, and shunting transistor N2.Delay circuit 33 keeps an electronegative potential in node E when electrostatic potential produces the initial stage.Voltage divider 35 receives electrostatic potential from node A, and makes transistor P1 conducting via the electronegative potential that E is ordered, and in a dividing potential drop of node G output electrostatic potential.The drain electrode of shunting transistor N2 is coupled to node A, source electrode is coupled to Node B, and when electrostatic potential produced, drain electrode received electrostatic potential from node A, grid makes shunting transistor N2 enter one and jumps logical state and produce discharge path from the dividing potential drop of voltage divider 35 reception electrostatic potentials.In addition, at the static early period of origination, shunting transistor N2 receives the suitable dividing potential drop of electrostatic potential and is in a weak conducting state from voltage divider 35, shunting transistor N2 is entered ahead of time jump the trigger voltage reduction of leading to state.In voltage divider 35, the current potential that the grid receive delay circuit 33 of transistor P1 is ordered at E, source electrode is coupled to node A, and drain electrode is coupled to the grid of shunting transistor N2.The grid of transistor P2 is coupled to Node B jointly with drain electrode, and the drain electrode of source electrode and transistor P1 is coupled to the grid of shunting transistor N2 jointly and exports the dividing potential drop of electrostatic potential.
Transistor P1, P2 are the MOSFET of P type, and transistor N1, N2 are the MOSFET of N type.Transistor N1, P1 also form a reverser 31.
At the beginning of the positive voltage static discharge takes place, the current potential of node A upwards increases, the current potential of node E remains on low-potential state, and transistor P1 and P2 then are in conducting state, and the current potential on the node G is then decided by the ratio of the conduction resistance value (on-resistance) of transistor P1 and P2.This moment, transistor P1 and P2 promptly waited same voltage divider.Breadth length ratio (W/L) by adjusting channel, the trigger voltage value considering matrix effect (body effect) and estimate transistor N2 just can be at the current potential of node A during in the trigger voltages that rises near transistor N2, on node G, keep as 1 to 2V half voltage range of 0.5 to 2.5V or 0.5 to A node voltage.
Under the ratio of considering matrix effect that transistor P1, P2 are different and W/L, represent the node W of the N wellblock of transistor P2 can be coupled to node G, can also be coupled to node A.
The P wellblock node K of transistor N2 can be coupled to Node B, can also be coupled to node G.If be coupled to node G, when the source junction of transistor N2 takes place at an esd event, be in suitable state partially and enter the logical state of jumping further to trigger transistor N2 ahead of time.
The action that provides time enough to trigger by resistance R 1, capacitor C 1 formed RC time constant to NMOS.For instance, this RC time constant can be between 15 to 50 nanoseconds.
Resistance R 2 can be merely the resistance value of plain conductor with R3, or is provided by other resistor assembly (for example by the formed resistor assembly of polysilicon or N wellblock), the size of current of flow through when being limited in the static discharge generation transistor P1, P2.So, have following voltage ratio by transistor P1, P2, resistance R 2, the formed voltage divider of R3:
V
G/V
A＝[R
ON(P2)+R3]/[R
ON(P1)+R2+R
ON(P2)+R3]
Wherein, V
G, V
AThe current potential of difference representation node G, A, R
ON(P1), R
ON(P2) represent the conduction resistance value of transistor P1, P2 respectively.In addition, in the instantaneous process of static discharge, transistor N2 grid capacitance value has also been played the part of a key player, yet the people who knows this technology should know that understanding under the condition of the temporal pattern of setting static discharge, can utilize circuit simulation to obtain the size of suitable resistance R 2, R3 value and transistor P1, P2.
When node A be the VDD power bus and opening the VDD power supply after (powered on), the grid potential of transistor N1 can be drawn high to high potential via resistance R 1 and be in conducting state, and the grid (node G) that makes transistor N2 is everywhere in closed condition.
Above-mentioned electrostatic discharge protective circuit is when the circuit normal running, even produce noise at node E, the current potential of node G also is limited and can suppresses the leakage current of transistor N2.
Fig. 4 A has shown the electrostatic discharge protective circuit in the second embodiment of the invention, the modification of above-mentioned first embodiment.Wherein, transistor P2 is directly replaced by resistance R 3, and transistor N1 is also removable, so still can reach the similar function with first embodiment.At this moment, the voltage ratio of voltage divider is:
V
G/V
A＝R3/[R
ON(P1)+R2+R3]
This voltage ratio can preferably be between 1/15 to 3/5, so that this transistor N2 is near touching when logical, grid potential G o'clock near 1 to 2V, 0.5 to 2.5V or half voltage range of 0.5V to A node voltage.
Fig. 4 B has shown the electrostatic discharge protective circuit in the third embodiment of the invention.The second above-mentioned embodiment is two electrostatic discharge protective circuits between the node, certainly, can also use a plurality of shunting transistors and electrostatic protection between a plurality of nodes (IC pin or power bus) and VSS is provided, shown in Fig. 4 B.This electrostatic discharge protective circuit has used transistor N4 and N2 to provide VDD to VSS and weld pad to the electrostatic discharging path between VSS respectively; wherein transistor N4 utilizes the direct conducting of grid bias, and transistor N2 then utilizes grid bias to enter the mode of jumping logical state ahead of time discharge path is provided.
When the positive voltage static discharge betides the VDD power bus, identical with above-mentioned first embodiment in the static discharge instantaneous process, also through (its voltage ratio is V by transistor P1, resistance R 2, voltage divider that R3 formed
G/ V
A=[R2+R3]/[R
ON(P1)+R2+R3]), and make the direct conducting of transistor N4; When static discharge betided on the weld pad 41, this electrostatic potential can be coupled on the VDD bus through transistor P2, not only makes the direct conducting of transistor N4, also made to produce bias voltage on the grid of transistor N2 (its voltage ratio is V
G '/ V
A=[R3]/[R
ON(P1)+R2+R3]), and the trigger voltage of transistor N2 is descended, make the transistor N2 can the faster function that electrostatic protection is provided between weld pad 41 and VSS.The ratio of resistance R 3 and R2 can preferably be between 1: 12 to 2.5: 5 or 1.5: 7 to 2.5: 5, so that when static discharge took place, the grid potential of N2 and N4 was in preferable scope.
In addition, in the 3rd embodiment, the value of resistance R 2 can be reduced to extremely low, as the resistance (being short circuit between node G and the resistance R 3) that only contains lead, the grid of transistor N4 and N2 will have identical current potential this moment, provide discharge path and all utilize grid bias to enter the mode of jumping logical state ahead of time.
Fig. 5 has shown the electrostatic discharge protective circuit in the fourth embodiment of the invention.The 4th embodiment is the modification of first embodiment, and wherein the reverser in Fig. 3 31 directly replaces with a reverser symbol.Comparison diagram 5 can find with Fig. 3, the location swap of resistance R 1 and capacitor C 1, P transistor npn npn P2 is replaced into N transistor npn npn N3, and its grid is coupled to node G, and between reverser 31 and node G increase by one reverser 51.
The operation of the 4th embodiment also is similar to the operation of first embodiment.The reverser 31,51 and the N transistor npn npn N3 of polyphone form voltage divider mutually by two, and the input receive delay circuit 53 of reverser 31 is at the current potential of E point output, the source electrode of N transistor npn npn N3 is coupled to Node B, and the output of grid, drain electrode and reverser 51 is coupled to the grid of shunting transistor N2 jointly and exports the dividing potential drop of electrostatic potential.At first, at the beginning of the positive voltage static discharge took place, the current potential of node A rose, because the relation of capacitor C 1, the current potential of node E is also followed node A and risen.Behind the reverser 31 and 51 through two polyphones, the current potential of node G is reversed device 51 and draws high and follow node E and rise.Yet the current potential of node G be owing to can make transistor N3 conducting when rising to limit voltage above transistor N3 thereon, and can't be pulled up to the current potential near node A.So, suitably adjust the W/L value of transistor N3 and reverser 51, when the current potential of node A when rising, can on node G, obtain current potential as 1 to 2V or 0.5 to 2.5V, reduced the trigger voltage of transistor N2.
The P wellblock node K of transistor N2 can be coupled to Node B (normally P type substrate).In addition, node K can also be coupled to node G or be in floating.
Fig. 6 has shown the electrostatic discharge protective circuit of fifth embodiment of the invention.The 5th embodiment is the modification of the 4th embodiment, and wherein resistance R 1 and the position of capacitor C 1 return back to identically with first embodiment, only use a reverser 31 and transistor N3 is replaced with a diode D1.
Transistor N3 among diode D1 and the 4th embodiment has identical functions.Voltage divider is made up of reverser 31 and diode D1.The input receive delay circuit 63 of reverser 31 is at the current potential of E point output, and the negative terminal of diode D1 is coupled to Node B, and the output of anode and reverser 31 is coupled to the grid of shunting transistor N2 jointly and exports the dividing potential drop of electrostatic potential.At the beginning of the positive voltage static discharge took place, the current potential of node A rose, because the relation of capacitor C 1, the current potential of node E remains on the electronegative potential near VSS.Through behind the reverser 31, the pulled transistor that the current potential of node G is reversed in the device 31 upwards draws high.Yet the current potential of node G be owing to can make diode D1 conducting when rising to conducting voltage above transistors diodes D1 thereon, and can't be pulled up to the current potential near node A.So, suitably adjust the W/L value of diode D1 and reverser 31, when the current potential of node A when rising, can on node G, obtain preferably as 1 to 2V current potential, reduced the trigger voltage of transistor N2.
Among the 5th embodiment of this external Fig. 6, diode D1 can also be replaced as a resistance by an impedance (impedance).
Fig. 7 has shown the electrostatic discharge protective circuit of sixth embodiment of the invention.The 6th embodiment also is the modification of first embodiment.This circuit is used between weld pad and the VSS electrostatic discharge (ESD) protection is provided.
Wherein, resistance R 1, transistor P1 are coupled to the VDD power bus, and transistor N2 is coupled to a weld pad.One P type MOSFET P3 then is coupled between weld pad and the VDD power bus.
When the positive voltage static discharge betided between weld pad and the VSS, positive electrostatic potential was to be coupled to the VDD power bus via the formed parasitic diode in p+/nwell composition surface of transistor P3.Remaining operation is then with first embodiment.In addition, transistor P3 can also replace with a diode, as shown in Figure 8.
Comprehensively above-mentioned, the present invention has and surmounts the advantage that electric current shunting static discharge is clamped down on device and traditional gate coupled device simultaneously.Can have less size (for example about 500 to 1200 μ m) at N type MOSFET used in the present invention; the static discharge of electric current shunting is clamped down on circuit then needs 3000 to 10000 μ m, and the electrostatic discharge protective circuit of the more traditional gate coupled of instantaneous bias voltage on the grid is had better control.
Though the present invention is open with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; can do some equivalence and change and modification, so protection scope of the present invention is as the criterion with claim.
Claims (14)
1. an electrostatic discharge protective circuit that uses the gate coupled metal-oxide half field effect transistor when an electrostatic potential produces on a first node, in order to the discharge path from this first node to one Section Point to be provided, is characterized in that, comprising:
One delay circuit is exported a current potential when this electrostatic potential produces;
One voltage divider receives this electrostatic potential, and touches a dividing potential drop of this electrostatic potential of back output via the current potential of this delay circuit output; And
One shunting transistor, drain electrode is coupled to this first node, source electrode is coupled to this Section Point, when this electrostatic potential produces, drain electrode receives this electrostatic potential from this first node, grid receives the dividing potential drop of this electrostatic potential from this voltage divider, makes this shunting transistor enter one and jumps logical state and produce this discharge path.
2. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1; it is characterized in that; this shunting transistor receives the dividing potential drop of this electrostatic potential and is in a weak conducting state from this voltage divider, and a trigger voltage that makes this shunting transistor enter the logical state of this jumping reduces.
3. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1 is characterized in that, before this shunting transistor entered the logical state of jumping, the dividing potential drop of this electrostatic potential of this voltage divider output was between 1 to 2V.
4. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1 is characterized in that, before this shunting transistor entered the logical state of jumping, the dividing potential drop of this electrostatic potential of this voltage divider output was between 0.5 to 2.5V.
5. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1; it is characterized in that; before this shunting transistor entered the logical state of jumping, the dividing potential drop of this electrostatic potential of this voltage divider output was half of the positive operating voltage level of 0.5V to.
6. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1 is characterized in that, this voltage divider comprises:
One the one P transistor npn npn, grid receive the current potential of this delay circuit output, and source electrode is coupled to this first node, and drain electrode is coupled to the grid of this shunting transistor; And
One the 2nd P transistor npn npn, grid is coupled to this Section Point jointly with drain electrode, and the drain electrode of a source electrode and a P transistor npn npn is coupled to the grid of this shunting transistor jointly and exports the dividing potential drop of this electrostatic potential.
7. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 6 is characterized in that, the 2nd P transistor npn npn has a N wellblock, and this N wellblock and source electrode couple.
8. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 6 is characterized in that, the 2nd P transistor npn npn has a N wellblock, and this N wellblock and this first node couple.
9. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1 is characterized in that, this voltage divider comprises:
One first and second reverser, the input of polyphone and this first reverser receives the current potential of this delay circuit output mutually; And
One N transistor npn npn, source electrode is coupled to this Section Point, and the output of grid, drain electrode and this second reverser is coupled to the grid of this shunting transistor jointly and exports the dividing potential drop of this electrostatic potential.
10. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1 is characterized in that, this voltage divider comprises:
One reverser, input receive the current potential of this delay circuit output; And
One diode, negative terminal are coupled to this Section Point, and the output of anode and this reverser is coupled to the grid of this shunting transistor jointly and exports the dividing potential drop of this electrostatic potential.
11. the electrostatic discharge protective circuit of use gate coupled metal-oxide half field effect transistor as claimed in claim 1 is characterized in that, this voltage divider comprises:
One reverser, input receive the current potential of this delay circuit output; And
One resistance, an end is coupled to this Section Point, and the output of the other end and this reverser is coupled to the grid of this shunting transistor jointly and exports the dividing potential drop of this electrostatic potential.
12. an electrostatic discharge protective circuit that uses the gate coupled metal-oxide half field effect transistor when an electrostatic potential produces on one first power bus, in order to the discharge path from this first power bus to second source bus to be provided, is characterized in that, comprising:
One delay circuit is exported a current potential when this electrostatic potential produces;
One voltage divider receives this electrostatic potential, and touches a dividing potential drop of this electrostatic potential of back output via the current potential of this delay circuit output; And
One shunting transistor, drain electrode is coupled to this first power bus, source electrode is coupled to this second source bus, when this electrostatic potential produces, drain electrode receives this electrostatic potential from this first power bus, grid receives the dividing potential drop of this electrostatic potential from this voltage divider, makes this shunting transistor enter one and jumps logical state and produce this discharge path.
13. electrostatic discharge protective circuit that uses the gate coupled metal-oxide half field effect transistor; when an electrostatic potential produces on a weld pad; in order to the discharge path from this weld pad to one second source bus to be provided; wherein this electrostatic potential is coupled to one first power bus via a PN composition surface; it is characterized in that this circuit comprises:
One delay circuit is exported a current potential when this electrostatic potential produces;
One voltage divider receives this electrostatic potential, and touches a dividing potential drop of this electrostatic potential of back output via the current potential of this delay circuit output; And
One shunting transistor, drain electrode is coupled to this weld pad, source electrode is coupled to this second source bus, when this electrostatic potential produces, drain electrode receives this electrostatic potential from this weld pad, grid receives the dividing potential drop of this electrostatic potential from this voltage divider, makes this shunting transistor enter one and jumps logical state and produce this discharge path.
14. an electrostatic discharge protective circuit that uses the gate coupled metal-oxide half field effect transistor, when an electrostatic potential several first nodes one on when producing, in order to the discharge path to a Section Point to be provided, it is characterized in that, comprising:
One delay circuit is exported a current potential when this electrostatic potential produces;
One voltage divider receives this electrostatic potential, and touches a dividing potential drop of this electrostatic potential of back output via the current potential of this delay circuit output; And
Several shunting transistors, drain electrode is coupled to those first nodes, source electrode is coupled to this Section Point, when this electrostatic potential produces, drain electrode receives this electrostatic potential from one of those first nodes, grid receives the dividing potential drop of this electrostatic potential from this voltage divider, makes one of those shunting transistors enter one and jumps logical state and produce this discharge path.
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|---|---|---|---|
| CN 02151341 CN1228844C (en) | 2002-11-15 | 2002-11-15 | Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor |
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|---|---|---|---|
| CN 02151341 CN1228844C (en) | 2002-11-15 | 2002-11-15 | Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor |
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- 2002-11-15 CN CN 02151341 patent/CN1228844C/en not_active Expired - Fee Related
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| CN113053856A (en) * | 2019-12-26 | 2021-06-29 | 湖南国芯半导体科技有限公司 | Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device |
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