CN102779819B

CN102779819B - ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process

Info

Publication number: CN102779819B
Application number: CN201210294541.0A
Authority: CN
Inventors: 高国平; 周毅; 罗静
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2012-08-17
Filing date: 2012-08-17
Publication date: 2014-12-03
Anticipated expiration: 2032-08-17
Also published as: CN102779819A

Abstract

The invention relates to an ESD (Electronic Static Discharge) protection structure based on a partial depletion mode SOI (Silicon on Insulator) process. A common enhanced PMOS (P-channel Metal Oxide Semiconductor) transistor in an SOI process is used, substrate contact is not needed, a P+/N well parasitic diode of the source end of the PMOS transistor is used for offsetting an N well; and the grid electrode of the PMOS transistor is offset by using a clamp circuit. The capacity of carrying out ESD protection is improved by using a reverse breakdown principle. The ESD protection structure has the advantages of simple structure and small occupation layout area in an SOI/CMOS integrated circuit, is convenient for use, and effectively improves the ESD tolerance level of the integrated circuit.

Description

A kind of esd protection structure based on PD SOI technique

Technical field

The present invention relates to a kind of esd protection structure based on PD SOI technique, belong to technical field of integrated circuits.

Background technology

SOI technology refers on insulating barrier and to form the technology that the material with certain thickness single crystal semiconductor silicon membrane layer prepares technology and manufacture semiconductor device on thin layer.This technology can realize completely medium isolation, and compares with the body silicon device of P-N knot isolation, has the advantages such as, radiation hardness high, high temperature resistant without breech lock, high-speed, low-power consumption, integrated level.

According to SOI silicon film thickness, SOI device can be divided into thick film device and thin-film device.For thick film SOI device, when SOI silicon film thickness is greater than the maximum depletion widths of twice, be called as part depletion device; For Thin film SOI device, when the thickness of silicon fiml is less than maximum depletion widths, be called full depleted device.

In SOI technology, device is fabricated in the silicon fiml that top layer is very thin, buries oxide layer separate between device and substrate by one deck.This structure makes SOI/ MOS device have the many merits low in energy consumption of Denging just, than traditional body silicon MOS technique, compares, and is more suitable in high performance ULSI and VLSI circuit.Its advantage mainly comprises:

1, without latch-up.In SOI/MOS device, due to the existence of dielectric isolation structure, therefore do not arrive the current channel of substrate, the path of latch-up is cut off, and mutually isolates physically with in electricity between each device, has improved the reliability of circuit.

2, simple in structure, technique is simple, and integration density is high.SOI/MOS device architecture is simple, does not need to prepare the complicated isolation technologies such as trap of Bulk CMOS circuit, and the restriction of photoetching and lithographic technique is only depended in device minimum interval, and integration density significantly improves.SOI/MOS device is also particularly suitable for integrated high voltage and low-voltage circuit on same chip, therefore has very high chip area utilance and cost performance.

3, parasitic capacitance is little, and operating rate is fast.The main electric capacity of body silicon MOS device is the electric capacity between pipe source-drain area and source/leakage diffusion zone and substrate, and its doping content with substrate increases, and this affects the operating rate of circuit by the load capacitance of increasing circuit; In SOI/MOS device, owing to burying the existence of oxide layer, source-drain area and substrate cannot form PN junction, parasitic PN junction electric capacity disappears, the substitute is buried oxidation layer electric capacity, this electric capacity is proportional to the dielectric constant of capacitance material, and its value is much smaller than the PN junction parasitic capacitance of source-drain area in body silicon and substrate, and is not subject to the impact of scaled down.

4, low-power consumption.The power consumption of SOI/MOS device is comprised of quiescent dissipation and two parts of dynamic power consumption, and SOI device has steep sub-threshold slope, approaches desirable level, so leakage current is very little, and quiescent dissipation is very low; Because SOI/MOS device has than the less junction capacitance of body silicon device and wire capacitances, therefore, under same operating rate, dynamic power consumption also reduces greatly.

From esd protection analysis, because SOI technique MOS device forms above oxide layer burying, compare with body silicon, reduced the heat radiation volume of device, so the esd protection ability of device weakens greatly.

In the world the esd protection of SOI technique circuit is adopted in two ways more at present: 1, utilize gate control diode to carry out esd protection, mainly use the characteristic of the forward conduction of gate control diode.2, adopt the metal-oxide-semiconductor of dynamically opening, mainly use the conducting simultaneously of metal-oxide-semiconductor and parasitic gate control diode.Above two kinds of modes are difficult to meet the various demand of input/output end port.

Summary of the invention

The present invention seeks to overcome the deficiencies in the prior art; a kind of esd protection device architecture based on PD SOI technique is provided; based on PD SOI technique; use enhancement mode PMOS pipe; the structure that substrate is floated; utilize parasitic PNP dynatron performance, improved and utilized reverse breakdown to carry out the device capabilities of esd protection.

According to technical scheme provided by the invention, a kind of esd protection structure based on PD SOI technique, comprise a N-type substrate PMOS tubular construction, described N-type substrate PMOS tubular construction comprises that grid, diffusion region, P+ source, P+ leak diffusion region, N trap, silicon dioxide isolated area, oxygen buried layer and silicon substrate, described oxygen buried layer is positioned on silicon substrate, and diffusion region, described P+ source, P+ leak diffusion region, N trap and silicon dioxide isolated area and be positioned on oxygen buried layer; Described N trap leaks between diffusion region in diffusion region, P+ source and P+, in diffusion region, P+ source, between N trap, forms parasitic diode, and silicon dioxide isolated area surrounds diffusion region, described P+ source and P+ leaks diffusion region; Described grid is positioned on N trap; The exit of diffusion region, described P+ source is the source of PMOS pipe, and the exit that P+ leaks diffusion region is the drain terminal of PMOS pipe; Between the source of grid and PMOS pipe, connect clamp circuit; The parasitic diode of PMOS pipe source is setovered to N trap; The grid of PMOS pipe is used clamp circuit to setover.

When being used in while carrying out esd protection between input pressure welding point and ground; the source of PMOS pipe connects input pressure welding point by semiconductor alloy aluminium; drain terminal is connected with ground by semiconductor alloy aluminium; the current potential of N trap is determined by diffusion region, P+ source and parasitic diode; clamp circuit guarantees that PMOS pipe is in off state when under normal mode of operation.

When being used in while carrying out esd protection between input pressure welding point and power supply; the source of PMOS pipe connects power supply by semiconductor alloy aluminium; drain terminal connects input pressure welding point by semiconductor alloy aluminium; the current potential of N trap is determined by diffusion region, P+ source and parasitic diode; clamp circuit guarantees that PMOS pipe is in off state when under normal mode of operation.

Described silicon substrate material is highly doped monocrystalline silicon; Oxygen buried layer material is silicon dioxide; It is B Implanted element in silicon that diffusion region, P+ source and P+ leak diffusion region material, and the degree of depth arrives oxygen buried layer; N trap material for injecting P elements in silicon, and the degree of depth arrives oxygen buried layer; Silicon dioxide isolated area material is silicon dioxide, and the degree of depth arrives oxygen buried layer; Grid is depositing polysilicon on silicon dioxide.

Advantage of the present invention is: the present invention is simple in structure, takies chip area little in SOI/CMOS integrated circuit, easy to use, can effectively improve the ESD tolerance level of integrated circuit.This structure is compared with traditional SOI technique esd protection device, applied range, as plug-and-play circuit, mixed-voltage compatible port, power supply-between esd protection.

Accompanying drawing explanation

Fig. 1 is device architecture profile of the present invention.

Fig. 2 is the circuit theory diagrams of Fig. 1.

Fig. 3 is that the present invention is for the PMOS device profile map between port and ground GND.

Fig. 4 is the circuit theory diagrams of Fig. 3.

Fig. 5 is that the present invention is for the PMOS device profile map between port and power vd D.

Fig. 6 is the circuit theory diagrams of Fig. 5.

Embodiment

Below in conjunction with drawings and Examples, the present invention is described further.

As Fig. 1, shown in 2, the present invention includes a N-type substrate PMOS tubular construction, described N-type substrate PMOS tubular construction comprises: grid (ploy grid) 5, diffusion region, P+ source 4, P+ leak diffusion region 6, N trap 7, silicon dioxide isolated area 3, oxygen buried layer (BOX) 2 and silicon substrate 1, described oxygen buried layer 2 is positioned on silicon substrate 1, and diffusion region, described P+ source 4, P+ leak diffusion region 6, N trap 7 and silicon dioxide isolated area 3 and be positioned on oxygen buried layer 2; Described N trap 7 leaks between diffusion region 6 in diffusion region 4, P+ source and P+, between 4 to the N traps 7 of diffusion region, P+ source, forms parasitic diode D1, and silicon dioxide isolated area 3 surrounds diffusion region 4, described P+ source and P+ leaks diffusion region 6; Described grid 5 is positioned on N trap 7; The exit of diffusion region, described P+ source 4 is the source of PMOS pipe, and the exit that P+ leaks diffusion region 6 is the drain terminal of PMOS pipe; Between the source of grid 5 and PMOS pipe, connect clamp circuit; The parasitic diode D1 of PMOS pipe source setovers to N trap 7; The grid 5 of PMOS pipe is used clamp circuit to setover.

As Fig. 3, shown in 4, when being used in while carrying out esd protection between input pressure welding point and ground, the source of PMOS pipe connects input pressure welding point by metallic aluminium, drain terminal by metallic aluminium connect GND, between grid and source, connect clamp circuit.The current potential of N trap 7 is definite with parasitic diode D1 by diffusion region, P+ source 4, and clamp circuit guarantees that PMOS pipe is in off state when under normal mode of operation.

As Fig. 5, shown in 6, be used in while carrying out esd protection between input pressure welding point and power vd D, the source of PMOS pipe connects power vd D by metallic aluminium, and drain terminal is connected and is inputted pressure welding point by metallic aluminium, between grid and source, connects clamp circuit.The current potential of N trap 7 is definite with parasitic diode D1 by diffusion region, P+ source 4, and clamp circuit guarantees that PMOS pipe is in off state when under normal mode of operation.

Grid 5 depositing polysilicon on silicon dioxide; It is B Implanted element in silicon that diffusion region 4, P+ source and P+ leak diffusion region 6 materials, and its degree of depth arrives oxygen buried layer 2; N trap 7 materials for injecting P elements in silicon, and its degree of depth arrives oxygen buried layer 2; Silicon dioxide isolated area 3 materials are silicon dioxide, and its degree of depth arrives oxygen buried layer 2; Oxygen buried layer material is silicon dioxide; Substrate 1 material is highly doped monocrystalline silicon, is positioned at the below of total.

Operation principle of the present invention is as follows: first, the source of PMOS pipe (diffusion region, P+ source 4) voltage raises, the substrate N trap 7 of PMOS pipe is followed source voltage terminal, when source-drain terminal voltage difference of PMOS pipe reaches emitter-collector breakdown voltage open base of parasitic lateral PNP, parasitic lateral PNP starts working, until PMOS pipe source-drain terminal electric current surpasses certain value, PMOS pipe damages.

In sum, the present invention uses enhancement mode PMOS pipe common in PD SOI technique, does not need to do substrate contact, uses the P+/N trap parasitic diode D1 of PMOS pipe source to setover to N trap; The grid 5 of PMOS pipe is used clamp circuit to setover.This structure is utilized parasitic lateral PNP, improves the esd protection ability of device.

Claims

1. the esd protection structure based on PD SOI technique, it is characterized in that: comprise a N-type substrate PMOS tubular construction, described N-type substrate PMOS tubular construction comprises that grid (5), diffusion region, P+ source (4), P+ leak diffusion region (6), N trap (7), silicon dioxide isolated area (3), oxygen buried layer (2) and silicon substrate (1), described oxygen buried layer (2) is positioned on silicon substrate (1), and diffusion region, described P+ source (4), P+ leak diffusion region (6), N trap (7) and silicon dioxide isolated area (3) and be positioned on oxygen buried layer (2); Described N trap (7) is positioned at diffusion region, P+ source (4) and P+ leaks between diffusion region (6), in diffusion region, P+ source (4), between N trap (7), form parasitic diode (D1), silicon dioxide isolated area (3) surrounds diffusion region, described P+ source (4) and P+ leaks diffusion region (6); Described grid (5) is positioned on N trap (7); The exit of diffusion region, described P+ source (4) is the source of PMOS pipe, and the exit that P+ leaks diffusion region (6) is the drain terminal of PMOS pipe; Between grid (5) and the source of PMOS pipe, connect clamp circuit; The parasitic diode (D1) of PMOS pipe source is setovered to N trap (7); The grid of PMOS pipe (5) is used clamp circuit to setover;

When being used in while carrying out esd protection between input pressure welding point and ground, the source of PMOS pipe connects input pressure welding point by semiconductor alloy aluminium, drain terminal is connected with ground (GND) by semiconductor alloy aluminium, the current potential of N trap (7) is determined by diffusion region, P+ source (4) and parasitic diode (D1), clamp circuit guarantees that PMOS pipe is in off state when under normal mode of operation;

When being used in while carrying out esd protection between input pressure welding point and power supply (VDD), the source of PMOS pipe connects power supply (VDD) by semiconductor alloy aluminium, drain terminal connects input pressure welding point by semiconductor alloy aluminium, the current potential of N trap (7) is determined by diffusion region, P+ source (4) and parasitic diode (D1), clamp circuit guarantees that PMOS pipe is in off state when under normal mode of operation;

Described silicon substrate (1) material is highly doped monocrystalline silicon; Oxygen buried layer (2) material is silicon dioxide; It is B Implanted element in silicon that diffusion region, P+ source (4) and P+ leak diffusion region (6) material, and the degree of depth arrives oxygen buried layer (2); N trap (7) material for injecting P elements in silicon, and the degree of depth arrives oxygen buried layer (2); Silicon dioxide isolated area (3) material is silicon dioxide, and the degree of depth arrives oxygen buried layer (2); Grid (5) is depositing polysilicon on silicon dioxide.