CN103515944B - Using the Power Clamp for ESD protections between power supply and ground of dual-channel technology - Google Patents
Using the Power Clamp for ESD protections between power supply and ground of dual-channel technology Download PDFInfo
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- CN103515944B CN103515944B CN201310477495.2A CN201310477495A CN103515944B CN 103515944 B CN103515944 B CN 103515944B CN 201310477495 A CN201310477495 A CN 201310477495A CN 103515944 B CN103515944 B CN 103515944B
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Abstract
The present invention relates to a kind of Power Clamp for ESD protections between power supply and ground of employing dual-channel technology.Using technical scheme be：Including the detection circuit of RC triggerings, R1 and C constitutes ESD observation circuits, put between vdd and vss, after phase inverter I is placed on RC observation circuits, input is connected with Filter nodes, and output end is connected with phase inverter II, the output end of phase inverter II is connected with the grid of PMOS1, the grid ground connection of NMOS1, the leakage of NMOS1 are connected with the leakage of PMOS1 and then connect the grid of BIGFET, and the grid of BIGFET are grounded by a resistance R simultaneously.The new Power clamp of the present invention adopt dual-channel technology, RC time constants to need only to 10 50ns, can greatly reduce the chip area of Power clamp.
Description
Technical field
The present invention relates to can be used for the Power Clamp of ESD protections between the power supply and ground of 65nm semiconductor technologies, especially
It is related to a kind of Power clamp of the resistance capacitance triggering for saving area（Clamp circuit between power supply and ground）.
Background technology
Semiconductor processing technology can produce the transistor of minimal type.These micro-transistors have very thin oxide isolated
Layer, which is easily damaged by static electricity.Therefore, SC is needed when hand-held these semiconductor devices.
Static discharge（ESD, Electron Static Discharge）Be when the pin suspension joint of an integrated circuit,
A large amount of electrostatic charges pour into the instantaneous process of integrated circuit from outside to inside, and whole process about takes 100ns to 1us.In integrated electricity
The high pressure of hundreds if not thousands of volts can be produced during the static discharge on road, by the gate oxide breakdown of input stage in integrated circuit.
The model of ESD event mainly has four kinds：Human body discharge's model (HBM), mechanical discharging model (MM), device charging mould
Type (CDM) and electric field induction model (FIM).For general IC products, typically will be through human body discharge's model, machine
The test of tool discharging model and device charge model.In order to bear so high static discharge voltage, integrated circuit is produced
Product are generally had to using with high-performance, the electrostatic discharge protector of high tolerance.
The Power clamp of general RC triggerings, are designed to control NMOS based on the control circuit of RC time constants
The conducting of device, the drain electrode (drain) of the nmos device are connected to VDD, and its source electrode (source) is connected to VSS.When there is ESD electric
Extrude it is existing across between VDD and VSS power lines when, the nmos device can be switched on and that one is formed between VDD and VSS is temporary transient
The low impedance path of property, esd discharge electric current are released by the nmos device.Using this ESD clamped circuit, effectively can prevent
Shield esd discharges of the VDD to VSS.
The Power clamp of general RC triggerings, effectively release ESD electric currents to reach, and RC time constants need to set
0.5us-1us is calculated as, so big RC time constants are needed than larger electric capacity and resistance, then in IC Layout
When, R and C is needed than larger chip area, causes to waste.
The content of the invention
It is an object of the invention to provide a kind of Power for ESD protections between power supply and ground of employing dual-channel technology
Clamp, the RC time constants of this new Power clamp can arrange very little, as long as ESD is released by detecting esd pulse
Electric current, can greatly reduce the chip area of Power clamp.
The technical solution used in the present invention is：Using the Power for ESD protections between power supply and ground of dual-channel technology
Clamp, including the detection circuit for being provided with RC triggerings between vdd and vss, described detection circuit includes PMOS1, NMOS1, electricity
Resistance R2 and BigFET, and there is Filter nodes, INV1OUT nodes, INV2OUT nodes and BigFET grid nodes；R1 and C is constituted
ESD observation circuits, put between vdd and vss, after phase inverter I is placed on RC observation circuits, the input of phase inverter I and
Filter nodes are connected, and output end is connected with phase inverter II, and the output end of phase inverter II is connected with the grid of PMOS1, the grid of NMOS1
Ground connection, the leakage of NMOS1 are connected with the leakage of PMOS1 and then connect the grid of BIGFET, and the grid of BIGFET are grounded by resistance R2 simultaneously.
The Power Clamp for ESD protections between power supply and ground of above-mentioned employing dual-channel technology, it is described
For reaching the initial stage in esd pulse, PMOS1 is opened PMOS1, and BigFET grid nodes are high voltage, and it is electric that BigFET opens the ESD that releases
Stream.
The Power Clamp for ESD protections between power supply and ground of above-mentioned employing dual-channel technology, it is described
NMOS1 remains in that BigFET opens ESD electric currents of releasing for reaching in pulse after having crossed RC time constants.
The Power Clamp for ESD protections between power supply and ground of above-mentioned employing dual-channel technology, described resistance
In the case that R2 is for the electricity on circuit is normal, BigFET grid nodes voltage is made for low level, BigFET is closed, and will not be produced leakage
Electricity.
The Power Clamp for ESD protections between power supply and ground of above-mentioned employing dual-channel technology, RC detection circuit
RC time constants be set to 10-50ns.
The Power Clamp for ESD protections between power supply and ground of above-mentioned employing dual-channel technology, RC detection circuit
RC time constants be set to 20ns.
The invention has the beneficial effects as follows：The Power clamp of the present invention adopt dual-channel technology, and RC time constants are only
10-50ns is needed, the chip area of Power clamp can be greatly reduced.The RC detection circuits of the present invention adopt binary channels, and one
Individual passage is used for maintaining BigFET conducting 0.5us-1us with conducting BigFET, ESD electric currents of releasing, another passage is come, from
And ESD whole electric currents of effectively can releasing.
Description of the drawings
Fig. 1 is the structural representation of the present invention.
In the case of Fig. 2 is spice emulation HBM 2000V esd pulses, the unlatching situation of the Power clamp of the present invention.
Specific embodiment
As shown in figure 1, a kind of Power Clamp for ESD protections between power supply and ground of employing dual-channel technology, bag
Include in VDD（1）And VSS（2）Between be provided with the detection circuit of RC triggerings, described detection circuit includes PMOS1（3）、NMOS1
（4）, resistance R2（5）And BigFET（6）, and there is Filter nodes（ 7）, INV1OUT nodes（8）, INV2OUT nodes（9）With
BigFET grid nodes（10）；R1 and C constitutes ESD observation circuits, is placed on VDD（1）And VSS（2）Between, phase inverter I（11）It is placed on
After RC observation circuits, phase inverter I（11）Input and Filter nodes（7）It is connected, output end and phase inverter II（12）Phase
Even, phase inverter II（12）Output end and PMOS1（3）Grid be connected, NMOS1（4）Grid ground connection, NMOS1（4）Leakage and
PMOS1（3）Leakage be connected then meet BIGFET（6）Grid, BIGFET（6）Grid simultaneously pass through resistance R2（5）Ground connection.
As shown in figure 1, Filter nodes are RC network node, after detecting that HBM pulses, HBM pulses have come, this
Node exports a positive voltage.INV1OUT nodes are I output node of phase inverter, and INV2OUT nodes are II output node of phase inverter.
When esd pulse applies between vdd and vss, RC detects electric circuit inspection to signal, and Filter nodes are low-voltage,
INV1OUT nodes are high voltage, and INV2OUT is low-voltage, and PMOS1 is opened, and BigFET grid nodes are high voltage, and BigFET is opened
Conduct ESD current.
After RC time constants 20ns, Filter nodes are high voltage, and INV1OUT nodes are low-voltage, and INV2OUT is
High voltage, PMOS1 are closed, but NMOS1 is also switched off, and BigFET grid nodes are also high voltage, and BigFET continues on the ESD that releases
Electric current.
The Power Clamp for ESD protections between power supply and ground of employing dual-channel technology as shown in Figure 1, it is described
PMOS1（3）Effect be esd pulse reach the initial stage, PMOS1（3）Open, BigFET grid nodes（10）For high voltage,
BigFET（6）Unlatching is released ESD electric currents.
The Power Clamp for ESD protections between power supply and ground of employing dual-channel technology as shown in Figure 1, it is described
NMOS1（4）Effect be esd pulse reach, after having crossed RC time constants 20ns, remain in that BigFET（6）Open
Release ESD electric currents.
The Power Clamp for ESD protections between power supply and ground of employing dual-channel technology as shown in Figure 1, it is described
Resistance R2（5）Effect be on circuit is normal electricity（Power ON）In the case of, make BigFET grid nodes（10）Electricity
Press as low-voltage, BigFET（6）Close, electric leakage will not be produced.
As shown in figure 1, using the Power Clamp for ESD protections between power supply and ground of dual-channel technology, this circuit
RC time constants be only 20ns or so, layout design area can be greatly reduced.
As shown in Fig. 2 using the voltage of each node under the HBM2000V pulses of Cadence sprectre emulation gained
And current conditions.Under HBM pulses, in 0-0.6us time intervals, BigFET gate voltages are high level（More than 0.5V）,
BigFET opens ESD electric currents of releasing.The whole electric currents of BigFET current drains can be seen.
Claims (2)
1., using the power clamping circuit for ESD protections between power supply and ground of dual-channel technology, power vd D is included in（1）
With ground VSS（2）Between be provided with RC triggering detection circuit, it is characterised in that：Described detection circuit includes PMOS1（3）、
NMOS1（4）, resistance R2（5）And BigFET（6）, and there is Filter nodes（7）, INV1OUT nodes（8）, INV2OUT nodes
（9）With BigFET gate nodes（10）；R1 and C constitutes the RC observation circuits of ESD, is placed on VDD（1）And VSS（2）Between, wherein
Filter nodes（7）For R1 and C junctions, phase inverter I（11）After being placed on RC observation circuits, phase inverter I（11）Input
With Filter nodes（7）It is connected, output end and phase inverter II（12）Input be connected, phase inverter II（12）Output end and
PMOS1（3）Grid be connected, NMOS1（4）Grounded-grid, NMOS1（4）Drain electrode and PMOS1（3）Drain electrode be connected then
Meet BigFET（6）Grid, PMOS1（3）Source electrode meet power supply, NMOS1（4）Source ground, BigFET（6）Grid simultaneously
By resistance R2（5）Ground connection；
Described PMOS1（3）For reaching initial stage, PMOS1 in esd pulse（3）Open, BigFET gate nodes（10）For high electricity
Pressure, BigFET（6）Unlatching is released ESD electric currents；
Described NMOS1（4）For reaching in esd pulse, after having crossed the RC time constants of RC observation circuits, remain in that
BigFET（6）Unlatching is released ESD electric currents；
Described resistance R2（5）In the case of for the electricity on circuit is normal, BigFET gate nodes are made（10）Voltage is low electricity
It is flat, BigFET（6）Close, electric leakage will not be produced；
The RC time constants of RC observation circuits are set to 10-50ns.
2. as claimed in claim 1 using the power clamping circuit for ESD protections between power supply and ground of dual-channel technology,
It is characterized in that：The RC time constants of RC observation circuits are set to 20ns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310477495.2A CN103515944B (en) | 2013-10-14 | 2013-10-14 | Using the Power Clamp for ESD protections between power supply and ground of dual-channel technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310477495.2A CN103515944B (en) | 2013-10-14 | 2013-10-14 | Using the Power Clamp for ESD protections between power supply and ground of dual-channel technology |
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| Publication Number | Publication Date |
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| CN103515944A CN103515944A (en) | 2014-01-15 |
| CN103515944B true CN103515944B (en) | 2017-03-29 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332976B (en) * | 2014-11-20 | 2017-05-17 | 辽宁大学 | High voltage compatible with electrostatic discharge power supply clamp circuit of integrated circuit |
| CN106300311A (en) * | 2016-08-27 | 2017-01-04 | 中科院微电子研究所昆山分所 | A kind of RC power supply clamp based on TVS diode |
| CN108880212B (en) * | 2018-06-30 | 2021-07-20 | 唯捷创芯(天津)电子技术股份有限公司 | Surge-proof power supply clamping circuit, chip and communication terminal |
| CN113192848B (en) * | 2021-04-28 | 2022-03-11 | 长江存储科技有限责任公司 | Packaging method and packaging structure of integrated circuit |
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|---|---|---|---|---|
| CN1501757A (en) * | 2002-11-15 | 2004-06-02 | 华邦电子股份有限公司 | Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor |
| CN1658388A (en) * | 2004-02-18 | 2005-08-24 | 富士通株式会社 | Electrostatic discharge protection circuit |
| CN101908759A (en) * | 2009-06-08 | 2010-12-08 | 财团法人工业技术研究院 | ESD (Electrostatic Discharge) clamp circuit |
| CN102723702A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Dual-feedback power supply clamp used for on-chip electrostatic discharge protection |
| CN102820292A (en) * | 2011-06-06 | 2012-12-12 | 索尼公司 | Semiconductor integrated circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10349405A1 (en) * | 2003-10-21 | 2005-05-25 | Austriamicrosystems Ag | Active protection circuitry |
| US7545614B2 (en) * | 2005-09-30 | 2009-06-09 | Renesas Technology America, Inc. | Electrostatic discharge device with variable on time |
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2013
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501757A (en) * | 2002-11-15 | 2004-06-02 | 华邦电子股份有限公司 | Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor |
| CN1658388A (en) * | 2004-02-18 | 2005-08-24 | 富士通株式会社 | Electrostatic discharge protection circuit |
| CN101908759A (en) * | 2009-06-08 | 2010-12-08 | 财团法人工业技术研究院 | ESD (Electrostatic Discharge) clamp circuit |
| CN102820292A (en) * | 2011-06-06 | 2012-12-12 | 索尼公司 | Semiconductor integrated circuit |
| CN102723702A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Dual-feedback power supply clamp used for on-chip electrostatic discharge protection |
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| CN103515944A (en) | 2014-01-15 |
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Effective date of registration: 20190305 Address after: 210019 Building No. 18, Jialing Jiangdong East Street, Jianye District, Nanjing City, Jiangsu Province, 3, 16 floors Patentee after: Nanjing Wencai Industry Intelligent Research Institute Co., Ltd. Address before: 110000 58 Shenbei New Area Road South, Shenyang, Liaoning. Patentee before: Liaoning University |