CN113053856B - Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device - Google Patents
Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device Download PDFInfo
- Publication number
- CN113053856B CN113053856B CN201911368420.4A CN201911368420A CN113053856B CN 113053856 B CN113053856 B CN 113053856B CN 201911368420 A CN201911368420 A CN 201911368420A CN 113053856 B CN113053856 B CN 113053856B
- Authority
- CN
- China
- Prior art keywords
- silicon chip
- resistor
- chip resistor
- metal
- coating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 177
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 177
- 239000010703 silicon Substances 0.000 title claims abstract description 177
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 claims description 59
- 239000011247 coating layer Substances 0.000 claims 23
- 239000010410 layer Substances 0.000 claims 11
- 238000009825 accumulation Methods 0.000 abstract description 3
- 238000012360 testing method Methods 0.000 description 21
- 238000010586 diagram Methods 0.000 description 9
- 238000013461 design Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method, a structure and a power semiconductor device for preventing a silicon chip resistor from generating partial discharge failure as a gate resistor, belongs to the technical field of high-voltage power modules, and is used for solving the problem of partial discharge failure caused by the silicon chip resistor as the gate resistor. The technical scheme adopted is as follows: the upper surface and the lower surface of the silicon chip resistor are at the same level by binding the line or optimizing the lining plate or optimizing the silicon chip resistor, so that the whole silicon chip resistor is at the same level. The method, the structure and the power semiconductor device have the advantages of being simple and convenient to operate, avoiding partial discharge failure of the silicon chip resistor serving as a gate resistor, eliminating charge accumulation, improving working reliability and the like.
Description
Technical Field
The invention mainly relates to the technical field of high-voltage power modules, in particular to a method, a structure and a power semiconductor device for preventing a silicon chip resistor from generating partial discharge failure as a gate resistor.
Background
In power semiconductor devices, in order to increase the current level of a module, it is common practice to adopt a parallel connection mode of a chip and a lining board. Thus, the current sharing problem of the chip and the lining board level needs to be solved. The dynamic current sharing capability of the lining board level can be improved through the built-in gate resistance on the lining board.
There are two types of gate resistors commonly used, one is a common resistor and one is a silicon resistor. Both resistors have the problem of influencing the partial discharge test result of the power semiconductor module. For the common resistor, the problem of poor partial discharge test results can be improved and solved by optimizing the encapsulation process. The reason that the silicon chip resistor causes poor partial discharge test results is different from the common resistor, and the silicon chip resistor is difficult to optimize by improving the encapsulation process.
The silicon chip resistor is formed by doping, so that a certain resistivity exists on the silicon chip, the size of the resistor can be adjusted by controlling the doping concentration, the resistor can be welded on a lining plate together with a power chip when in use, the resistor is very suitable for being used as a gate resistor on the lining plate, the structure of the resistor is shown in figure 1, the resistor comprises a bonding area 101, and the back surface of the resistor is a welding area. The equivalent circuit is shown in fig. 2, the resistor R1 plus R2 is usually the gate resistance value required by the device, and a larger resistor exists between the upper surface and the lower surface of the silicon chip resistor during actual measurement, which can be equivalent to a diode connected in series with the large resistor R3.
According to the international standard of the IEC 1287 semiconductor module partial discharge test, the test is shown in fig. 3, and the module can short-circuit the power terminal and the signal terminal of the module together when the module performs the partial discharge test so as to ensure that the working circuit and the control circuit related in the operation of the module are in the same potential. When there is a silicon chip resistor in the module, its equivalent circuit for testing partial discharge is shown in fig. 4.
When the power semiconductor device module performs partial discharge test, both the gate terminal and the driving terminal are shorted with the power terminal, and a higher voltage is applied. For example, 3300V is taken as an example, when a voltage of 6kV is applied, the lower surfaces of the silicon resistors are not at the same potential, so that the partial discharge value of the silicon resistor positions becomes high.
In view of the effect of the silicon chip resistor on the partial discharge capability of the power semiconductor device module when the silicon chip resistor is used as the gate resistor, a scheme is urgently required to be provided for solving the problem of partial discharge failure caused by the silicon chip resistor.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides a method, a structure and a power semiconductor device which are simple and convenient to operate and capable of keeping the whole potential of a silicon chip resistor at the same potential and preventing the silicon chip resistor from generating partial discharge failure as a gate electrode resistor.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method for preventing the silicon chip resistor from generating partial discharge failure as gate electrode resistor features that the electric potential of suspended end in the equivalent circuit of silicon chip resistor is controlled to make it at same electric potential with the whole of silicon chip resistor.
As a further improvement of the above technical scheme:
when the potential control is performed, the potentials of the upper surface and the lower surface of the resistor of the silicon chip are controlled to be at the same level.
When the potential control is performed, the metal-coated layer of the silicon chip resistor is directly connected with the upper surface of the silicon chip resistor, or the metal-coated layer connected with the upper surface of the silicon chip resistor is connected with the metal-coated layer of the silicon chip resistor, so that the potentials of the upper surface and the lower surface of the silicon chip resistor are at the same level.
The metal-clad layer of the silicon chip resistor is directly connected with the upper surface of the silicon chip resistor through a binding line, or the metal-clad layer connected with the upper surface of the silicon chip resistor is connected with the metal-clad layer of the silicon chip resistor through a binding line.
The metal-clad layer connected with the upper surface of the silicon chip resistor and the metal-clad layer where the silicon chip resistor is positioned are designed into a whole, so that the potentials of the upper surface and the lower surface of the silicon chip resistor are at the same level.
And a process through hole is arranged on the silicon chip resistor to connect the upper surface and the lower surface of the silicon chip resistor so that the potentials of the upper surface and the lower surface of the silicon chip resistor are at the same level.
The invention further discloses a structure for preventing the silicon chip resistor from generating partial discharge failure as the gate resistor, which comprises a binding line, wherein the binding line is used for directly connecting a metal-coated layer where the silicon chip resistor is positioned with the upper surface of the silicon chip resistor or connecting a metal-coated layer connected with the upper surface of the silicon chip resistor with the metal-coated layer where the silicon chip resistor is positioned, so that the electric potentials of the upper surface and the lower surface of the silicon chip resistor are at the same level.
The invention also discloses a power semiconductor device, which comprises a power semiconductor chip, a silicon chip resistor, a first binding line, a second binding line, a third binding line, a first metal-clad layer, a second metal-clad layer, a third metal-clad layer and a fourth metal-clad layer, wherein the power semiconductor chip is arranged on the first metal-clad layer, the silicon chip resistor is arranged on the third metal-clad layer, the first metal-clad layer is connected with the second metal-clad layer through the first binding line, the first upper surface end of the silicon chip resistor is connected with the second metal-clad layer through the second binding line, the second upper surface end of the silicon chip resistor is connected with the fourth metal-clad layer through the third binding line, and the power semiconductor device further comprises a fourth binding line for connecting the third metal-clad layer with the second metal-clad layer or the fourth metal-clad layer.
The invention also discloses a power semiconductor device, which comprises a power semiconductor chip, a silicon chip resistor, a first binding line, a second binding line, a third binding line, a first metal-clad layer, a second metal-clad layer, a third metal-clad layer and a fourth metal-clad layer, wherein the power semiconductor chip is arranged on the first metal-clad layer, the silicon chip resistor is arranged on the third metal-clad layer, the first metal-clad layer is connected with the second metal-clad layer through the first binding line, the first upper surface end of the silicon chip resistor is connected with the second metal-clad layer through the second binding line, the second upper surface end of the silicon chip resistor is connected with the fourth metal-clad layer through the third binding line, and the second metal-clad layer or the fourth metal-clad layer and the third metal-clad layer are of an integrated structure.
The invention also discloses a power semiconductor device, which comprises a power semiconductor chip and a silicon chip resistor, wherein the silicon chip resistor is used as a gate resistor of the power semiconductor chip, and a process through hole for connecting the upper surface and the lower surface of the silicon chip resistor is arranged on the silicon chip resistor.
Compared with the prior art, the invention has the advantages that:
(1) The method for preventing the silicon chip resistor from generating partial discharge failure as the gate resistor can keep the potential of the silicon chip resistor at the same potential, thereby solving the problem of partial discharge failure generated by adopting the silicon chip resistor as the gate resistor, eliminating charge accumulation at the silicon chip resistor, improving the reliability and being popularized to the design of middle-low voltage power module packaging and gate driving circuits.
(2) The method for preventing the silicon chip resistor from generating partial discharge failure as the gate electrode resistor adopts modes of binding wires or optimizing lining plates or process through holes and the like to keep the whole potential of the silicon chip resistor at the same potential, and the corresponding method is simple and convenient to operate and is realized.
(3) According to the power semiconductor device, the upper surface and the lower surface of the silicon chip resistor are communicated in a mode of binding wires or optimizing a lining plate or optimizing a silicide resistor, so that the whole silicon chip resistor is at the same potential level, partial discharge failure of the silicon chip resistor is prevented, and the product yield, the product reliability and the service life are improved; in addition, the silicon chip resistor is used as the gate resistor, so that the current sharing characteristic inside the power semiconductor device module can be optimized, and the current passing capability and reliability of the module can be improved.
Drawings
Fig. 1 is a schematic diagram of a prior art silicon chip resistor.
Fig. 2 is a schematic diagram of an equivalent circuit of a silicon resistor in the prior art.
FIG. 3 is a schematic diagram of a prior art module partial discharge test circuit connection.
Fig. 4 is a schematic diagram of an equivalent circuit of an actual partial discharge in the prior art.
Fig. 5 is a structural equivalent circuit diagram of the present invention.
Fig. 6 is a schematic diagram of a structure employing binding lines according to the present invention.
FIG. 7 is a schematic view of the structure of the optimized lining board according to the present invention.
Fig. 8 is a schematic structural diagram corresponding to the first scheme in the discharge test of the present invention.
Fig. 9 is a schematic structural diagram corresponding to the second scheme in the discharge test of the present invention.
FIG. 10 is a diagram of IEC 1287 test standards according to the invention.
Legend description: 1. a power semiconductor chip; 2. silicon chip resistance; 21. a first upper surface end; 22. a second upper surface end; 3. coating a metal layer; 31. a first metal-clad layer; 32. a second metal-clad layer; 33. a third metal-clad layer; 34. a fourth metal-clad layer; 4. binding the wire; 41. a first binding line; 42. a second binding line; 43. a third binding line; 44. a fourth binding line; 101. and a bonding region.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific examples.
As shown in fig. 5-8, in the method for preventing the silicon resistor from generating partial discharge failure as the gate resistor in this embodiment, in the silicon resistor 2, the potential control is performed on the suspended end of the equivalent circuit of the silicon resistor 2, so that the suspended end and the whole body of the silicon resistor 2 are at the same potential. Specifically, when the potential control is performed, the potentials of the upper surface and the lower surface of the silicon chip resistor 2 are controlled to be at the same level, so that the whole of the silicon chip resistor 2 is at the same potential, and the corresponding equivalent circuit is shown in fig. 5. Wherein R3 is a resistor with more than two orders of magnitude relative to R1 and R2, and an equivalent diode exists in the middle, so that the Bottom end and the Gate end or Driver end in FIG. 5 are short-circuited, the influence on the Gate resistance is negligible, but the potential of the silicon chip resistor 2 can be kept at the same potential, thereby solving the problem of partial discharge failure caused by adopting the silicon chip resistor 2 as a Gate resistor, eliminating charge accumulation at the silicon chip resistor 2, improving the reliability, and being popularized to the design of middle-low voltage power module packages and Gate driving circuits.
In this embodiment, when the potential control is performed, the metal-clad layer of the silicon resistor 2 is directly connected to the upper surface of the silicon resistor 2, or the metal-clad layer connected to the upper surface of the silicon resistor 2 is connected to the metal-clad layer of the silicon resistor 2, so that the potentials of the upper and lower surfaces of the silicon resistor 2 are at the same level. Specifically, as shown in fig. 6, the metal-clad layer where the silicon chip resistor 2 is located is directly connected with the upper surface of the silicon chip resistor 2 through a binding line, or the metal-clad layer connected with the upper surface of the silicon chip resistor 2 is connected with the metal-clad layer where the silicon chip resistor 2 is located through a binding line; the method is simple and convenient to operate and easy to realize by binding the wires. In other embodiments, the design of the lining plate may be optimized, for example, the metal-clad layer connected to the upper surface of the silicon resistor 2 is designed to be integrated with the metal-clad layer where the silicon resistor 2 is located, so that the electric potentials of the upper and lower surfaces of the silicon resistor 2 are at the same level, as shown in fig. 7. It will be appreciated that the silicon resistor 2 may be optimized, for example, by providing process vias in the silicon resistor 2 to interconnect the upper and lower surfaces so that the upper and lower surfaces of the silicon resistor 2 are at the same level.
The invention also correspondingly discloses a structure for preventing the silicon chip resistor 2 from generating partial discharge failure as the gate resistor, which comprises a binding wire, wherein the binding wire is used for directly connecting a metal-coated layer of the silicon chip resistor 2 with the upper surface of the silicon chip resistor 2 or connecting a metal-coated layer connected with the upper surface of the silicon chip resistor 2 with the metal-coated layer of the silicon chip resistor 2 so as to enable the electric potentials of the upper surface and the lower surface of the silicon chip resistor 2 to be at the same level, and the structure is simple and easy to realize.
As shown in fig. 6, the invention also discloses a power semiconductor device, which comprises a power semiconductor chip 1, a silicon chip resistor 2, a binding line 4 and a metal-clad layer 3, wherein the binding line 4 comprises a first binding line 41, a second binding line 42 and a third binding line 43; the metal clad layer 3 includes a first metal clad layer 31, a second metal clad layer 32, a third metal clad layer 33, and a fourth metal clad layer 34; the power semiconductor chip 1 is arranged on the first metal-clad layer 31, the silicon chip resistor 2 is arranged on the third metal-clad layer 33, the first metal-clad layer 31 is connected with the second metal-clad layer 32 through a first binding line 41, the first upper surface end 21 on the silicon chip resistor 2 is connected with the second metal-clad layer 32 through a second binding line 42, the second upper surface end 22 on the silicon chip resistor 2 is connected with the fourth metal-clad layer 34 through a third binding line 43, and the power semiconductor chip further comprises a fourth binding line 44 for connecting the third metal-clad layer 33 with the second metal-clad layer 32 or the fourth metal-clad layer 34. According to the power semiconductor device, the upper surface and the lower surface of the silicon chip resistor 2 are communicated in a wire binding mode, so that the whole silicon chip resistor 2 is at the same potential level, partial discharge failure of the silicon chip resistor 2 is prevented, and the product yield, the product reliability and the service life are improved. In addition, the silicon chip resistor 2 is used as a gate resistor, so that the current sharing characteristic inside the power semiconductor device module can be optimized, and the current passing capability and reliability of the module can be improved.
As shown in fig. 9, in a specific application example, three power semiconductor chips 1 are adopted in parallel, and the structure of the silicon chip resistor 2 is optimized through binding wires. Wherein the power semiconductor chip 1 is soldered or sintered on the first metallization layer 31, connected to the second metallization layer 32 by means of a first bonding wire 41, and connected to the first upper surface end 21 of the silicon resistor 2 by means of a second bonding wire 42. The silicon chip resistor 2 is welded or sintered on the third metal-clad layer 33, and the third binding wire 43 connects the second upper surface end 22 of the silicon chip resistor 2 with the fourth metal-clad layer 34, wherein the first upper surface end 21 and the second upper surface end 22 respectively represent the inflow and outflow surfaces of current; finally, the third metal-clad layer 33 and the second metal-clad layer 32 or the fourth metal-clad layer 34 are connected through the fourth binding line 44, so as to ensure that the whole silicon chip resistor 2 is at the same potential.
With reference to test standard IEC 1287, a partial discharge test will be performed on a 1700V or higher voltage class power semiconductor device module product, the test standard of which is shown in fig. 10.
Partial discharge tests were performed on two schemes, no fourth bond line 44 (scheme 1 as shown in fig. 8) and a fourth bond line 44 (scheme 2 as shown in fig. 9), with the test results shown in table 1:
Table 1 sample test results:
| Sample number | Partial discharge @6kV | Partial discharge @2.6kV | Test results |
| #1 | 136 | 8 | Pass |
| #2 | 14 | 13 | Fail |
| #3 | 125 | 7 | Pass |
| #4 | 115 | 8 | Pass |
| #5 | 117 | 8 | Pass |
| #6 | 131 | 2 | Pass |
| #7 | 127 | 2 | Pass |
| #8 | 133 | 2 | Pass |
| #9 | 131 | 2 | Pass |
| #10 | 2 | 1 | Pass |
| #11 | 2.3 | 1 | Pass |
| #12 | 3 | 1 | Pass |
Wherein #1- #9 corresponds to no fourth binding line 44 added, # 10- #12 added fourth binding line 44. It can be seen that the above-described scheme of adding the fourth bonding wire 44 can significantly improve the passing rate of the partial discharge test.
In general, it is necessary to place the entire silicon resistor 2 at a potential during the partial discharge test according to the IEC 1287 standard to ensure that the silicon resistor 2 does not undergo partial discharge failure. Besides the mode of externally shorting the silicon resistor 2, the internal structure of the silicon resistor 2 can be adjusted.
The invention further discloses a power semiconductor device, which comprises a power semiconductor chip 1, a silicon chip resistor 2, a first binding line 41, a second binding line 42, a third binding line 43, a first metal-coated layer 31, a second metal-coated layer 32, a third metal-coated layer 33 and a fourth metal-coated layer 34, wherein the power semiconductor chip 1 is arranged on the first metal-coated layer 31, the silicon chip resistor 2 is arranged on the third metal-coated layer 33, the first metal-coated layer 31 is connected with the second metal-coated layer 32 through the first binding line 41, a first upper surface end 21 on the silicon chip resistor 2 is connected with the second metal-coated layer 32 through the second binding line 42, a second upper surface end 22 on the silicon chip resistor 2 is connected with the fourth metal-coated layer 34 through the third binding line 43, and the second metal-coated layer 32 or the fourth metal-coated layer 34 and the third metal-coated layer 33 are of an integrated structure, so that the upper surface and the lower surface of the silicon chip resistor 2 are connected, the whole resistor 2 is at the same potential, and the problem of partial discharge failure of the silicon chip resistor 2 is prevented.
The invention also discloses a power semiconductor device, which comprises a power semiconductor chip 1 and a silicon chip resistor 2, wherein the silicon chip resistor 2 is used as a gate resistor of the power semiconductor chip 1, and a process through hole for connecting the upper surface and the lower surface of the silicon chip resistor 2 is arranged on the silicon chip resistor 2, so that the upper surface and the lower surface of the silicon chip resistor 2 are connected, the whole silicon chip resistor 2 is at the same potential, and the problem of partial discharge failure of the silicon chip resistor 2 can be prevented.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (10)
1. A method for preventing a silicon chip resistor from generating partial discharge failure as a gate resistor is characterized by comprising the following steps: in the silicon chip resistor (2), the potential control is carried out on one suspended end in the equivalent circuit of the silicon chip resistor (2) so that the suspended end and the whole body of the silicon chip resistor (2) are in the same potential.
2. The method of preventing partial discharge failure of a silicon wafer resistor as a gate resistor of claim 1, wherein: when the potential control is performed, the potentials of the upper surface and the lower surface of the silicon chip resistor (2) are controlled to be at the same level.
3. The method of preventing partial discharge failure of a silicon wafer resistor as a gate resistor according to claim 2, wherein: when the potential control is performed, the metal-coated layer of the silicon chip resistor (2) is directly connected with the upper surface of the silicon chip resistor (2), or the metal-coated layer connected with the upper surface of the silicon chip resistor (2) is connected with the metal-coated layer of the silicon chip resistor (2), so that the potentials of the upper surface and the lower surface of the silicon chip resistor (2) are at the same level.
4. A method of preventing partial discharge failure of a silicon die resistor as a gate resistor as set forth in claim 3 wherein: the metal-clad layer of the silicon chip resistor (2) is directly connected with the upper surface of the silicon chip resistor (2) through a binding line, or the metal-clad layer connected with the upper surface of the silicon chip resistor (2) is connected with the metal-clad layer of the silicon chip resistor (2) through a binding line.
5. The method of preventing partial discharge failure of a silicon wafer resistor as a gate resistor according to claim 2, wherein: the metal-coated layer connected with the upper surface of the silicon chip resistor (2) and the metal-coated layer where the silicon chip resistor (2) is arranged are designed into a whole, so that the potentials of the upper surface and the lower surface of the silicon chip resistor (2) are at the same level.
6. The method of preventing partial discharge failure of a silicon wafer resistor as a gate resistor according to claim 2, wherein: and a process through hole is arranged on the silicon chip resistor (2) to enable the upper surface and the lower surface of the silicon chip resistor (2) to be connected, so that the potentials of the upper surface and the lower surface of the silicon chip resistor (2) are at the same level.
7. The structure for preventing the silicon chip resistor from generating partial discharge failure as the gate electrode resistor is characterized by comprising a binding line, wherein the binding line is used for directly connecting a metal-coated layer of the silicon chip resistor (2) with the upper surface of the silicon chip resistor (2) or connecting a metal-coated layer connected with the upper surface of the silicon chip resistor (2) with the metal-coated layer of the silicon chip resistor (2) so as to enable the electric potentials of the upper surface and the lower surface of the silicon chip resistor (2) to be at the same level.
8. The utility model provides a power semiconductor device, includes power semiconductor chip (1), silicon chip resistance (2), first binding line (41), second binding line (42), third binding line (43), first metal coating layer (31), second metal coating layer (32), third metal coating layer (33) and fourth metal coating layer (34), power semiconductor chip (1) locates on first metal coating layer (31), silicon chip resistance (2) locates on third metal coating layer (33), first metal coating layer (31) are through first binding line (41) with second metal coating layer (32) link to each other, first upper surface end (21) on silicon chip resistance (2) are through second binding line (42) with second metal coating layer (32) link to each other, second upper surface end (22) on silicon chip resistance (2) are through third binding line (43) with fourth metal coating layer (34) link to each other, its characterized in that still includes fourth binding line (41) and link to each other with second metal coating layer (32).
9. The utility model provides a power semiconductor device, includes power semiconductor chip (1), silicon chip resistance (2), first binding line (41), second binding line (42), third binding line (43), first metal coating layer (31), second metal coating layer (32), third metal coating layer (33) and fourth metal coating layer (34), power semiconductor chip (1) locates on first metal coating layer (31), silicon chip resistance (2) locates on third metal coating layer (33), first metal coating layer (31) are through first binding line (41) with second metal coating layer (32) link to each other, first upper surface end (21) on silicon chip resistance (2) are through second binding line (42) with second metal coating layer (32) link to each other, second upper surface end (22) on silicon chip resistance (2) are through third binding line (43) with fourth metal coating layer (34) link to each other, its characterized in that second metal coating layer (32) or fourth metal coating layer (33) are integrative.
10. The power semiconductor device comprises a power semiconductor chip (1) and a silicon chip resistor (2), wherein the silicon chip resistor (2) is used as a gate resistor of the power semiconductor chip, and the power semiconductor device is characterized in that a process through hole electrically connected with the upper surface and the lower surface of the silicon chip resistor (2) is formed in the silicon chip resistor (2), so that the upper surface and the lower surface of the silicon chip resistor (2) are electrically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911368420.4A CN113053856B (en) | 2019-12-26 | 2019-12-26 | Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911368420.4A CN113053856B (en) | 2019-12-26 | 2019-12-26 | Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113053856A CN113053856A (en) | 2021-06-29 |
| CN113053856B true CN113053856B (en) | 2024-07-02 |
Family
ID=76505405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911368420.4A Active CN113053856B (en) | 2019-12-26 | 2019-12-26 | Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113053856B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501757A (en) * | 2002-11-15 | 2004-06-02 | 华邦电子股份有限公司 | Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor |
| CN103367303A (en) * | 2013-07-04 | 2013-10-23 | 株洲南车时代电气股份有限公司 | High-power IGBT (Insulated Gate Bipolar Transistor) module with integrated gate pole resistor layout |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19630902B4 (en) * | 1996-08-01 | 2005-07-14 | Ixys Semiconductor Gmbh | Device for temperature monitoring in a power electronic device |
| JP4449772B2 (en) * | 2004-04-09 | 2010-04-14 | 株式会社デンソー | Power semiconductor switching element and semiconductor power module using the same |
| JP6893169B2 (en) * | 2017-12-26 | 2021-06-23 | 株式会社日立製作所 | Power module and power converter |
| CN212750884U (en) * | 2020-07-28 | 2021-03-19 | 致瞻科技(上海)有限公司 | Power semiconductor module of integrated gate absorption circuit |
-
2019
- 2019-12-26 CN CN201911368420.4A patent/CN113053856B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501757A (en) * | 2002-11-15 | 2004-06-02 | 华邦电子股份有限公司 | Electrostatic protection circuit using grid coupling metal-oxide half field effect transistor |
| CN103367303A (en) * | 2013-07-04 | 2013-10-23 | 株洲南车时代电气股份有限公司 | High-power IGBT (Insulated Gate Bipolar Transistor) module with integrated gate pole resistor layout |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113053856A (en) | 2021-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5413349B2 (en) | Semiconductor test equipment and semiconductor test circuit connection equipment | |
| US8487407B2 (en) | Low impedance gate control method and apparatus | |
| CN108347177A (en) | Semiconductor device | |
| CN101047148B (en) | Manufacturing method of semiconductor device corresponding to loop back test | |
| US20160336741A1 (en) | Usb controller esd protection apparatus and method | |
| CN106233461A (en) | Semiconductor device and manufacture method thereof | |
| CN102201401B (en) | Semiconductor device | |
| CN100428462C (en) | Semiconductor integrated circuit device | |
| CN100550369C (en) | Has array capacitor in order to the space of realizing full-grid socket | |
| CN112970198A (en) | High speed switching circuit arrangement | |
| CN109997223A (en) | Power semiconductor modular | |
| TW200402140A (en) | Semiconductor integrated circuit device | |
| US6670692B1 (en) | Semiconductor chip with partially embedded decoupling capacitors | |
| CN205542761U (en) | Power module | |
| CN105977938A (en) | ESD protection circuit for chip | |
| CN113053856B (en) | Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device | |
| EP1474695B1 (en) | Method and apparatus for testing electronic devices | |
| US20100171211A1 (en) | Semiconductor device | |
| CN114088986A (en) | Dynamic test board for needle-shaped terminal half-bridge type power module | |
| CN104882388A (en) | Voltage-withstanding detection system and method for subunit based on DBC substrate | |
| US7023086B2 (en) | Semiconductor component arrangement with a reduced oscillation tendency | |
| CN101325164A (en) | Method for manufacturing semiconductor device equipped with passive element | |
| CN112886558A (en) | Power semiconductor chip parallel structure and drive circuit overcurrent failure suppression method thereof | |
| CN103327737B (en) | Chip package assembly and chip assemble method | |
| EP1414066B1 (en) | Method for monitoring semiconductor power elements |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |