CN1494162A - Semiconductor substrate and its mfg. method, and semiconductor device and its mfg. method - Google Patents
Semiconductor substrate and its mfg. method, and semiconductor device and its mfg. method Download PDFInfo
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- CN1494162A CN1494162A CNA031603025A CN03160302A CN1494162A CN 1494162 A CN1494162 A CN 1494162A CN A031603025 A CNA031603025 A CN A031603025A CN 03160302 A CN03160302 A CN 03160302A CN 1494162 A CN1494162 A CN 1494162A
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- 239000000758 substrate Substances 0.000 title claims abstract description 195
- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 title claims description 90
- 239000012535 impurity Substances 0.000 claims abstract description 257
- 238000009792 diffusion process Methods 0.000 claims abstract description 143
- 238000004519 manufacturing process Methods 0.000 claims abstract description 62
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- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052734 helium Inorganic materials 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 238000003892 spreading Methods 0.000 claims description 6
- 230000007480 spreading Effects 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 76
- 229910052710 silicon Inorganic materials 0.000 abstract description 76
- 239000010703 silicon Substances 0.000 abstract description 76
- 230000002457 bidirectional effect Effects 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract 4
- 230000015556 catabolic process Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 23
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
An N<->-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N<->-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N<->-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N<->-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N<-> region (1a) which is part of the N<->-type silicon substrate (1). The N<-> region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N<->-type silicon substrate (1). Thus obtained are a semiconductor device and a method of manufacturing the same, and a semiconductor substrate and a method of manufacturing the same, which make it possible to retain bidirectional breakdown voltages and ensure high reliability.
Description
Technical field
The present invention relates to be used for the Semiconductor substrate of power semiconductor and the semiconductor device and the manufacture method thereof of manufacture method and this Semiconductor substrate of employing thereof.
Background technology
Proposed in recent years three-phase voltage source directly carry out by bidirectional switch switch mode, what is called is called as the power circuit of AC matrix converter.And,, require to have two-way withstand voltage power device as the bidirectional switch that is used to the AC matrix converter.As one, having delivered can be at the withstand voltage IGBT of two-way maintenance (with reference to non-patent literature 1).
And, the technology that forms the Localized Lifetime district by irradiation helium or proton under remember that patent documentation 1 is disclosed.
[non-patent literature 1]
M.Takei，Y.Harada，and?K.Ueno，600V-IGBT?with?ReverseBlocking?Capability、Proceedings?of?2001?InternationalSymposium?on?Power?Semiconductor?Devices?&?ICs，Osaka。
[patent documentation 1]
The spy opens the 2002-76017 communique
But, in the IGBT of above-mentioned document 1 record, dig collector electrode P layer from substrate surface by the groove that will be called mesa structure always, the material that is formed for slowing down electric field in the inside of groove keeps withstand voltage.Though also adopted the method in existing bidirectional triode thyristor etc., there is the low problem of reliability in it.
And, though put on an equal footing,, result from the Shi Tihua of proton and the problem that exists counter withstand voltage to descend along with the change in depth of in substrate, injecting proton at above-mentioned document 2 helium and proton.
Summary of the invention
The present invention is exactly in order to address these problems, purpose be obtain can be in two-way maintenance withstand voltage and semiconductor device with high reliability and manufacture method thereof, and the Semiconductor substrate and the manufacture method thereof that obtain to be used for this semiconductor device.
The described Semiconductor substrate of the 1st invention comprises: the substrate with the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface; The impurity diffusion layer of the 2nd that form in the 1st first type surface based on diffusion of impurities, different conductivity type with the 1st conductivity type; Locally in the 2nd first type surface form, have the bottom surface of arriving at impurity diffusion layer, surround the impurity diffusion zone of the 2nd conductivity type of a part of the 1st conductivity type of substrate from the plane based on diffusion of impurities, the part of being surrounded by impurity diffusion zone is defined as component forming region.
The described semiconductor device of the 2nd invention comprises: Semiconductor substrate, it comprises the substrate that (a) has the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface, the impurity diffusion layer of the 2nd that (b) in the 1st first type surface, form, different conductivity type with the 1st conductivity type based on diffusion of impurities, and (c) locally in the 2nd first type surface form, have the bottom surface of arriving at impurity diffusion layer, surround the impurity diffusion zone of the 2nd conductivity type of a part of the 1st conductivity type of substrate from the plane based on diffusion of impurities, the part of being surrounded by impurity diffusion zone is defined as component forming region; In component forming region, the 1st impurity range of local the 2nd conductivity type that forms in the 2nd first type surface.
The described semiconductor device of the 3rd invention comprises: Semiconductor substrate, it comprises the substrate that (a) has the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface, (b) in the 1st first type surface, form, play a role as transistor collector, the impurity diffusion layer of 2nd conductivity type different with the 1st conductivity type, and (c) local formation in the 2nd first type surface, has the bottom surface of arriving at impurity diffusion layer, surround the impurity diffusion zone of the 2nd conductivity type of a part of the 1st conductivity type of substrate from the plane, the part of being surrounded by impurity diffusion zone is defined as component forming region; In component forming region, the 1st impurity range of the 2nd conductivity type that locally in the 2nd first type surface forms, plays a role as transistor base; In the 1st impurity range, the 2nd impurity range of the 1st conductivity type that locally in the 2nd first type surface forms, plays a role as emitter; Above the 1st impurity range between the part at the 1st conductivity type of the 2nd impurity range and substrate, clip the gate electrode that gate insulating film forms on the 2nd first type surface; Inject the 1st Localized Lifetime district that proton forms by substantial middle district at the film thickness direction of the part of the 1st conductivity type of substrate.
The manufacture method of the described Semiconductor substrate of the 4th invention comprises: the operation of substrate of (a) preparing to have the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface; (b) by in substrate, spreading the 1st impurity, form the operation of the impurity diffusion layer of 2nd conductivity type different with the 1st conductivity type from the 1st first type surface; (c) in substrate, spread the 2nd impurity by a part from the 2nd first type surface, form the operation of impurity diffusion zone of the 2nd conductivity type of a part that has the bottom surface of arriving at impurity diffusion layer, surrounds the 1st conductivity type of substrate from the plane, the part of being surrounded by impurity diffusion zone is defined as component forming region.
The manufacture method of the described semiconductor device of the 5th invention comprises: the operation of substrate of (a) preparing to have the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface; (b) by in substrate, spreading the 1st impurity, form the operation of the impurity diffusion layer of 2nd conductivity type different with the 1st conductivity type from the 1st first type surface; (c) in substrate, spread the 2nd impurity by a part from the 2nd first type surface, form the operation of impurity diffusion zone of the 2nd conductivity type of a part that has the bottom surface of arriving at impurity diffusion layer, surrounds the 1st conductivity type of substrate from the plane, the part of being surrounded by impurity diffusion zone is defined as component forming region, also comprise: (d) in component forming region, the local operation that forms the 1st impurity range of the 2nd conductivity type in the 2nd first type surface; (e) in the 1st impurity range, the local operation that forms the 2nd impurity range of the 1st conductivity type in the 2nd first type surface; (f) above the 1st impurity range between the part at the 1st conductivity type of the 2nd impurity range and substrate, clip gate insulating film and on the 2nd first type surface, form the operation of gate electrode, the 1st impurity range plays a role as transistorized base stage, the 2nd impurity range plays a role as transistorized emitter, and impurity diffusion zone plays a role as transistorized collector electrode.
The manufacture method of the described semiconductor device of the 6th invention comprises: the operation of substrate of (a) preparing to have the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface; (b) in the 1st first type surface, form, as transistor collector play a role, the operation of the impurity diffusion layer of 2nd conductivity type different with the 1st conductivity type; (c) operation of impurity diffusion zone of the 2nd conductivity type of a part that locally in the 2nd first type surface forms, has the bottom surface of arriving at impurity diffusion layer, surrounds the 1st conductivity type of substrate from the plane, the part of being surrounded by impurity diffusion zone is defined as component forming region, also comprise: (d) in component forming region, in the 2nd first type surface local form as transistorized base stage play a role, the operation of the 1st impurity range of the 2nd conductivity type; (e) in the 1st impurity range, in the 2nd first type surface local form as transistorized emitter play a role, the operation of the 2nd impurity range of the 1st conductivity type; (f) above the 1st impurity range between the part at the 1st conductivity type of the 2nd impurity range and substrate, clip gate insulating film forms gate electrode on the 2nd first type surface operation; (g) from the 1st main surface side by impurity diffusion layer, inject proton in the substantial middle district of the film thickness direction of the part of the 1st conductivity type of substrate, form the operation in the 1st Localized Lifetime district thus.
Description of drawings
Fig. 1 is the vertical view that the Semiconductor substrate structure of embodiment of the present invention 1 is shown.
Fig. 2 is the profile that illustrates along the relevant cross-section structure in the position of X1-X1 line shown in Figure 1.
Fig. 3 is the profile that the Semiconductor substrate manufacture method of embodiment of the present invention 1 is shown by process sequence.
Fig. 4 is the profile that the Semiconductor substrate manufacture method of embodiment of the present invention 1 is shown by process sequence.
Fig. 5 is the profile that the Semiconductor substrate manufacture method of embodiment of the present invention 1 is shown by process sequence.
Fig. 6 is the profile that the Semiconductor substrate manufacture method of embodiment of the present invention 1 is shown by process sequence.
Fig. 7 is the figure that is used to illustrate the effect of the Semiconductor substrate of embodiment of the present invention 1 and manufacture method thereof.
Fig. 8 is the figure that is used to illustrate the effect of the Semiconductor substrate of embodiment of the present invention 1 and manufacture method thereof.
Fig. 9 is the profile that the Semiconductor substrate manufacture method of embodiment of the present invention 2 is shown by process sequence.
Figure 10 is the profile that the Semiconductor substrate manufacture method of embodiment of the present invention 2 is shown by process sequence.
Figure 11 is the profile that the Semiconductor substrate manufacture method of embodiment of the present invention 2 is shown by process sequence.
Figure 12 is that the Semiconductor substrate that illustrates to make of the manufacture method of the Semiconductor substrate of embodiment of the present invention 2 is the figure of the SR evaluation result of object.
Figure 13 is the profile that the change example of execution mode 1,2 is shown.
Figure 14 is the profile that the semiconductor device structure of embodiment of the present invention 3 is shown.
Figure 15 is the profile that the method, semi-conductor device manufacturing method of embodiment of the present invention 3 is shown by process sequence.
Figure 16 is the profile that the method, semi-conductor device manufacturing method of embodiment of the present invention 3 is shown by process sequence.
Figure 17 is the profile that the method, semi-conductor device manufacturing method of embodiment of the present invention 3 is shown by process sequence.
Figure 18 is the profile that the method, semi-conductor device manufacturing method of embodiment of the present invention 3 is shown by process sequence.
Figure 19 is the profile that the method, semi-conductor device manufacturing method of embodiment of the present invention 3 is shown by process sequence.
Figure 20 is the profile that the method, semi-conductor device manufacturing method of embodiment of the present invention 3 is shown by process sequence.
Figure 21 is the profile that the method, semi-conductor device manufacturing method of embodiment of the present invention 3 is shown by process sequence.
Figure 22 illustrates about N
-The figure of the analog result of the thickness in district and withstand voltage relation.
Figure 23 is the figure of the leakage current measurement result when withstand voltage mensuration is shown.
Figure 24 is the profile that the semiconductor device structure of embodiment of the present invention 4 is shown.
Figure 25 is the profile that the semiconductor device structure of embodiment of the present invention 5 is shown.
Figure 26 is the profile of one procedure that the method, semi-conductor device manufacturing method of embodiment of the present invention 5 is shown.
Figure 27 is that the monitor board that illustrates with regulation is the figure of the SR evaluation result of object.
Figure 28 be illustrate proton the injection degree of depth and withstand voltage between the curve chart of investigation result of relation.
Figure 29 is based on semiconductor device shown in Figure 24, the profile of the semiconductor device structure of embodiment of the present invention 6 is shown.
Figure 30 is based on semiconductor device shown in Figure 25, the profile of the semiconductor device structure of embodiment of the present invention 6 is shown.
Figure 31 illustrates the profile that embodiment of the present invention 6 becomes the semiconductor device structure of example 1.
Figure 32 illustrates the profile that embodiment of the present invention 6 becomes the semiconductor device structure of example 2.
Symbol description
1 N
-The type silicon substrate; 2 P type isolated areas; 3 p type impurity diffusion layers; 5,15 silicon oxide films; 20 p type impurity districts; 21 N type impurity ranges; 23 gate electrodes; 24 emitter electrodes; 27 collector electrodes; 30,30p, 30h Localized Lifetime district; 49,50 materials.
Embodiment
Fig. 1 is the vertical view that the Semiconductor substrate structure of embodiment of the present invention 1 is shown, and Fig. 2 is the profile that illustrates along the relevant cross-section structure in the position of X1-X1 line shown in Figure 1.With reference to Fig. 2, N
- Type silicon substrate 1 has opposed bottom surface and upper surface.By the diffusion of p type impurity, at N
-Form the p type impurity diffusion layer 3 of high concentration in the bottom surface of type silicon substrate 1 comprehensively.And, by the diffusion of p type impurity, at N
-The local P type isolated area 2 that forms in the upper surface of type silicon substrate 1.P type isolated area 2 has the bottom surface of the upper surface that arrives at p type impurity diffusion layer 3.In addition, with reference to Fig. 1, when from N
-During the upper surface unilateral observation of type silicon substrate 1, P type isolated area 2 is to surround as N
-The N of the part of type silicon substrate 1
-The mode of district 1a forms.Then, the above-mentioned N that is surrounded by P type isolated area 2
- District 1a is defined as N
-The component forming region of type silicon substrate 1.
Fig. 3～6th illustrates the profile of the Semiconductor substrate manufacture method of present embodiment 1 by process sequence.With reference to Fig. 3, at first, prepare N
-Type silicon substrate 1.Secondly, use thermal oxidation method at N
-Form silicon oxide film 4 on the upper surface of type silicon substrate 1 comprehensively.
With reference to Fig. 4, then, at N
-Apply the material (for example dielectric film) 49 that contains p type impurities such as boron on the bottom surface of type silicon substrate 1 comprehensively.By heat-treat, the p type impurity that in material 49 comprise be directed into N thereafter,
-In the type silicon substrate 1 and make it thermal diffusion.In view of the above, at N
-Form p type impurity diffusion layer 3 in the bottom surface of type silicon substrate 1.Remove silicon oxide film 4 and material 49 thereafter.In addition, heat treatment temperature and time during by adjustment thermal diffusion p type impurity, can set from N arbitrarily
-The degree of depth of the p type impurity diffusion layer 3 that the bottom surface of type silicon substrate 1 is counted.
With reference to Fig. 5, then, use thermal oxidation method at N
-Form silicon oxide film 5 all sidedly on the upper surface of type silicon substrate 1 He on the bottom surface.Then, partly remove with phototype and etching method at N
-The silicon oxide film 5 that forms on the upper surface of type silicon substrate 1.In view of the above, form aperture portion 5a, expose N
-The part of the upper surface of type silicon substrate 1.
With reference to Fig. 6, then, in the mode of capping oxidation silicon fiml 5 at N
-Apply the material (for example dielectric film) 50 that contains p type impurities such as boron on the upper surface of type silicon substrate 1.At the part that forms aperture portion 5a, material 50 and N
-The upper surface contact of type silicon substrate 1.Thereafter, by heat-treating, at material 50 and N
-The part that type silicon substrate 1 is in contact with one another is directed into N with the p type impurity that comprises in the material 50
-In the type silicon substrate 1 and make it thermal diffusion.In view of the above, at N
-Form P type isolated area 2 in the upper surface of type silicon substrate 1.By remove silicon oxide film 5 and material 50, can obtain shown in Figure 2 Semiconductor substrate thereafter.
Like this, utilize the Semiconductor substrate and the manufacture method thereof of present embodiment 1, at N
-After forming the p type impurity diffusion layer 3 of high concentration in the bottom surface of type silicon substrate 1, at N
-Form P type isolated area 2 in the upper surface of type silicon substrate 1.Thereby, because p type impurity diffusion layer 3 plays a role as the absorption site at damage when forming P type isolated area 2, so can access the Semiconductor substrate that reduces or eliminates the defective that the formation because of P type isolated area 2 causes.
Below this effect is specifically verified.Fig. 7, the 8th is used to illustrate the figure of the effect of the Semiconductor substrate of present embodiment 1 and manufacture method thereof.Fig. 7 does not form p type impurity diffusion layer 3 and example when forming P type isolated area 2, and Fig. 8 is the example when forming p type impurity diffusion layer 3 backs and form P type isolated areas 2.
In thickness is the upper surface of FZ wafer of 800 μ m, form the P type isolated area 2 that the degree of depth is about 250 μ m.Then, in the heat treatment of carrying out more than 1100 ℃ about 60 minutes.Then, after the wafer cleavage,, defective is manifested by carrying out etching with the Sirtl etching liquid.The results are shown in Fig. 7 with microscope to what the sample that obtains was like this observed.As shown in Figure 7, in wafer, produced and numerous can think OSF (Oxide Stacking Fault: the defective 10 oxide stacking fault).Also have, when with this wafer fabrication IGBT, the leakage current during withstand voltage mensuration is very big, and particularly leakage current is bigger under high temperature (125 ℃) state, the IGBT cisco unity malfunction.
On the other hand, in the bottom surface of FZ wafer, behind the formation p type impurity diffusion layer 3, form the P type isolated area 2 of the about 180 μ m of the degree of depth, carry out the resulting Fig. 8 that the results are shown in of observation same as described above.As shown in Figure 8, in wafer, do not produce defective 10.Also have, when with this wafer fabrication IGBT, compare with the situation that does not form p type impurity diffusion layer 3, the leakage current during withstand voltage mensuration reduces significantly.
Fig. 9～11st illustrates the profile of the Semiconductor substrate manufacture method of embodiment of the present invention 2 by process sequence.With reference to Fig. 9, at first, prepare N
-Type silicon substrate 1.Secondly, use thermal oxidation method at N
-Form silicon oxide film 15 all sidedly on the upper surface of type silicon substrate 1 He on the bottom surface.
With reference to Figure 10, then, partly remove at N with phototype and etching method
-The silicon oxide film 15 that forms on the upper surface of type silicon substrate 1.In view of the above, form aperture portion 15a, expose N
-The part of the upper surface of type silicon substrate 1.In addition, will be with etching method at N
-The silicon oxide film 15 that forms on the bottom surface of type silicon substrate 1 is removed comprehensively.In view of the above, expose N
-The bottom surface of type silicon substrate 1.
With reference to Figure 11, then, in the mode of capping oxidation silicon fiml 15 at N
-On the upper surface of type silicon substrate 1, and at N
-Apply the material 50 that contains p type impurities such as boron on the bottom surface of type silicon substrate 1 respectively.Thereafter, by heat-treating, at material 50 and N
-The part that type silicon substrate 1 is in contact with one another is directed into N with the p type impurity that comprises in the material 50
-In the type silicon substrate 1 and make it thermal diffusion.In view of the above, at N
-Form P type isolated area 2 in the upper surface of type silicon substrate 1, simultaneously at N
-Form p type impurity diffusion layer 3 in the bottom surface of type silicon substrate 1.By remove silicon oxide film 15 and material 50, can obtain shown in Figure 2 Semiconductor substrate thereafter.
Figure 12 is that the Semiconductor substrate that illustrates to make of the manufacture method of the Semiconductor substrate of present embodiment 2 is SR (the Spreading Resistance: the figure of evaluation result spreading resistance) of object.Transverse axis is from N
-The depth D that the upper surface of type silicon substrate 1 is counted (μ m), the longitudinal axis are concentration N (cm
-3), electricalresistivity (Ω cm) and resistance R (Ω).In Figure 12, extract thickness out and be in the Semiconductor substrate of 350 μ m from N
-The upper surface of type silicon substrate 1 to the degree of depth is the zone of 240 μ m, and the result that SR estimates is shown.
With reference to Figure 12 as can be known, be the center with near the degree of depth (175 μ m) the central authorities of the thickness of Semiconductor substrate, roughly symmetrical about each characteristic of concentration N, electricalresistivity and resistance R.That is, as can be known in the Semiconductor substrate of present embodiment 2, the thickness of p type impurity diffusion layer 3 with from N
-The degree of depth of the P type isolated area 2 that the upper surface of type silicon substrate 1 is counted (is all 175 μ m) about equally.In addition, as noting the characteristic of concentration N, then from N
-The bottom surface of type silicon substrate 1 is to the impurities concentration distribution of the p type impurity diffusion layer 3 of substrate interior direction and from N
-The upper surface of type silicon substrate 1 is roughly the same to the P of substrate interior direction type isolated area 2 impurities concentration distribution.
Like this, according to the Semiconductor substrate and the manufacture method thereof of present embodiment 2, as shown in Figure 1, being used to form the thermal diffusion of p type impurity of P type isolated area 2 and the thermal diffusion that is used to form the p type impurity of p type impurity diffusion layer 3 can be undertaken by same operation.Consequently, compare, can reduce the worker ordinal number with above-mentioned execution mode 1.
Figure 13 is the profile that the change example of above-mentioned execution mode 1,2 is shown.After the manufacture method with above-mentioned execution mode 1,2 obtains Semiconductor substrate shown in Figure 2, by from the bottom surface one side with N
- Type silicon substrate 1 grinds away desirable thickness, with p type impurity diffusion layer 3 attenuates.In view of the above, can adjust the surface (N of p type impurity diffusion layer 3
-The bottom surface of type silicon substrate 1) impurity concentration in.
In addition, open among Fig. 4 of flat 7-307469 communique, disclose and carried out (a) in order by from N the spy
-The upper surface of type substrate and bottom surface local diffusion p type impurity form the local N of perforation
-The operation of the upper surface of type substrate and the p type impurity diffusion region between the bottom surface; (b) pass through to N
-Overall diffusion p type impurity in the bottom surface of type substrate, the manufacture method of the semiconductor device of the operation of the p type impurity diffusion layer that formation is connected with above-mentioned p type impurity diffusion region.But, in this way, in above-mentioned operation (a), must be mask alignment N
-The same position of the upper surface of type substrate and bottom surface forms, thereby has manufacturing process's complicated problems.And on the other hand, use the manufacture method of the Semiconductor substrate of embodiment of the present invention 1,2, then there is not this problem.
Also have, in Fig. 5 of above-mentioned communique, disclose and carried out (a) in order at P
+Form N on the upper surface of type substrate
-The operation of type epitaxial loayer; (b) pass through to N
-Local diffusion p type impurity in the upper surface of type epitaxial loayer forms and above-mentioned P
+The P that the type substrate connects
+The manufacture method of the semiconductor device of the operation of type impurity diffusion layer.But, in this way, because need be at P
+Form N on the type substrate
-The operation of type epitaxial loayer, thus exist manufacturing cost to increase, the problem that the worker ordinal number increases.And on the other hand, use the manufacture method of the Semiconductor substrate of embodiments of the present invention 1,2, this problem does not then take place.
Figure 14 is the profile of structure of semiconductor device (IGBT) that the embodiment of the present invention 3 of the Semiconductor substrate of using above-mentioned execution mode 1,2 is shown.In component forming region, at N
-The local p type impurity district 20 that forms in the upper surface of type silicon substrate 1.In p type impurity district 20, at N
-In the upper surface of type silicon substrate 1, the local N that forms
+Type impurity range 21.P type impurity district 20 plays a role as the base stage of IGBT, N
+Type impurity range 21 plays a role as the emitter of IGBT, and p type impurity diffusion layer 3 plays a role as the collector electrode of IGBT.In addition, at N
-In the upper surface of type silicon substrate 1, be positioned at N
+Type impurity range 21 and N
-The p type impurity district 20 of the part of district between the 1a plays a role as channel region.A part that clips dielectric film 22 on channel region forms gate electrode 23.The material of gate electrode 23 for example is a polysilicon.At N
-Form the collector electrode 27 that contacts with p type impurity diffusion layer 3 on the bottom surface of type silicon substrate 1.At N
-On the upper surface of type silicon substrate 1, form and p type impurity district 20 and N
+The emitter electrode 24 of type impurity range 21 contacts.Electrode 25 is connected with P type isolated area 2.In addition, the IGBT of present embodiment 3 comprises the guard ring structure 26 with p type impurity district 26a, electrode 26b and dielectric film 26c.
Figure 15～21st illustrates the profile of the method, semi-conductor device manufacturing method of present embodiment 3 by process sequence.With reference to Figure 15, at first, prepare the Semiconductor substrate of above-mentioned execution mode 1,2.
With reference to Figure 16, then, use thermal oxidation method at N
-Form silicon oxide film on the upper surface of type silicon substrate 1 comprehensively.Then, use phototype and etching method, form silicon oxide film 22a, 26c thus this silicon oxide film body plan figure.Then, with ion implantation to the part N that exposes from silicon oxide film 22a, 26c
-Import p type impurity in the upper surface of type silicon substrate 1, form p type impurity district 20a, 26a thus.
With reference to Figure 17, then,, use thermal oxidation method at N by after silicon oxide film 22a body plan figure is formed silicon oxide film 22b
-Form the also thin silicon oxide film 22c of ratio silicon oxide film 22b, 26c on the upper surface of type silicon substrate 1.
With reference to Figure 18, then, on whole, form polysilicon film with the CVD method.Then, by this polysilicon film body plan figure being formed gate electrode 23 with phototype and etching method.
With reference to Figure 19, then, use phototype and ion implantation to N
-The local p type impurity that imports forms the p type impurity district 20b also more shallow than p type impurity district 20a in the upper surface of type silicon substrate 1.Constitute p type impurity district 20 shown in Figure 14 by p type impurity district 20a, 20b.
With reference to Figure 20, then, remove the partial oxidation silicon fiml 22c that exposes from gate electrode 23 with etching method.Be not removed and rest parts silicon oxide film 22c plays a role as gate insulating film.Then, the local N type impurity that imports in the upper surface in p type impurity district 20 forms N with phototype and ion implantation
+ Type impurity range 21.
With reference to Figure 21, then, on whole, form silicon oxide film with the CVD method.Then, with phototype and etching method this silicon oxide film body plan figure is formed side and the upper surface of silicon oxide film with covering grid electrode 23.Constitute dielectric film shown in Figure 14 22 by silicon oxide film 22b～22d.Thereafter, at N
- Form emitter electrode 24 and electrode 25,26b on the upper surface of type silicon substrate 1.In addition, at N
- Form collector electrode 27 on the bottom surface of type silicon substrate 1.In view of the above, can obtain semiconductor device shown in Figure 14.
Below the withstand voltage of semiconductor device of present embodiment 3 discussed.In the following description, the voltage note that puts on the p type impurity district 20 that plays a role as base stage is made " V
20", the voltage note that puts on the p type impurity diffusion layer 3 that plays a role as collector electrode is made " V
3".
When between base stage-collector electrode, applying V
20＜V
3Forward voltage the time, depletion layer is 20 expansions from the p type impurity district, thereby can keep forward withstand voltage.At this moment, though the end in p type impurity district 20 is dogleg shapes, electric field strengthens near it, owing to be formed with guard ring structure 26, near the electric field that can slow down it is concentrated.Consequently can keep rightly by p type impurity district 20, N
-The forward of decisions such as separately impurity concentration of district 1a and p type impurity diffusion layer 3, shape is withstand voltage.
On the other hand, when between base stage-collector electrode, applying V
20＞V
3Reverse voltage the time, depletion layer is from 2 expansions of p type impurity diffusion layer 3 and P type isolated area, thereby can keep oppositely withstand voltage.At this moment, because the end bent shape of P type isolated area 2 relaxes, so withstand voltage maintenance structure such as supplementary protection ring not also can keep by p type impurity district 20, N rightly
-Decisions such as separately impurity concentration of district's 1a, p type impurity diffusion layer 3 and P type isolated area 2, shape oppositely withstand voltage.
Here, make N
-The impurity concentration of district 1a produces various variations, has investigated N by simulating
-The thickness of district 1a and the relation of withstand voltage VCES.Figure 22 is the figure that this analog result is shown.Can know, by adjusting N
-Impurity concentration and the thickness of district 1a can obtain withstand voltage arbitrarily.
In addition, form the situation of P type isolated area 2 to not forming p type impurity diffusion layer 3, and to forming the situation that p type impurity diffusion layer 3 backs form P type isolated area 2, the leakage current when having measured withstand voltage mensuration respectively.Figure 23 is the figure that this measurement result is shown.Characteristic K1 is that characteristic K2 is the measurement result that forms the situation of P type isolated area 2 to not forming p type impurity diffusion layer 3 to the measurement result in the situation that forms p type impurity diffusion layer 3 back formation P type isolated areas 2.As can be known, by forming p type impurity diffusion layer 3 back formation P type isolated areas 2, can reduce leakage current ICES significantly.
Turn-on action to semiconductor device shown in Figure 14 (IGBT) describes below.As the collector voltage VCE that applies regulation between emitter-collector electrode, when applying the grid voltage VGE of regulation simultaneously between emitter-grid, the p type impurity district 20 of the below of gate insulating film 22 is reversed to the N type, forms channel region.So, electronics is injected into N from N type impurity range 21 by channel region
-District 1a.By means of this injected electrons, N
-Become positive bias between district 1a and the p type impurity diffusion layer 3.So, because the hole is injected into N from p type impurity diffusion layer 3
- So district 1a is N
-The resistance value of district 1a descends significantly, by the ability rising of electric current.Like this, in IGBT,, reduced N by the injection of hole from p type impurity diffusion layer 3
-The resistance of district 1a.
Below shutoff work is described.When making grid voltage VGE is 0 or during reverse bias, N type channel region turns back to the P type, from N type impurity range 21 to N
-The electronics of district 1a injects and stops.Accompany therewith, from p type impurity diffusion layer 3 to N
-The hole of district 1a is injected and is also stopped.At N
-The electronics of accumulation and hole in the district 1a since from the p type impurity district electric field of the depletion layers of 20 expansions and discharging to N type impurity range 21 or p type impurity diffusion layer 3, perhaps compound mutually and disappear.
As mentioned above, in the semiconductor device of present embodiment 3, from p type impurity diffusion layer 3 and 2 expansions of P type isolated area, can keep oppositely withstand voltage by depletion layer.Therefore, because can not be as existing IGBT, at p type impurity diffusion layer 3 and N
-Form N between the district 1a
+So the type resilient coating is must be with N
-The thickness thickening of district 1a extremely to a certain degree.N
-The thickness of district 1a can utilize needed withstand voltage and N
-The relation of the impurity concentration of district 1a decides according to curve shown in Figure 22.
Like this, according to the semiconductor device and the manufacture method thereof of present embodiment 3, the forward of IGBT is withstand voltage and reverse withstand voltage can both the maintenance.Therefore, the semiconductor device of present embodiment 3 can be applied to require two-way withstand voltage power device, for example bidirectional switch that uses in the AC matrix converter.
Figure 24 is the profile that the semiconductor device structure of embodiment of the present invention 4 is shown.Based on the semiconductor device of above-mentioned execution mode 3, at N
-Be formed with Localized Lifetime district 30 in the district 1a.Localized Lifetime district 30 can be by means of after obtaining structure for example shown in Figure 21, from N
-Bottom surface one side of type silicon substrate 1 is passed p type impurity diffusion layer 3 to N
-Impurity such as ion injection proton or helium form in the district 1a.Certainly, also can be from N
-Upper surface one side of type silicon substrate 1 is carried out ion and is injected.
As mentioned above, in the semiconductor device of above-mentioned execution mode 3, must be with N
-The thickness thickening of district 1a extremely to a certain degree.Therefore, when conducting, must be from N type impurity range 21 to N
-District 1a injects more electronics.In addition, when turn-offing, at the N of contiguous p type impurity diffusion layer 3
-The part of district 1a, residual have a zone that does not form depletion layer.So owing to do not form the zone of depletion layer at this, the disappearance reason of charge carrier is not based on the discharge of electric field during shutoff, but compound dominating role, thereby it is longer to turn-off the required time.
Therefore, by at N
-Particularly in forming the zone of above-mentioned depletion layer, do not form Localized Lifetime district 30 among the district 1a, impel the charge carrier in this zone compound, the shortening that can seek to turn-off required time.
Figure 25 is the profile that the semiconductor device structure of embodiment of the present invention 5 is shown.In addition, Figure 26 is the profile of one procedure that the method, semi-conductor device manufacturing method of embodiment of the present invention 5 is shown.After obtaining structure shown in Figure 21, with reference to Figure 26, by from the bottom surface one side with N
- Type silicon substrate 1 grinds away desirable thickness, makes 3 attenuation of p type impurity diffusion layer.Then, the same with above-mentioned execution mode 4, by means of from N
-Bottom surface one side of type silicon substrate 1 is passed p type impurity diffusion layer 3 to N
-Ion injects the impurity of regulation in the district 1a, forms Localized Lifetime district 30.Thus, can obtain semiconductor device shown in Figure 25.
Like this, according to the semiconductor device and the manufacture method thereof of present embodiment 5, behind attenuate p type impurity diffusion layer 3, by from N
-The bottom surface one side ion of type silicon substrate 1 injects the impurity of regulation, comes at N
-Form Localized Lifetime district 30 in the district 1a.Therefore, compare with above-mentioned execution mode 4, can be at N
-Form Localized Lifetime district 30 near the upper surface of type silicon substrate 1.That is, when setting the degree of depth that forms Localized Lifetime district 30, it is set the degree of freedom and increases.
Passing through to inject proton at N
-When forming Localized Lifetime district 30 in the district 1a, execute bodyization by the annealing proton after injecting, its result has injected the part N of proton
-The impurity concentration of district 1a increases.
Figure 27 is that the monitor board that illustrates with regulation is the figure of the SR evaluation result of object.Monitor board is at the N with 150 μ m thickness
-After near (being the degree of depth 75 μ m) ion injects proton near the middle section type silicon substrate, film thickness direction, make by annealing.The transverse axis of Figure 27 is from N
-The depth D that the upper surface of type silicon substrate is counted (μ m), the longitudinal axis are concentration N (cm
-3), electricalresistivity (Ω cm) and resistance R (Ω).With reference to Figure 27 as can be known, the result who executes bodyization by the annealing proton is near the N degree of depth 75 μ m
-The concentration N of district 1a uprises.
Then, in the semiconductor device of above-mentioned execution mode 3, establish N
-The thickness of district 1a is 170 μ m, and withstand voltage and oppositely withstand voltage each absolute value is with to N to the forward of semiconductor device
-How the degree of depth of district 1a injection proton changes is investigated.Figure 28 is the curve chart of its investigation result of expression.The transverse axis of curve chart is from N
-The interface of district 1a and p type impurity diffusion layer 3 begins the distance L (μ m) to the protonation place.The longitudinal axis of curve chart is withstand voltage and reverse withstand voltage each absolute value (V) of forward.With reference to Figure 28 as can be known, the long more oppositely withstand voltage absolute value of distance L becomes big more, and on the contrary, the absolute value that the short more forward of distance L is withstand voltage then becomes big more.It is to result from the Shi Tihua of proton that the short oppositely withstand voltage absolute value of distance L diminishes, owing to inject the part N of proton
-The impurity concentration of district 1a uprises.
Can recognize that from Figure 28 the too short then reverse withstand voltage absolute value of distance L diminishes, the withstand voltage absolute value of the oversize then forward of distance L diminishes.Therefore, when forming the Localized Lifetime district, at N by the injection proton
-Ion injection proton is desirable near the central area of the film thickness direction of district 1a.In example shown in Figure 28,, can obtain the semiconductor device that withstand voltage and reverse each the withstand voltage absolute value of forward all surpasses 1200 (V) by distance L being set in about 80～100 μ m.
Figure 29 is based on semiconductor device shown in Figure 24, the profile of the semiconductor device structure of present embodiment 6 is shown.Replace Localized Lifetime district 30 shown in Figure 24, be formed with Localized Lifetime district 30p.From N
-Bottom surface one side of type silicon substrate 1 is passed p type impurity diffusion layer 3, at N
-Ion injects proton near the central area of the film thickness direction of district 1a, forms Localized Lifetime district 30p thus.
Figure 30 is based on semiconductor device shown in Figure 25, the profile of the semiconductor device structure of present embodiment 6 is shown.Replace Localized Lifetime district 30 shown in Figure 25, be formed with Localized Lifetime district 30p.The same with semiconductor device shown in Figure 29, from N
-Bottom surface one side of type silicon substrate 1 is passed p type impurity diffusion layer 3, at N
-Ion injects proton near the central area of the film thickness direction of district 1a, forms Localized Lifetime district 30p thus.
Figure 31 illustrates the profile that present embodiment 6 becomes the semiconductor device structure of example 1.Based on semiconductor device shown in Figure 29, at N
-Appended Localized Lifetime district 30h in the district 1a.From N
-Bottom surface one side of type silicon substrate 1 is passed p type impurity diffusion layer 3, injecting helium than the more close p type impurity diffusion layer 3 one side ions of Localized Lifetime district 30p, forms Localized Lifetime district 30h thus.
Figure 32 illustrates the profile that present embodiment 6 becomes the semiconductor device structure of example 2.Based on semiconductor device shown in Figure 30, at N
-Appended Localized Lifetime district 30h in the district 1a.The same with semiconductor device shown in Figure 31, from N
-Bottom surface one side of type silicon substrate 1 is passed p type impurity diffusion layer 3, injecting helium than the more close p type impurity diffusion layer 3 one side ions of Localized Lifetime district 30p, forms Localized Lifetime district 30h thus.
Different with proton, helium does not cause Shi Tihua.Even so at N
-The near interface of district 1a and p type impurity diffusion layer 3 forms Localized Lifetime district 30h, and oppositely withstand voltage absolute value can not reduce yet.Also form Localized Lifetime district 30h by being not only Localized Lifetime district 30p, can further promote the compound of charge carrier to realize turn-offing the further shortening of required time.
Like this, according to the semiconductor device and the manufacture method thereof of present embodiment 6, by at N
-Ion injects proton near the central area of the film thickness direction of district 1a, forms Localized Lifetime district 30p thus.Therefore, forward is withstand voltage and reverse each withstand voltage absolute value one side can extremely not reduce, and it is withstand voltage and oppositely withstand voltage that high level keeps the forward of IGBT simultaneously.Therefore, the semiconductor device of present embodiment 6 can be applied to require two-way withstand voltage power device, for example bidirectional switch that uses in the AC matrix converter.
In addition, in above-mentioned execution mode 1～6, the IGBT of N raceway groove is narrated, but the present invention is also applicable to the IGBT of P raceway groove.And, the IGBT that forms gate type on silicon substrate is narrated, but the present invention also is embedded in the IGBT (trench gate type IGBT) of the type in the groove that is formed in the silicon substrate applicable to grid.
The invention effect
According to the Semiconductor substrate of the 1st invention, can be by shape in the 1st first type surface of substrate After becoming impurity diffusion layer, in the 2nd first type surface of substrate, form impurity range and make the semiconductor lining The end. At this moment, since impurity diffusion layer when forming impurity diffusion zone as the absorption for damage The position plays a role, thus can reduce or eliminate that formation because of impurity diffusion zone produces half The defective of conductive substrate.
According to the semiconductor devices of the 2nd invention, expand energy from the 1st impurity range by depletion layer Enough keep forward withstand voltage. And, expand from impurity diffusion layer and impurity diffusion zone by depletion layer, Can keep oppositely withstand voltage. That is, forward withstand voltage and reverse withstand voltage both all can keep.
According to the semiconductor devices of the 3rd invention, forward is withstand voltage and reverse withstand voltage all can high-level guarantor Hold.
According to the manufacture method of the 4th Semiconductor substrate of inventing, because impurity diffusion layer is forming Play a role as the absorption site for damage during impurity diffusion zone, so can be reduced Or the Semiconductor substrate of defective takes place in elimination because of the formation of impurity diffusion zone.
According to the manufacture method of Semiconductor substrate of the 5th invention, by depletion layer from the 1st impurity District's expansion can keep forward withstand voltage. And, by depletion layer from impurity diffusion layer and impurity The diffusion region expansion can keep oppositely withstand voltage. That is it is withstand voltage and oppositely withstand voltage, to access forward Both all retainable IGBT.
According to the manufacture method of Semiconductor substrate of the 6th invention, forward is withstand voltage and reverse all withstand voltage Can keep by high level.
Claims (20)
1. Semiconductor substrate,
It comprises:
Substrate with the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface;
The impurity diffusion layer of the 2nd that form in above-mentioned the 1st first type surface based on diffusion of impurities, different conductivity type with above-mentioned the 1st conductivity type;
Locally in above-mentioned the 2nd first type surface form, have the bottom surface of arriving at above-mentioned impurity diffusion layer, surround the impurity diffusion zone of above-mentioned the 2nd conductivity type of a part of above-mentioned the 1st conductivity type of above-mentioned substrate from the plane based on diffusion of impurities,
The part of being surrounded by above-mentioned impurity diffusion zone is defined as component forming region.
2. the described Semiconductor substrate of claim 1, wherein
The thickness of above-mentioned impurity diffusion layer approximates the degree of depth of the above-mentioned impurity diffusion zone of counting from above-mentioned the 2nd first type surface.
3. the described Semiconductor substrate of claim 1, wherein
From above-mentioned the 1st first type surface to the impurities concentration distribution of the above-mentioned impurity diffusion layer of the internal direction of above-mentioned substrate with roughly the same to the impurities concentration distribution of the above-mentioned impurity diffusion zone of the internal direction of above-mentioned substrate from above-mentioned the 2nd first type surface.
4. the described Semiconductor substrate of claim 1, wherein
The thickness of above-mentioned impurity diffusion layer is thinner than the degree of depth of the above-mentioned impurity diffusion zone of counting from above-mentioned the 2nd first type surface.
5. semiconductor device, it comprises:
Comprise the substrate that (a) has the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface, (b) form in above-mentioned the 1st first type surface based on diffusion of impurities, the impurity diffusion layer of 2nd conductivity type different with above-mentioned the 1st conductivity type, and (c) based on diffusion of impurities local formation in above-mentioned the 2nd first type surface, has the bottom surface of arriving at above-mentioned impurity diffusion layer, surround the impurity diffusion zone of above-mentioned the 2nd conductivity type of a part of above-mentioned the 1st conductivity type of above-mentioned substrate from the plane, the part of being surrounded by above-mentioned impurity diffusion zone is defined as the Semiconductor substrate of component forming region;
In said elements forms the district, the 1st impurity range of local above-mentioned the 2nd conductivity type that forms in above-mentioned the 2nd first type surface.
6. the described semiconductor device of claim 5,
It also comprises: the 2nd impurity range of local above-mentioned the 1st conductivity type that forms in above-mentioned the 1st impurity range, in above-mentioned the 2nd first type surface,
Above-mentioned the 1st impurity range plays a role as transistorized base stage,
Above-mentioned the 2nd impurity range plays a role as above-mentioned transistorized emitter,
Above-mentioned impurity diffusion layer plays a role as above-mentioned transistorized collector electrode.
7. the described semiconductor device of claim 6, it also comprises:
Above above-mentioned the 1st impurity range between the part at above-mentioned the 1st conductivity type of above-mentioned the 2nd impurity range and above-mentioned substrate, clip the gate electrode that gate insulating film forms on above-mentioned the 2nd first type surface.
8. the described semiconductor device of claim 6, it also comprises:
The Localized Lifetime district that in the part of above-mentioned the 1st conductivity type of above-mentioned substrate, forms.
9. the described semiconductor device of claim 8, wherein
Above-mentioned Localized Lifetime district has by the substantial middle district at the part film thickness direction of above-mentioned the 1st conductivity type of above-mentioned substrate injects the 1st Localized Lifetime district that proton forms.
10. the described semiconductor device of claim 9, wherein
Above-mentioned Localized Lifetime district also has by injecting the 2nd Localized Lifetime district that proton forms than more close above-mentioned impurity diffusion layer one side in above-mentioned the 1st Localized Lifetime district.
11. the manufacture method of a Semiconductor substrate,
Comprise:
(a) prepare to have the operation of substrate of the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface;
(b) by in above-mentioned substrate, spreading the 1st impurity, form the operation of the impurity diffusion layer of 2nd conductivity type different with above-mentioned the 1st conductivity type from above-mentioned the 1st first type surface;
(c) in above-mentioned substrate, spread the 2nd impurity by a part from above-mentioned the 2nd first type surface, form the operation of impurity diffusion zone of above-mentioned the 2nd conductivity type of a part that has the bottom surface of arriving at above-mentioned impurity diffusion layer, surrounds above-mentioned the 1st conductivity type of above-mentioned substrate from the plane
The part of being surrounded by above-mentioned impurity diffusion zone is defined as component forming region.
12. the manufacture method of the described Semiconductor substrate of claim 11, wherein
Above-mentioned operation (b) comprising:
(b-1) on above-mentioned the 1st first type surface, form the operation of the film contain above-mentioned the 1st impurity;
(b-2) operation that above-mentioned the 1st impurity is spread in above-mentioned substrate from above-mentioned film.
13. the manufacture method of the described Semiconductor substrate of claim 11, wherein
Above-mentioned operation (c) comprising:
(c-1) the local operation that forms the 1st film on above-mentioned the 2nd first type surface;
(c-2) on above-mentioned the 2nd first type surface, form the operation of the 2nd film that contains above-mentioned the 2nd impurity in the mode that covers above-mentioned the 1st film;
(c-3) operation that above-mentioned the 2nd impurity is spread in above-mentioned substrate from above-mentioned the 2nd film.
14. the manufacture method of the described Semiconductor substrate of claim 11, wherein
Above-mentioned operation (b) comprising:
(b-1) on above-mentioned the 1st first type surface, form the operation of the 1st film contain above-mentioned the 1st impurity;
(b-2) operation that above-mentioned the 1st impurity is spread in above-mentioned substrate from above-mentioned the 1st film,
Above-mentioned operation (c) comprising:
(c-1) the local operation that forms the 2nd film on above-mentioned the 2nd first type surface;
(c-2) on above-mentioned the 2nd first type surface, form the operation of the 3rd film that contains above-mentioned the 2nd impurity in the mode that covers above-mentioned the 2nd film;
(c-3) operation that above-mentioned the 2nd impurity is spread in above-mentioned substrate from above-mentioned the 3rd film,
Above-mentioned operation (b-2) and above-mentioned operation (c-3) are undertaken by same operation.
15. the manufacture method of the described Semiconductor substrate of claim 11,
Also comprise all the following operation of carrying out before in above-mentioned operation (b) and above-mentioned operation (c):
(d) carry out oxidation by surface, on above-mentioned the 1st first type surface, form the 1st oxide-film comprehensively, on above-mentioned the 2nd first type surface, form the operation of the 2nd oxide-film simultaneously comprehensively above-mentioned substrate;
(e) remove the operation of above-mentioned the 1st oxide-film comprehensively;
(f) part is removed the operation of above-mentioned the 2nd oxide-film,
Above-mentioned operation (b) comprising:
(b-1) on above-mentioned the 1st first type surface, form the operation of the 1st film contain above-mentioned the 1st impurity;
(b-2) operation that above-mentioned the 1st impurity is spread in above-mentioned substrate from above-mentioned the 1st film,
Above-mentioned operation (c) comprising:
(c-1) on above-mentioned the 2nd first type surface, form the operation of the 2nd film that contains above-mentioned the 2nd impurity in the mode that covers above-mentioned the 2nd oxide-film;
(c-2) operation that above-mentioned the 2nd impurity is spread in above-mentioned substrate from above-mentioned the 2nd film.
16. the manufacture method of a semiconductor device,
Comprise:
(a) prepare to have the operation of substrate of the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface;
(b) by in above-mentioned substrate, spreading the 1st impurity, form the operation of the impurity diffusion layer of 2nd conductivity type different with above-mentioned the 1st conductivity type from above-mentioned the 1st first type surface;
(c) in above-mentioned substrate, spread the 2nd impurity by a part from above-mentioned the 2nd first type surface, form the operation of impurity diffusion zone of above-mentioned the 2nd conductivity type of a part that has the bottom surface of arriving at above-mentioned impurity diffusion layer, surrounds above-mentioned the 1st conductivity type of above-mentioned substrate from the plane
The part of being surrounded by above-mentioned impurity diffusion zone is defined as component forming region,
Also comprise:
(d) in said elements forms the district, in above-mentioned the 2nd first type surface the operation of the 1st impurity range of above-mentioned the 2nd conductivity type of local formation;
(e) in above-mentioned the 1st impurity range, in above-mentioned the 2nd first type surface the local operation that forms the 2nd impurity range of above-mentioned the 1st conductivity type;
(f) above above-mentioned the 1st impurity range between the part at above-mentioned the 1st conductivity type of above-mentioned the 2nd impurity range and above-mentioned substrate, clip gate insulating film forms gate electrode on above-mentioned the 2nd first type surface operation,
Above-mentioned the 1st impurity range plays a role as transistorized base stage,
Above-mentioned the 2nd impurity range plays a role as above-mentioned transistorized emitter,
Above-mentioned impurity diffusion layer plays a role as above-mentioned transistorized collector electrode.
17. the manufacture method of the described semiconductor device of claim 16 also comprises:
(g) operation of the 1st main electrode that formation contacts with above-mentioned impurity diffusion layer on above-mentioned the 1st first type surface;
(h) on above-mentioned the 2nd first type surface, form operation with the above-mentioned the 1st the 2nd main electrode that contacts with the 2nd impurity range.
18. the manufacture method of the described semiconductor device of claim 17 also comprises:
(i) carry out before in above-mentioned operation (g), by above-mentioned substrate being ground away the thickness of regulation, with the operation of above-mentioned impurity diffusion layer attenuate from above-mentioned the 1st first type surface one side.
19. the manufacture method of a semiconductor device,
Comprise:
(a) prepare to have the operation of substrate of the 1st conductivity type of the 1st relative first type surface and the 2nd first type surface;
(b) in above-mentioned the 1st first type surface, form as transistor collector play a role, the operation of the impurity diffusion layer of 2nd conductivity type different with above-mentioned the 1st conductivity type;
(c) the local operation of impurity diffusion zone of above-mentioned the 2nd conductivity type of a part that has the bottom surface of arriving at above-mentioned impurity diffusion layer, surrounds above-mentioned the 1st conductivity type of above-mentioned substrate from the plane that forms in above-mentioned the 2nd first type surface,
The part of being surrounded by above-mentioned impurity diffusion zone is defined as component forming region,
Also comprise:
(d) in said elements forms the district, in above-mentioned the 2nd first type surface local form as above-mentioned transistorized base stage play a role, the operation of the 1st impurity range of above-mentioned the 2nd conductivity type;
(e) in above-mentioned the 1st impurity range, in above-mentioned the 2nd first type surface local form as above-mentioned transistorized emitter play a role, the operation of the 2nd impurity range of above-mentioned the 1st conductivity type;
(f) above above-mentioned the 1st impurity range between the part at above-mentioned the 1st conductivity type of above-mentioned the 2nd impurity range and above-mentioned substrate, clip gate insulating film forms gate electrode on above-mentioned the 2nd first type surface operation;
(g) from above-mentioned the 1st main surface side by above-mentioned impurity diffusion layer, inject proton in the substantial middle district of the film thickness direction of the part of above-mentioned the 1st conductivity type of above-mentioned substrate, form the operation in the 1st Localized Lifetime district thus.
20. the manufacture method of the described semiconductor device of claim 19 also comprises:
(h) in the part of above-mentioned the 1st conductivity type of above-mentioned substrate,, form the operation in the 2nd Localized Lifetime district thus injecting helium than more close above-mentioned impurity diffusion layer one side in above-mentioned the 1st Localized Lifetime district.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP280666/2002 | 2002-09-26 | ||
| JP2002280666 | 2002-09-26 | ||
| JP280666/02 | 2002-09-26 | ||
| JP194129/2003 | 2003-07-09 | ||
| JP2003194129A JP4781616B2 (en) | 2002-09-26 | 2003-07-09 | Semiconductor substrate manufacturing method and semiconductor device manufacturing method |
| JP194129/03 | 2003-07-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1494162A true CN1494162A (en) | 2004-05-05 |
| CN100423285C CN100423285C (en) | 2008-10-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031603025A Expired - Fee Related CN100423285C (en) | 2002-09-26 | 2003-09-26 | Semiconductor substrate and its mfg. method, and semiconductor device and its mfg. method |
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| Country | Link |
|---|---|
| JP (1) | JP4781616B2 (en) |
| KR (1) | KR100553625B1 (en) |
| CN (1) | CN100423285C (en) |
| DE (1) | DE10344827A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517837A (en) * | 2013-09-29 | 2015-04-15 | 无锡华润上华半导体有限公司 | Method for manufacturing insulated gate bipolar transistor |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4872190B2 (en) * | 2004-06-18 | 2012-02-08 | トヨタ自動車株式会社 | Semiconductor device |
| JP2006108346A (en) * | 2004-10-05 | 2006-04-20 | Matsushita Electric Ind Co Ltd | Chip type semiconductor element and its manufacturing method |
| JP4892825B2 (en) * | 2004-11-12 | 2012-03-07 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| JP2006210606A (en) * | 2005-01-27 | 2006-08-10 | Mitsubishi Electric Corp | Semiconductor apparatus and manufacturing method thereof |
| JP4843253B2 (en) * | 2005-05-23 | 2011-12-21 | 株式会社東芝 | Power semiconductor device |
| JP4852943B2 (en) * | 2005-09-09 | 2012-01-11 | 富士電機株式会社 | Method for sorting semiconductor device chips |
| JP4627272B2 (en) * | 2006-03-09 | 2011-02-09 | 三菱電機株式会社 | Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device |
| US7557386B2 (en) | 2006-03-30 | 2009-07-07 | Infineon Technologies Austria Ag | Reverse conducting IGBT with vertical carrier lifetime adjustment |
| JP5614451B2 (en) | 2010-08-12 | 2014-10-29 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| JPWO2012056536A1 (en) | 2010-10-27 | 2014-03-20 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN104303285B (en) * | 2012-08-22 | 2017-03-01 | 富士电机株式会社 | Semiconductor device and the manufacture method of semiconductor device |
| JP6263966B2 (en) * | 2012-12-12 | 2018-01-24 | 富士電機株式会社 | Semiconductor device |
| JP6467882B2 (en) * | 2014-11-13 | 2019-02-13 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5988871A (en) * | 1982-11-12 | 1984-05-22 | バ−・ブラウン・コ−ポレ−ション | High stabilized low voltage integrated circuit surface breakdown diode structure and method of producing same |
| DE3484747D1 (en) * | 1983-12-05 | 1991-08-01 | Gen Electric | SEMICONDUCTOR SUBSTRATE WITH AN ELECTRICALLY INSULATED SEMICONDUCTOR ARRANGEMENT. |
| US5177587A (en) * | 1989-07-21 | 1993-01-05 | Linear Technology Corporation | Push-back junction isolation semiconductor structure and method |
| JPH04286163A (en) * | 1991-03-14 | 1992-10-12 | Shin Etsu Handotai Co Ltd | Manufacture of semiconductor substrate |
| JP2726583B2 (en) * | 1991-11-18 | 1998-03-11 | 三菱マテリアルシリコン株式会社 | Semiconductor substrate |
| US5272119A (en) * | 1992-09-23 | 1993-12-21 | Memc Electronic Materials, Spa | Process for contamination removal and minority carrier lifetime improvement in silicon |
| JPH06216058A (en) * | 1993-01-18 | 1994-08-05 | Sony Corp | Manufacture of semiconductor device |
| JP3352840B2 (en) * | 1994-03-14 | 2002-12-03 | 株式会社東芝 | Reverse parallel connection type bidirectional semiconductor switch |
| JP3413021B2 (en) * | 1996-07-30 | 2003-06-03 | 株式会社東芝 | Semiconductor device |
| CN1235380A (en) * | 1999-04-07 | 1999-11-17 | 赵振华 | Structure and manufacture of small power thysistor |
| JP4788028B2 (en) * | 2000-08-28 | 2011-10-05 | 富士電機株式会社 | Bidirectional IGBT with reverse blocking IGBTs connected in antiparallel |
-
2003
- 2003-07-09 JP JP2003194129A patent/JP4781616B2/en not_active Expired - Fee Related
- 2003-09-26 CN CNB031603025A patent/CN100423285C/en not_active Expired - Fee Related
- 2003-09-26 DE DE2003144827 patent/DE10344827A1/en not_active Withdrawn
- 2003-09-26 KR KR20030066838A patent/KR100553625B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517837A (en) * | 2013-09-29 | 2015-04-15 | 无锡华润上华半导体有限公司 | Method for manufacturing insulated gate bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| DE10344827A1 (en) | 2004-05-13 |
| JP4781616B2 (en) | 2011-09-28 |
| KR100553625B1 (en) | 2006-02-22 |
| KR20040027442A (en) | 2004-04-01 |
| CN100423285C (en) | 2008-10-01 |
| JP2004165619A (en) | 2004-06-10 |
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