CN101060133A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN101060133A CN101060133A CN 200710088556 CN200710088556A CN101060133A CN 101060133 A CN101060133 A CN 101060133A CN 200710088556 CN200710088556 CN 200710088556 CN 200710088556 A CN200710088556 A CN 200710088556A CN 101060133 A CN101060133 A CN 101060133A
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Abstract
To provide a semiconductor device where the effective thickness of a semiconductor substrate is reduced corresponding to the depths of openings and the semiconductor substrate is prevented from warping, and to provide a method for manufacturing the same. In the present invention, openings 11 such as trench holes are formed on a back surface side of a semiconductor substrate 1. Then, a drain electrode 12 is formed being electrically connected with bottoms of these openings 11. In this case, a current path is formed short corresponding to the depths of the openings 11, thereby easily achieving low on-resistance.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to semiconductor device and manufacture method thereof at the longitudinal stream super-high-current of semiconductor substrate.
Background technology
Longitudinal type MOSFET compares with the horizontal type MOSFET that arranges source electrode, drain electrode on same surface, because therefore the output area broadening of electric current, be suitable as big current element most.
Figure 27 is the profile of an example of the longitudinal type MOS transistor of prior art.
On N+ N-type semiconductor N substrate 201, be formed with N one type epitaxial loayer 202, be formed with P type channel layer 203 on the top layer of epitaxial loayer 202.In addition, also be formed with from the top layer of channel layer 203, in groove 204, form the grid 206 that constitutes by polysilicon film via insulating barrier 205 to the groove 204 of the prescribed depth position of epitaxial loayer 202.And then, on the top layer of epitaxial loayer 202 and in the two side of groove 204 one, be formed with N+ type source layer 207 with insulating barrier 205 adjacency.In addition, stride across between the adjacent source layer 207 and be formed with P+ type body layer 208.Then, to cover the mode of source layer 207, go up the source electrode 209 that formation for example is made of aluminium alloy at semiconductor substrate 201 (epitaxial loayer 202).And, on grid 206, be formed with element isolation film 210 with source electrode 207 insulated separation.
On the other hand, in the rear side of semiconductor substrate 201, form drain electrode 212B and constitute semiconductor device by vacuum vapour deposition.
In this structure, when grid 206 is applied the voltage of regulation, along grid 206, form raceway groove in channel layer 203 parts, with respect to source electrode 207, when drain electrode 212B was applied voltage, electric current just flowed to source layer 207, source electrode 209 from drain electrode 212B by semiconductor substrate 201 and epitaxial loayer 202 and the channel layer 203 of flowing through.
In addition, igbt is also referred to as IGBT, and its elementary cell is the structure with bipolar transistor and compoundization of MOSFET, and therefore, this semiconductor device has both the former low connection voltage characteristic and the latter's driven characteristic.
Figure 28 represents the example of IGBT of the NPT type of prior art.
Face side at N-N-type semiconductor N substrate 301 is formed with the MOS structure.That is, on the first type surface of N-type drift region 302, form P type base region 303 selectively.In addition, on the first type surface of base region 103, form N+ type emitter region 304 selectively.And the surface coverage to the base region 303 of the position that major general's emitter region 304 and drift region 302 clip forms grid 306 via grid oxidation film 305.And then grid 306 is insulated film 307 and surrounds, and covers dielectric film 307 and is connected with emitter region 304 and forms emitter 308.
On the other hand, be formed with collector electrode 311, connect collector electrode 311 and form P+ type collector region 310 in the rear side of semiconductor substrate 301.
In the above-described configuration, for example, in the IGBT of the NPT of withstand voltage 600V type, drift region 302 forms about 90 μ m, collector region 310 forms about 1 μ m.
In this structure, collector electrode 310 is being applied under the state of positive voltage, if grid 306 is applied positive voltage, then on base region 303, form raceway groove corresponding to grid 306.Therefore, electronics is supplied with drift region 302 via this raceway groove.And, when this electronics arrives collector regions 310 through drift region 302,, therefore, realize low connection resistance owing to 310 supply with holes to drift region 302 from the collector region.
On the other hand, when stopping to apply voltage, in NPT type IGBT because the hole amount that is injected in the drift region 302 is few, therefore, minority carrier to accumulate effect little, discharge rapidly via collector electrode 310 in the hole that drift region 302 is accumulated.So this semiconductor device is short opening time, is used in speed-sensitive switch element etc.
As the technical literature of association, for example enumerate following patent documentation.
Patent documentation 1:(Japan) spy opens the 2004-140101 communique
Patent documentation 2:(Japan) spy opens the 2005-129652 communique
Patent documentation 3:(Japan) spy opens the 2001-119023 communique
Till now, in these semiconductor devices, improved cell density, reduced connection resistance, but the microminiaturization of cell density reaches the limit of.
Therefore, semiconductor substrate is required its filming.That is to say, in the current path of these semiconductor devices, the resistance components maximum be semiconductor substrate, as the method that reduces this composition, selected the filming of semiconductor substrate.
But, in the filming of semiconductor substrate, also have certain technical problem and be accompanied by difficulty.Below, be that example describes with NPT type IGBT, this problem equally also is applicable to the longitudinal type MOS transistor.
In NPT type IGBT, except the optimization of connecting resistance, also to consider withstand voltagely, design the thickness of drift region 302 thus.For example, the thickness of drift region 302 with respect to the withstand voltage design of 600V into about 90 μ m, with respect to the withstand voltage design of 1200V into about 130 μ m.And, by the rear side of grinding semiconductor substrate 301, the thickness of drift region 302 is adjusted.
Below, with reference to Figure 29 to Figure 32, the manufacturing process of NPT type IGBT of the prior art is described, specifically represent this problem points.
At first, as shown in figure 29, prepare N-N-type semiconductor N substrate 301, the surface of its face side is carried out thermal oxidation and formed oxide-film 305a.Then, on oxide-film 305a, pile up gate members 306a such as polysilicon.
Then, as shown in figure 30, oxide-film 305a and gate members 306a utilize photoetching technique and etching technique to form grid oxidation film 305 and grid 306 relatively.Then, grid 306 as mask, is injected p type impurities such as boron, form P type base region 303.And then the assigned position on base region 303 forms the photoresist figure with peristome selectively, then, injects N type impurity such as phosphorus with high concentration ion, forms N+ type emitter region 304.
Then, as shown in figure 31, after forming dielectric film, utilize photoetching technique and etching technique, be formed on the dielectric film 307 that has peristome corresponding to the part of emitter region 304 in the face side that covers semiconductor substrate 301.And then, cover dielectric film 307 and imbed Al etc., form the emitter 308 that is connected with emitter region 304.
Then, shown in figure 32,, for example form the drift region 302 of about 90 μ m corresponding to the withstand voltage of 600V from rear side grinding semiconductor substrate 301.
Then, as above-mentioned shown in Figure 28, under the state of thickness attenuation, weakened,, and then form P+ type collector region 310 by implementing heat treatment from the p type impurities such as rear side boron ion implantation of semiconductor substrate 301.Then, in the rear side evaporating Al of semiconductor substrate 301 etc., form the collector electrode 311 that is connected with collector region 310.
At this moment, semiconductor substrate 301 when the back side of processing semiconductor substrate, is accompanied by heat treatment owing to being made mechanical strength die down by filming, semiconductor substrate 301 easy warpages.
In the prior art, in order to address the above problem a little, to adhere to supporting substrates in the face side of semiconductor substrate 301 and wait and keep intensity, simultaneously, carry out the grinding of rear side, and, semiconductor back surface is processed adhering under the state of supporting substrates.
But, when adopting said method, need supporting substrates self, and, need the stickup of supporting substrates and stripping technology etc., cause cost to improve.In addition, even after finishing, because the weak strength of semiconductor substrate 1, poor based on the thermal coefficient of expansion of collector electrode and semiconductor substrate, the easy warpage of semiconductor substrate.
Summary of the invention
In view of the above problems, the invention provides a kind of semiconductor device, the longitudinal stream overcurrent at semiconductor substrate is characterized in that having: the MOS structure, and it is formed on the face side of described semiconductor substrate; Peristome, it is formed on the rear side of described semiconductor substrate; Backplate, it is connected with the bottom electrical of described peristome.
In addition, the present invention also provides a kind of manufacture method of semiconductor device, it is characterized in that, has: the operation that forms the MOS structure in the face side of the semiconductor substrate of first conductivity type; Form the operation of photoresist figure in the rear side of described semiconductor substrate; Carry out etching with described photoresist figure as mask and form the operation of peristome; Be connected with the bottom electrical of described peristome and form the operation of backplate.
In the present invention, essence thickness attenuation of semiconductor substrate, the warpage of inhibition semiconductor substrate corresponding to the degree of depth of peristome.
In addition, in IGBT, the collector region is not to be formed on the whole along peristome, and only is formed on the bottom of peristome.Therefore, the hole amount of supplying with the drift region from the collector region can be constrained to the such of design, and it is easy that the adjustment of opening time becomes.And, built-in FWD in IGBT.
Description of drawings
Fig. 1 (a) and (b) are plane graph and profiles of expression semiconductor device of the present invention;
Fig. 2 represents the part of the manufacturing process of semiconductor device of the present invention;
Fig. 3 represents the part of the manufacturing process of semiconductor device of the present invention;
Fig. 4 represents the part of the manufacturing process of semiconductor device of the present invention;
Fig. 5 represents the part of the manufacturing process of semiconductor device of the present invention;
Fig. 6 represents the part of the manufacturing process of semiconductor device of the present invention;
Fig. 7 represents the part of the manufacturing process of semiconductor device of the present invention;
Fig. 8 represents the part of the manufacturing process of semiconductor device of the present invention;
Fig. 9 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 10 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 11 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 12 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 13 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 14 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 15 is the profile of expression semiconductor device of the present invention;
Figure 16 is the profile of expression semiconductor device of the present invention;
Figure 17 is the profile of expression semiconductor device of the present invention;
Figure 18 is the profile of expression semiconductor device of the present invention;
Figure 19 is the profile of expression semiconductor device of the present invention;
Figure 20 (a) and (b) are profiles of expression semiconductor device of the present invention;
Figure 21 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 22 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 23 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 24 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 25 represents the part of the manufacturing process of semiconductor device of the present invention;
Figure 26 (a) and (b) are the profile of expression semiconductor device of the present invention and the part of manufacturing process;
Figure 27 is the profile of expression semiconductor device of the prior art;
Figure 28 is the profile of expression semiconductor device of the prior art;
Figure 29 represents the part of the manufacturing process of semiconductor device of the prior art;
Figure 30 represents the part of the manufacturing process of semiconductor device of the prior art;
Figure 31 represents the part of the manufacturing process of semiconductor device of the prior art;
Figure 32 represents the part of the manufacturing process of semiconductor device of the prior art.
Description of reference numerals
1: semiconductor substrate; 2: epitaxial loayer; 3: channel layer; 4: groove; 5: dielectric film; 6: grid; 7: source layer; 8: body layer; 9: source electrode; 10: element isolation film; 11: peristome; 12: drain electrode; 13: diaphragm; 14: gate terminal; 15: drain terminal; 101: semiconductor substrate; 102: drift region; 103: base region; 104: emitter region; 105: grid oxidation film; 106: grid; 107: dielectric film; 108: emitter; 109: peristome; 110: the collector region; 111: collector electrode; 201: semiconductor substrate; 202: epitaxial loayer; 203: channel layer; 204: groove; 205: dielectric film; 206: grid; 207: source layer; 208: body layer; 209: source electrode; 210: element isolation film; 212B: drain electrode; 301: semiconductor substrate; 302: drift region; 303: base region; 304: emitter region; 305: grid oxidation film; 306: grid; 307: dielectric film; 308: emitter; 310: the collector region; 311 collector electrodes
Embodiment
Below, with reference to accompanying drawing semiconductor device of the present invention and manufacture method thereof are elaborated.
At first, with reference to Fig. 1～Figure 15, the present invention is applicable to the situation of longitudinal type MOS transistor is specifically described.
Fig. 1 represents longitudinal type MOS transistor of the present invention, and Fig. 1 (a) is a plane graph, and Fig. 1 (b) is the profile along its X-X line.
On N type semiconductor substrate 1, form N-type epitaxial loayer 2, on the first type surface of epitaxial loayer 2, form P type channel layer 3.
In addition, groove 4 arrives epitaxial loayer 2 and forms from the top layer of channel layer 3.And, in groove 4, be embedded with the conductive layer that constitutes by polysilicon film that is insulated that film 5 surrounds, constitute grid 6.
In addition, the top layer of epitaxial loayer 2 and groove 4 in abutting connection with and form N+ type source layer 7, stride across between the source layer 7 of adjacency and form P+ type body layer 8.Then, be electrically connected with each source layer 7 and form the source electrode 9 that for example constitutes by Al.
On the other hand, be formed with peristome 11, on peristome 11, be formed with the drain electrode 12 that for example constitutes by Al etc. at the back side of semiconductor substrate.
In the present embodiment, the part of the current path of semiconductor substrate is replaced as the drain electrode 12 of peristome 11.Therefore, in the present invention,, just realize identical in fact low resistanceization not with semiconductor substrate 1 filming.
Then, the manufacture method to longitudinal type MOS transistor of the present invention describes.
At first, as shown in Figure 2, on the surface of the semiconductor substrate 1 of for example 200 μ m, make for example 10 μ m of N-type epitaxial loayer 2 growths.
Then, as shown in Figure 3, inject B (boron), BF at epitaxial loayer 2 intermediate ions
2(boron difluoride) etc. also heat-treats, and forming thickness on the first type surface of epitaxial loayer 2 for example is the P type channel layer 3 of 1.5 μ m.In addition, by this heat treatment, form oxide-film 13 on the surface of channel layer 3.
Then, as shown in Figure 4, utilize photoetching technique that composite membrane 13A such as the nitride film that formed by CVD on oxide-film 13 or oxide-film are carried out composition.Then, carry out etching with composite membrane 13A as mask, for example making opening diameter is the groove 4 arrival epitaxial loayers 2 of 0.4 μ m.
Then, as shown in Figure 5, remove composite membrane 13A, heat-treat then etc., the peristome bight and the bottom corner chamfering of groove 4 by etching.
Then, as shown in Figure 6, in groove 4, form oxide-film 5 by thermal oxidation, and then, polysilicon layer 14 piled up by CVD.
Then, as shown in Figure 7, polysilicon layer 14 etching repeatedly (エ Star チ バ Star Network) is formed grid 6.At this moment, preferably make the upper end of described grid 6 be in the position of a few μ m under the surface of channel layer 3.
Then, as shown in Figure 8,, carry out etching repeatedly and expose up to the surface of channel layer 3 piling up oxide-film by CVD on the grid 6 and on the oxide-film 5.Thus, the upper face side of grid 6 becomes the state that is capped with oxide-film 5 one.
Then, as shown in Figure 9, form after the diaphragm 15, inject B (boron), BF to channel layer 3 ions
2(boron difluoride) etc. by carrying out the heat treatment under oxygen atmosphere or nitrogen environment, forms P+ type body layer 8.
Then, as shown in figure 10, form after the diaphragm 16, the upper layer part ion of relative channel layer 3 injection As (arsenic) etc. also heat-treat, and form N+ type source layer 7.
Then, as shown in figure 11, dielectric film covered substrates such as BPSG are comprehensive, and dielectric film is carried out composition and source layer 7 and body layer 8 are exposed, and form element isolation film 10.
Then, as shown in figure 12, metal materials such as aluminium are covered the surface of semiconductor substrate 1, form source electrode 9 by photoetching, alloying by sputtering method or vapour deposition method.
Then, as shown in figure 13, form diaphragm 17, then diaphragm 17 is carried out etching as mask to semiconductor substrate 1, form by for example having the hole of 25 μ m～30 μ m opening diameters or the peristome 11 that groove constitutes at the back side of semiconductor substrate 1.In addition, peristome 11 is preferably formed on the position corresponding with the bottom of source layer 7.
Then, as shown in figure 14, form barrier layer (not shown) and inculating crystal layer (not shown), form the drain electrode 12 that for example constitutes then by the Cu layer at the back side of semiconductor substrate.In addition, as shown in figure 15, drain electrode 12A also can not imbed in the peristome 11, but forms than unfertile land along peristome 11.
More than, in the present invention, connect resistance and reduce by forming peristome 11, therefore, even, also can suppress the warpage of semiconductor substrate 1 through following heat treated operation.
Then, with reference to Figure 16～Figure 25, the present invention is applicable to the situation of NPT type IGBT is specifically described.
Figure 16 is the profile of expression longitudinal type MOS transistor of the present invention.
Face side at N-N-type semiconductor N substrate 101 is formed with the MOS structure.That is, the first type surface at N-type drift region 102 forms P type base region 103 selectively.And then, form N+ type emitter region 104 selectively at the first type surface of base region 103.In addition, if only when being conceived to the structure of face side, emitter region 104 play with MOS transistor in source, drain electrode identical functions.And the surface of the base region 103 that the position that clips with emitter region 104 and drift region 102 at least is corresponding all covers, and forms grid 106 via grid oxidation film 105.In addition, grid 106 for example uses polysilicon, polysilicon-metal silicide (Port リ サ イ De) etc. as electrode material.Grid 106 is insulated film 107 and surrounds.At this, as long as dielectric film 107 is cover gate 106 and be provided with peristome on emitter region 104, then applicable other Any shape.Then, cover dielectric film 107, and connect emitter region 104 and be formed with emitter 108.In addition, emitter 108 is for example formed by Al, Cu etc.
On the other hand, the rear side at semiconductor substrate 101 is formed with peristome 109.At this, as hereinafter described, the degree of depth of the drift region 102 of the degree of depth of peristome 109 decision essence.Particularly, in NPT type IGBT, under situation,, therefore, peristome 109 is deepened because the substantial depth of drift region 102 is shoaled for low pressure resistant type.For example, when the thickness that makes semiconductor substrate 101 was 150 μ m, in the NPT of withstand voltage 600V type IGBT, peristome 109 formed the degree of depth of 60 μ m.
In addition, be formed with P+ type collector region 110 in the bottom of peristome 109.At this, when the state that semiconductor device is connected, owing to supply with the hole to drift region 102, so impurity concentration is set corresponding to desirable connection resistance in collector region 110.Particularly, when the concentration of collector region 110 being set big,, therefore, connect resistance decreasing because more hole is fed to drift region 102.But when the concentration of collector region 110 is set when too much, when disconnecting, 110 electronics of accumulating are from time increase that collector electrode 110 is promptly discharged in the collector region.That is, in this case,, therefore, become the characteristic that is not suitable as switch etc. because the time that disconnects increases.
But in semiconductor device of the present invention, 110 bottoms at peristome 109, collector region form.Therefore, can be in IGBT built-in FWD, in the converter of motor driver etc., can reduce work hours, number of spare parts.Specifically describe, at grid 106 from connecting when disconnecting conversion, promptly, between emitter 108 and collector electrode 111, be applied with under the state of collector voltage, when between emitter 108 and grid 106, only applying 0V or the grid voltage below the threshold value, channel region is returned as the p type, and electronics does not inject to drift layer 102 from emitter 108.Therefore, to drift layer 102 injected hole not, drift region becomes high resistance, therefore, does not flow through collector current from collector layer 110.And, under this state, between emitter 108 and collector electrode 111, when applying voltage by the motor load that for example is connected with the outside, electric current flows through successively via the periphery and the collector electrode 111 of emitter 108, base region 103, drift layer 102, peristome 109.That is, from emitter 108 to the current path that collector electrode 111 flows, have not via the current path of collector region 110, this current path plays the function of FWD.
Then, on peristome 109, be electrically connected with collector region 110 and imbedded collector electrode 111.As the electrode material of collector electrode 111, for example use Cu, Al, polysilicon etc.In addition, as shown in figure 17, collector electrode 111 also can form via dielectric film 13.
But peristome 109 does not change at the area of section of depth direction, be vertically formed with depth direction, but the present invention is not limited thereto.For example, as shown in figure 18, peristome 109 also can form from the rear side of semiconductor substrate 101 and diminish towards contact-making surface, its area of section with collector region 110.In this case, when forming collector region 110, when ion injected, ion was difficult for colliding the sidewall of peristome.
In addition, as shown in figure 19, it is desirable to, during corresponding between each base region 103 and formation collector region 110, current efficiency is good.That is, when connecting, in the face side of semiconductor substrate 101, electronics supplies between each base region 103 via raceway groove, and this raceway groove is formed on the base region 102 with grid 106 bottom correspondence positions.Therefore, electronics flows through the surface and the back side with the shortest distance.
In addition, shown in Figure 20 (b) of Figure 20 (a) and its plane graph, also can on an element, only form one group of peristome 109 and collector region 110.Even this shape also helps to improve the mechanical strength of the semiconductor substrate 101 corresponding with surrounding collector electrode 111 parts.
Then, the action to NPT type IGBT of the present invention describes.
More than, even NPT type IGBT of the present invention not with the semiconductor substrate filming, also can and lack for low on-resistance opening time, is applicable to switch element etc.
Then, the manufacture method to semiconductor device of the present invention describes.
At first, as shown in figure 21, prepare N-N-type semiconductor N substrate 101.Then, the surface of the face side of thermal oxidation semiconductor substrate 101 forms oxide-film 105a, and then, on oxide-film 105a, pile up gate members 106a.In addition, gate members 106a for example uses polysilicon, polysilicon-metal silicide etc.
Then, as shown in figure 22,, utilize photoetching technique and etching technique, form grid oxidation film 105 and grid 106 for oxide-film 105a and gate members 106a.Then, be mask with grid 106, p type impurities such as boron ion implantation form P type base region 103.And then the assigned position on base region 103 forms the photoresist film 114a with peristome, then, injects N type impurity such as phosphorus with high concentration ion, forms N+ type emitter region 104 by implementing heat treatment.In addition, by implementing heat treatment, under the situation that the emitter region 104 of adjacency connects each other, for each emitter region 104 is separated, and at the p type impurity of the position ion injection high concentration of separating.At this, on semiconductor substrate 101, will be drift region 102 with corresponding zone definitions except that base region 103 or described emitter region 104.
Then, as shown in figure 23, all cover the face side of semiconductor substrate 101 and form dielectric film, then, utilize photoetching technique and etching technique, form the dielectric film 107 of the part opening corresponding with emitter region 104 tops.And then, imbed emitter materials such as Al in order to connect emitter region 104, form emitter 108.
Then, as shown in figure 24,, be that mask carries out etching with the photoresist figure afterwards at the rear side formation photoresist figure of semiconductor substrate 101, form peristome 109.At this, the essence thickness of the degree of depth of peristome 109 decision drift region 102.That is to say that in the operation of back, in the bottom of peristome 109, owing to form collector region 110, therefore, the raceway groove that forms and the distance of collector region 110 are by the degree of depth decision of peristome 109 when connecting.For example, when the thickness of semiconductor substrate 1 is about 150 μ m, in the IGBT of withstand voltage 600V, the about 60 μ m of the back etched of semiconductor substrate 1 are formed peristome 109, so that the essence thickness of drift region is 90 μ m.
At this, the shape of peristome 109 is suitable for different shape according to desirable function, corresponding to this, selects different engraving methods.For example, vertical for making peristome 109 with depth direction, can select anisotropic etching, can also select Bosch technology (ボ Star シ ユ プ ロ セ ス).At this, Bosch technology is meant by will mainly utilizing the plasma etching process of SF6 gas and mainly utilizing the plasma deposition process alternate repetition of C4F8 gas to carry out, can be with the vertically dark etching method of substrate.In addition, in Bosch technology, produce wavy fluffing shape on the internal face of peristome 109, this shape can the initiation problem in the operation of back.For example, ion is carried out in the bottom of peristome 109 inject and the operation of formation collector region 110, wavy fluffing shape can become the barrier that ion injects.In addition, when forming peristome 109 imperceptibly, wavy fluffing shape becomes barrier during the embedded electrode material in peristome 109.Be difficult to electrode material is embedded to fully in peristome 109.Thereby, can for example after Bosch technology, further carry out dry ecthing, make the inwall planarization of peristome 109.In addition, also can under the abundant situation in the interval between each peristome 109, select isotropic etching.
Then, as shown in figure 25, heat-treat, in peristome 109, form thin protective oxide layer 112.Then, p type impurity is injected at the vertical direction ion, form P+ type collector region 110 in the bottom of peristome 109.It is 1 * 10 with boron concentration for example that this ion injects
13/ cm
2, acceleration energy is that 50keV carries out.But, inject at ion, it is difficult injecting ion in complete vertical direction, a part is in oblique acceleration.To this, in the present embodiment since peristome 109 in formation protective oxide layer 112, therefore, do not inject ion at the sidewall of peristome 109.On the other hand, also be formed with protective oxide layer 112, but owing to quickened fully at the vertical direction ion, therefore, this direction ion is injected fully relatively in the bottom of peristome.
Then, as shown in figure 26, remove after the protective oxide layer 112, form fixed photoresist figure, in peristome 109, imbed collector material then, form the collector electrode 111 that is connected with the collector region.This collector material for example uses Cu, Al.In addition, as collector material, also can use polysilicon, in this case, because semiconductor substrate 101 is little with the difference of thermal coefficient of expansion, therefore, stability improves.
More than, in the present invention, even not with the semiconductor substrate filming, the also attenuation corresponding to the degree of depth of peristome of essence thickness of semiconductor substrate can suppress the warpage of semiconductor substrate.
In addition, should think that current disclosed execution mode only is example and not imposing any restrictions in all respects.Scope of the present invention not merely is the explanation of above-mentioned execution mode, but discloses by inventing claimed scope, in addition, comprises and the implication of inventing claimed scope equalization and all interior changes of scope thereof.
For example, in execution mode, in the longitudinal type MOS transistor, grid 6 is formed in the groove 4, and in NPT type IGBT, grid 106 is formed on the semiconductor substrate 101.But the present invention does not limit by grid structure.For example, in the longitudinal type MOS transistor, grid also can be formed on the semiconductor substrate, and in NPT type IGBT, grid also can be the ditch type.
In addition, as shown in figure 15, in the longitudinal type MOS transistor, 12 do not imbed peristome 11 but be illustrated than the execution mode that unfertile land forms along peristome 11 to draining, but in NPT type IGBT, collector electrode 111 also can not imbedded peristome 109 and form than unfertile land along peristome 11.When drain electrode 12 and collector electrode 111 when forming than unfertile land like this, not only bring cost degradation, and owing to the warpage of the difference of the thermal coefficient of expansion of semiconductor substrate 1,101 also reduces.
In addition, in the longitudinal type MOS transistor, on semiconductor substrate 1, form epitaxial loayer 2, in NPT type IGBT, on semiconductor substrate 101, do not form epitaxial loayer 2.But, no matter having or not of the present invention's epitaxial loayer is all suitable equally.
In addition, in the execution mode of NPT type IGBT, as shown in figure 20, peristome 109 is formed on the only position except the periphery of semiconductor substrate 101, but this execution mode is suitable for too for the longitudinal type MOS transistor.
In addition, in the explanation of execution mode, peristome 11,111 only forms the quantity identical with grid 6,206.But the present invention is not limited to this, and peristome 11,111 also can be than grid 6,206 miniaturizations more, many, the formation randomly of quantity.In this case, even do not carry out the location of peristome 11,111 and grid 6,206, also be difficult to produce the centralization of current density.
In the explanation of each execution mode, peristome 11,111 all forms same shape.But the present invention is not limited to this, peristome 11,111 for example also can bore and the degree of depth form differently.
For example, in the longitudinal type MOS transistor shown in Figure 26 (a), be formed with source electrode 9, gate terminal 14 and drain terminal 15 in face side.At this, gate terminal 14 is the terminals that are electrically connected with grid 6 by not shown connection distribution.In addition, drain terminal 15 is to be used for the terminal of drain current from the drain electrode derivation.In other words, because source electrode 9, gate terminal 14 and drain terminal 15 are formed on same plane, therefore, the longitudinal type MOS transistor can be installed by upside-down mounting.
In this constituted, the peristome 11b that forms in the position suitable with drain terminal 15 bottoms deeper formed than the peristome 11a that forms in the position suitable with source electrode 9 bottoms.In other words, do not form channel layer 3 in the position suitable with drain terminal 15 bottoms, but owing to drain electrode 12 extends near the drain terminal 15, so resistance reduces.Thus, drain current 12 is derived to drain terminal 15 from draining easily.
In addition, with suitable position, gate terminal 14 bottoms owing to do not form the current path of drain current, therefore can not form peristome 11.
And, when the diameter of the peristome 11b ratio open 11a of portion is big, preferably they are formed simultaneously by an etching.
In other words; shown in Figure 26 (b); diaphragm 13 for the back etched of semiconductor substrate 1 time; bigger and when carrying out composition at the position 13b that makes corresponding peristome 11b than the diameter of the position 13a of corresponding peristome 11a; if this diaphragm 13 is carried out etching as mask, then form peristome 11a and peristome 11b simultaneously by an etching.For example, the opening diameter of peristome 11a, 11b ratio is to design in about 1: 4, and particularly, the opening diameter of peristome 11a can be for about 10 μ m, and the opening diameter of peristome 11b can be for about 40 μ m.The difference of the miniature roll extrusion effect (マ イ Network ロ ロ one リ Application グ effect) when this is based on the etching of position 13a, 13b.In other words, when the diameter of peristome 11 became big, etching gas entered easily, and in addition, the residue that produces during etching is discharged easily, and etched tempo accelerates.
In addition, in Figure 26 (a), peristome 11b opening is in the way of epitaxial loayer 2, but the present invention is not limited to this, and for example, peristome 11b can connect epitaxial loayer 2 and arrive drain terminal 15.Thus, drain current 12 is derived to drain terminal 15 from draining better.
And, at the execution mode that designs difference in shape of these peristomes 11, be suitable for too for IGBT.
Claims (19)
1. semiconductor device, the longitudinal stream overcurrent at semiconductor substrate is characterized in that having: the MOS structure, it is formed on the face side of described semiconductor substrate; Peristome, it is formed on the rear side of described semiconductor substrate; Backplate, it is connected with the bottom electrical of described peristome.
2. semiconductor device as claimed in claim 1 is characterized in that,
Described semiconductor substrate is first conductivity type,
Described MOS structure has: the second conductive type of channel layer, and it is formed on the face side of described semiconductor substrate; A plurality of gate insulating films and grid; The first conductivity type source electrode layer, itself and described gate insulating film in abutting connection with and form; Source electrode, it is electrically connected and forms with described source layer,
The function of drain region is played in described bottom, and described backplate is drain electrode.
3. semiconductor device as claimed in claim 1 is characterized in that,
Described semiconductor substrate is first conductivity type,
Described MOS structure has: the second conductivity type base region, and it is formed on the face side at described semiconductor substrate; A plurality of gate insulating films and grid; The first conductivity type emitter region, itself and described gate insulating film in abutting connection with and form; Emitter, it is electrically connected and forms with described emitter region,
Be formed with the second conductive collector zone in described bottom, described backplate is a collector electrode.
4. as each described semiconductor device in the claim 1～3, it is characterized in that the periphery of described peristome has the function of the mechanical strength that keeps described semiconductor substrate.
5. as claim 2 or 3 described semiconductor devices, it is characterized in that described grid is the ditch type.
6. semiconductor device as claimed in claim 2 is characterized in that described peristome forms corresponding to the position of described source layer.
7. semiconductor device as claimed in claim 3 is characterized in that described peristome forms corresponding to the position of described emitter region.
8. semiconductor device as claimed in claim 4 is characterized in that, described peristome is formed on all parts except that described semiconductor substrate periphery.
9. as each described semiconductor device in the claim 1～8, it is characterized in that described peristome is coated with dielectric film in the part except that described bottom.
10. semiconductor device as claimed in claim 3 is characterized in that, the periphery of described peristome is formed with the current path of FWD.
11. as each described semiconductor device in the claim 1～10, it is characterized in that, be formed with the terminal that is used for from described backplate derived current on the surface of described semiconductor substrate, first peristome that described peristome is formed by the bottom in described MOS structure and second peristome that forms in the bottom of described terminal are formed, and described second peristome forms deeplyer than described first peristome.
12. semiconductor device as claimed in claim 11 is characterized in that, described second peristome is bigger than the diameter of first peristome.
13., it is characterized in that described second peristome is offered to described terminal as claim 11 or 12 described semiconductor devices.
14. the manufacture method of a semiconductor device is characterized in that, has:
Form the operation of MOS structure in the face side of the semiconductor substrate of first conductivity type;
Form the operation of photoresist figure in the rear side of described semiconductor substrate;
With described photoresist figure is that mask carries out the operation that etching forms peristome;
Be connected with the bottom electrical of described peristome and form the operation of backplate.
15. the manufacture method of semiconductor device as claimed in claim 14 is characterized in that, has the operation that second conductive-type impurity is injected into the bottom of described peristome and forms the collector region.
16. the manufacture method as claim 14 or 15 described semiconductor devices is characterized in that described backplate is formed by polysilicon.
17. the manufacture method as each described semiconductor device in the claim 14～16 is characterized in that, described peristome is formed on the part except that described semiconductor substrate periphery.
18. manufacture method as each described semiconductor device in the claim 14～17, it is characterized in that, be formed with the terminal that is used for from described backplate derived current on the surface of described semiconductor substrate, described photoresist figure with compare corresponding to the position of described MOS structure bottom, at bigger ground, position opening corresponding to described terminal bottom.
19. the manufacture method of semiconductor device as claimed in claim 18 is characterized in that, described peristome is offered to described terminal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP072645/06 | 2006-03-16 | ||
| JP2006072645 | 2006-03-16 | ||
| JP215906/06 | 2006-08-08 | ||
| JP042703/07 | 2007-02-22 |
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| CN101060133A true CN101060133A (en) | 2007-10-24 |
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| CN 200710088556 Pending CN101060133A (en) | 2006-03-16 | 2007-03-16 | Semiconductor device and manufacturing method thereof |
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