CN102254939A - Vertical double-diffusion MOS (metal-oxide semiconductor) transistor and manufacturing method thereof - Google Patents
Vertical double-diffusion MOS (metal-oxide semiconductor) transistor and manufacturing method thereof Download PDFInfo
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- CN102254939A CN102254939A CN2011102251848A CN201110225184A CN102254939A CN 102254939 A CN102254939 A CN 102254939A CN 2011102251848 A CN2011102251848 A CN 2011102251848A CN 201110225184 A CN201110225184 A CN 201110225184A CN 102254939 A CN102254939 A CN 102254939A
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Abstract
The invention relates to a vertical double-diffusion MOS (metal-oxide semiconductor) transistor and a manufacturing method thereof. The vertical double-diffusion MOS transistor comprises a substrate and an epitaxial layer formed at one side of the substrate, wherein the other side of the substrate comprises a plurality of V-shaped grooves; the surface of the substrate covers a drain electrode; and the drain electrode is changed along with the shape of the substrate to form a V-shaped groove. The vertical double-diffusion MOS transistor can be utilized to shorten the distance between a source area and the drain electrode, thus reducing on-resistance and on-pressure drop and improving the current of the drain electrode.
Description
Technical field
The present invention relates to a kind of vertical double-diffused MOS transistor (Vertical double-diffused metal oxide semiconductor, VDMOS) and preparation method thereof.
Background technology
Power MOS field effect transistor is the power switching device of new generation that grows up on MOS integrated circuit technology basis.A series of unique features such as the vertical double-diffused MOS transistor device has the input impedance height, switching speed is fast, operating frequency is high, voltage control, Heat stability is good obtain to use widely at aspects such as switching power supply, high-frequency heating, computer interface circuit and power amplifiers at present.
Fig. 1 is a kind of cross-sectional view of vertical double-diffused MOS transistor of prior art.Described vertical double-diffused MOS transistor comprises substrate 11, be formed at the epitaxial loayer 12 of described substrate 11 1 sides, be formed at described substrate 11 opposite sides drain electrode 13, be formed at the gate oxide 16 on described epitaxial loayer 12 surfaces and the polysilicon layer 17 that is formed at described gate oxide 16 surfaces.Be provided with P type well region 15 in the described epitaxial loayer 12, be provided with source region 14 in the described P type well region 15.After raceway groove was opened, electronics flowed to drain electrode 13 by flow through raceway groove, epitaxial loayer 12, substrate 11 of described source region 14.
Summary of the invention
The object of the present invention is to provide a kind of vertical double-diffused MOS transistor that can further reduce conducting resistance.
Another object of the present invention is to provide the preparation method of above-mentioned vertical double-diffused MOS transistor.
A kind of vertical double-diffused MOS transistor, the epitaxial loayer that comprises substrate and be formed at described substrate one side, the opposite side of described substrate comprises a plurality of " V " connected in star, the surface coverage drain electrode of described substrate, and described drain electrode also forms " V " connected in star with the shape of described substrate.
A kind of preparation method of vertical double-diffused MOS transistor comprises the steps: to provide a substrate, at the side formation epitaxial loayer of described substrate; With described substrate upset, described substrate is provided with under the side direction of described epitaxial loayer, opposite side is upwards; A side etching that makes progress at described substrate forms a plurality of " V " connected in star; The side surface with groove at described substrate forms drain electrode, and described drain electrode also forms " V " connected in star with the shape of described substrate; With substrate upset of living in, make under the side direction with groove of described substrate, have on the side direction of described epitaxial loayer.
A kind of preparation method of vertical double-diffused MOS transistor comprises the steps: to provide a substrate, forms a plurality of " V " connected in star in described substrate one side etching; The side surface with groove at described substrate forms drain electrode, and described drain electrode also forms " V " connected in star with the shape of described substrate.
As the preferred technique scheme, the degree of depth of described " V " connected in star is 5 microns, and the width of described " V " connected in star is 10 microns, and the thickness of described substrate is 65 microns.
Compared with prior art, one side of the substrate of vertical double-diffused MOS transistor of the present invention comprises a plurality of " V " connected in star, drain electrode also forms " V " connected in star with the shape of described substrate, shorten the distance between source region and the drain electrode, thereby reduced conductor resistance and conduction voltage drop, raising drain current.
Description of drawings
Fig. 1 is a kind of cross-sectional view of vertical double-diffused MOS transistor of prior art;
Fig. 2 is the cross-sectional view of vertical double-diffused MOS transistor of the present invention;
Fig. 3 is each step schematic diagram of the preparation method of vertical double-diffused MOS transistor of the present invention to Fig. 7.
Embodiment
The substrate of vertical double-diffused MOS transistor of the present invention and drain electrode form a plurality of grooves, have shortened the distance between source region and the drain electrode, thereby have reduced conducting resistance and conduction voltage drop, raising drain current.For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 2 is the cross-sectional view of vertical double-diffused MOS transistor of the present invention.Described vertical double-diffused MOS transistor comprises substrate 21, is formed at the epitaxial loayer 22 of described substrate 21 1 sides, is formed at the gate oxide 26 on described epitaxial loayer 22 surfaces and the polysilicon layer 27 that is formed at described gate oxide 26 surfaces.Be provided with well region 25 in the described epitaxial loayer 22, be provided with source region 24 in the described well region 25.Preferably, described substrate 21 can be N+ type substrate, and described epitaxial loayer 22 is a N-type epitaxial loayer, and described well region 25 is a P type well region, and described source region 24 is N+ type source region.
The opposite side of described substrate 21 comprises a plurality of " V " connected in star, the surface coverage drain electrode 23 of described substrate 21, and described drain electrode 23 also forms " V " connected in star with the shape of described substrate 21.Preferably, the degree of depth of described " V " connected in star is 5 microns, and the width of described " V " connected in star is 10 microns, and the thickness of described substrate 21 is 65 microns.
The substrate 21 of vertical double-diffused MOS transistor of the present invention and drain electrode 23 form a plurality of grooves, have shortened source region 24 and the distance between 23 of draining.After raceway groove was opened, electronics flowed to drain electrode 23 by source region 24 through raceway groove, epitaxial loayer 22, substrate 21.Vertical double-diffused MOS transistor of the present invention helps reducing conductor resistance and conduction voltage drop, raising drain current.
Fig. 3 is each step schematic diagram of the preparation method of vertical double-diffused MOS transistor of the present invention to Fig. 7.The preparation method of vertical double-diffused MOS transistor of the present invention comprises the steps:
One substrate 21 is provided, forms epitaxial loayer 22 in a side of described substrate 21 by doping way.Preferably, the thickness of described substrate 21 is 65 microns.After forming described epitaxial loayer 22, continue to form well region 25, source region 24, gate oxide 26 and the polysilicon layer 27 of described vertical double-diffused MOS transistor, as shown in Figure 3.The formation method of this step is same as the prior art, does not repeat them here.
With described substrate 21 upsets, described substrate 21 is provided with under the side direction of described epitaxial loayer 22, opposite side makes progress, as shown in Figure 4.
A side that makes progress at described substrate 21 forms the photoresistance pattern, is the described substrate 21 of mask etching with described photoresistance pattern, makes the surface of described substrate 21 form a plurality of " V " connected in star 29, as shown in Figure 5.Preferably, the width of described " V " connected in star 29 is 10 microns, and the degree of depth of described " V " connected in star is 5 microns.
The side surface with groove 29 at described substrate 21 forms drain electrode 23, and described drain electrode 23 also forms " V " connected in star with the shape of described substrate 21, as shown in Figure 6.
With described substrate 21 upsets, make under the side direction with groove of described substrate 21, have on the side direction of described epitaxial loayer 22, as shown in Figure 7.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (10)
1. vertical double-diffused MOS transistor, the epitaxial loayer that comprises substrate and be formed at described substrate one side, it is characterized in that: the opposite side of described substrate comprises a plurality of " V " connected in star, the surface coverage drain electrode of described substrate, and described drain electrode also forms " V " connected in star with the shape of described substrate.
2. vertical double-diffused MOS transistor according to claim 1 is characterized in that, the degree of depth of described " V " connected in star is 5 microns.
3. vertical double-diffused MOS transistor according to claim 1 is characterized in that, the width of described " V " connected in star is 10 microns.
4. vertical double-diffused MOS transistor according to claim 1 is characterized in that, the thickness of described substrate is 65 microns.
5. the preparation method of a vertical double-diffused MOS transistor is characterized in that, comprises the steps:
Provide a substrate, at the side formation epitaxial loayer of described substrate;
With described substrate upset, described substrate is provided with under the side direction of described epitaxial loayer, opposite side is upwards;
A side etching that makes progress at described substrate forms a plurality of " V " connected in star;
The side surface with groove at described substrate forms drain electrode, and described drain electrode also forms " V " connected in star with the shape of described substrate;
With substrate upset of living in, make under the side direction with groove of described substrate, have on the side direction of described epitaxial loayer.
6. the preparation method of vertical double-diffused MOS transistor according to claim 5 is characterized in that, the degree of depth of described " V " connected in star is 5 microns.
7. the preparation method of vertical double-diffused MOS transistor according to claim 5 is characterized in that, the width of described " V " connected in star is 10 microns.
8. the preparation method of vertical double-diffused MOS transistor according to claim 5 is characterized in that, the thickness of described substrate is 65 microns.
9. the preparation method of a vertical double-diffused MOS transistor is characterized in that, comprises the steps:
One substrate is provided, forms a plurality of " V " connected in star in described substrate one side etching;
The side surface with groove at described substrate forms drain electrode, and described drain electrode also forms " V " connected in star with the shape of described substrate.
10. the preparation method of vertical double-diffused MOS transistor according to claim 9 is characterized in that, the degree of depth of described " V " connected in star is 5 microns, and the width of described " V " connected in star is 10 microns, and the thickness of described substrate is 65 microns.
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| CN2011102251848A CN102254939A (en) | 2011-08-08 | 2011-08-08 | Vertical double-diffusion MOS (metal-oxide semiconductor) transistor and manufacturing method thereof |
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| CN2011102251848A CN102254939A (en) | 2011-08-08 | 2011-08-08 | Vertical double-diffusion MOS (metal-oxide semiconductor) transistor and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021046805A1 (en) * | 2019-09-12 | 2021-03-18 | 苏州晶湛半导体有限公司 | Method for manufacturing vertical-type device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6263472A (en) * | 1985-09-13 | 1987-03-20 | Sharp Corp | Power mos-fet |
| US5065219A (en) * | 1990-05-21 | 1991-11-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
| CN101060133A (en) * | 2006-03-16 | 2007-10-24 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN101719472A (en) * | 2009-11-18 | 2010-06-02 | 上海宏力半导体制造有限公司 | Method for preparing vertical double-diffusion MOS transistor |
-
2011
- 2011-08-08 CN CN2011102251848A patent/CN102254939A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6263472A (en) * | 1985-09-13 | 1987-03-20 | Sharp Corp | Power mos-fet |
| US5065219A (en) * | 1990-05-21 | 1991-11-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
| CN101060133A (en) * | 2006-03-16 | 2007-10-24 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN101719472A (en) * | 2009-11-18 | 2010-06-02 | 上海宏力半导体制造有限公司 | Method for preparing vertical double-diffusion MOS transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021046805A1 (en) * | 2019-09-12 | 2021-03-18 | 苏州晶湛半导体有限公司 | Method for manufacturing vertical-type device |
| US11908686B2 (en) | 2019-09-12 | 2024-02-20 | Enkris Semiconductor, Inc. | Methods of manufacturing vertical device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140430 |
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