CN103578997A - Manufacturing method of LDMOS grid electrode and product - Google Patents
Manufacturing method of LDMOS grid electrode and product Download PDFInfo
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- CN103578997A CN103578997A CN201210265532.9A CN201210265532A CN103578997A CN 103578997 A CN103578997 A CN 103578997A CN 201210265532 A CN201210265532 A CN 201210265532A CN 103578997 A CN103578997 A CN 103578997A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 114
- 229920005591 polysilicon Polymers 0.000 claims abstract description 111
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
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- 229910052782 aluminium Inorganic materials 0.000 claims description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses a manufacturing method of a grid electrode of a transverse double-diffusion metal-oxide semiconductor field effect transistor and a product. The method includes the steps of manufacturing drain regions, source regions and a polysilicon gate of an LDMOS through an interdigital plane structure, manufacturing a plurality of newly-increased field regions in a source region between every two adjacent drain regions, manufacturing polycrystalline silicon layer protrusions in the newly-increased field regions so that the polycrystalline silicon layer protrusions penetrate through the source regions to be connected with the polysilicon gate, setting distances on the polysilicon gate at intervals to manufacture a plurality of the polycrystalline silicon layer protrusions which penetrate through the source regions adjacent to the polysilicon gate and extend to the field regions outside the source regions, manufacturing contact holes in the polycrystalline layer protrusions, manufacturing a metal wire, and connecting all the contact holes in the polycrystalline layer protrusions in series with the metal wire so that the problems that in the prior art, resistance of a grid electrode is large and an LDMOS is low in on-off speed can be solved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly a kind of manufacture method of LDMOS grid and product.
Background technology
LDMOS(lateral double-diffusion metal oxide semiconductor field effect transistor, lateral double diffusion metal oxide semiconductor field effect transistor) owing to being easy to the Semiconductor with CMOS(Complementary metal Oxide, complementary metal oxide semiconductors (CMOS)) process compatible and being widely adopted.
The formation of LDMOS comprises well region, source region, drift region, drain region, gate oxide and polysilicon gate, and wherein source region, drain region and polysilicon gate adopt respectively after metal wire draws, and forms three electrodes of LDMOS, is respectively source electrode, drain and gate.
In LDMOS, within above-mentioned source region, drain region and channel region (channel region is the region that gate oxide and polysilicon gate cover) is all included in active area, active area is the region that does not have field oxide to cover in semiconductor device; In semiconductor device, the region being covered by field oxide is called place.
The parameter of weighing LDMOS device property has a lot, comprises static parameter and dynamic parameter, and wherein static parameter comprises puncture voltage, conducting resistance, threshold voltage etc., and dynamic parameter comprises switching speed etc.Switching speed is mainly by resistance (resistance of polysilicon gate self) and grid capacitance (electric capacity that gate oxide produces) decision, and resistance and grid capacitance are less, and switching speed is faster, and the energy consumption of LDMOS in switching process is also just less.
Because source, leakage and three electrodes of grid of LDMOS are all positioned at chip surface, in order to realize the target of the large current work of LDMOS, must adopt interdigitated planar structure: source region and drain region are alternate, and polysilicon gate (or polysilicon gate and drift region) is roundabout between source region, drain region, as shown in Figure 1.
In LDMOS structure, polysilicon gate is roundabout between source region and drain region, and total length reaches several thousand microns even more than 10,000 micron, as Fig. 2 signal, resistance is directly proportional to its length and width, so the resistance of size long polysilicon gate self like this is larger, has had a strong impact on the switching speed of LDMOS.
In prior art, the method that reduces resistance is, (Metal field plate is the metal-layer structure of top, LDMOS drift region polysilicon gate and Metal field plate to adopt contact hole, there is the electric field strength that reduces surface, drift region, thereby increase the effect of the puncture voltage of LDMOS) be connected, make polysilicon gate and Metal field plate in same current potential, Metal field plate is exactly the field plate of grid.And when the Metal field plate of LDMOS need to be connected with source electrode, this method is inapplicable.
Summary of the invention
The embodiment of the present invention provides a kind of manufacture method of LDMOS grid, exists resistance large, the problem that LDMOS switching speed is slow in order to solve in prior art.
The embodiment of the present invention provides a kind of manufacture method of LDMOS grid, comprising: adopt interdigitated planar structure to make drain region, source region and the polysilicon gate of LDMOS; In source region between every two adjacent drain regions, make several places; In above-mentioned place, make polysilicon layer projection, above-mentioned polysilicon layer projection is connected with polysilicon gate through source region, and interval setpoint distance is made a plurality of polysilicon layer projections on polysilicon gate, wherein, each polysilicon layer projection all runs through the source region adjacent with polysilicon gate and extends to the place outside source region; In each polysilicon layer projection, make contact hole; Make metal wire, utilize metal wire that the contact hole in all polysilicon layer projections is together in series.
The embodiment of the present invention provides a kind of electronic product that adopts above-mentioned LDMOS grid making method to make, and comprising: adopt interdigitated planar structure to make drain region, source region and the polysilicon gate of LDMOS; Newly-increased place, is located in the source region between every two adjacent drain regions; Polysilicon layer projection, is arranged in newly-increased place, through source region, is connected with polysilicon gate; And a plurality of polysilicon layer projections, be positioned at interval setpoint distance on polysilicon gate, and run through the source region adjacent with polysilicon gate and extend to the place outside source region; Contact hole, is positioned in each polysilicon layer projection; Metal wire, for being together in series the contact hole in all polysilicon layer projections.
The embodiment of the present invention provides a kind of manufacture method of lateral double diffusion metal oxide semiconductor fet gate, by make several polysilicon layer projections on polysilicon gate, in polysilicon layer projection, make on contact hole, and adopt metal wire that the contact hole in polysilicon layer projection is together in series, thereby make metal wire in parallel with polysilicon gate, reduce the resistance of LDMOS, accelerate the switching speed of LDMOS, alleviate zones of different inconsistent problem switching time of LDMOS, and do not have influence on the design and fabrication of the grid of LDMOS and the Metal field plate of source electrode.
Accompanying drawing explanation
Fig. 1 is the interdigitated planar structure of LDMOS of the prior art;
Fig. 2 is the floor map of the polysilicon gate of LDMOS in prior art;
Fig. 3 is the floor map of the LDMOS in the embodiment of the present invention;
Fig. 4 is the floor map of the polysilicon gate in the embodiment of the present invention;
Fig. 5 is the flow chart of the manufacture method of the LDMOS grid in the embodiment of the present invention;
Fig. 6 is the floor map after the active area of the making LDMOS in the embodiment of the present invention;
Fig. 7 is making polysilicon gate and the polysilicon layer projection floor map afterwards in the embodiment of the present invention;
Fig. 8 is the floor map after the making contact hole in the embodiment of the present invention;
Fig. 9 makes metal wire floor map afterwards in the embodiment of the present invention.
Embodiment
The manufacture method of a kind of lateral double diffusion metal oxide semiconductor fet gate that the embodiment of the present invention provides is, when adopting interdigitated planar structure to make LDMOS grid, Yi Ce edge, close source region at LDMOS polysilicon gate, make a plurality of polysilicon layer projections, make the outer rim of these polysilicon layer projections exceed the border (even above-mentioned polysilicon layer projection extends to the top of field oxide) of active area, and in polysilicon layer projection, exceed in the part on border, active area (being the part of polysilicon layer projection above field oxide) reserved or produce contact hole, then adopt metal wire the contact hole series connection in above-mentioned a plurality of polysilicon layer projections.
The product that the manufacture method of the LDMOS grid providing based on the embodiment of the present invention is produced, as shown in Figure 3, comprising:
Adopt interdigitated planar structure to make 301, source region 302, drain region and the polysilicon gate 303 of LDMOS;
Newly-increased place 304, is located in the source region 302 between every two adjacent drain regions 301;
Contact hole 307, is positioned in each polysilicon layer projection 305;
Metal wire 308, for being together in series the contact hole 307 in all polysilicon layer projections 305.
In practical application, the total length of polysilicon gate reaches several thousand microns even more than 10,000 micron, therefore many times roundabout between source region and drain region, in order clearly to express the planar structure of LDMOS, figure in the embodiment of the present invention all only draws polysilicon gate and is recessed into the roundabout in order to signal of a finger shape, obviously, the embodiment of the present invention comprises polysilicon gate roundabout situation repeatedly between source region and drain region.
As shown in Figure 4, the embodiment of the present invention adopts polysilicon layer projection the very long polysilicon gate of length to be divided into the interval of several little length, with metal wire, all polysilicon layer projections are connected simultaneously, and metal wire is in parallel with polysilicon gate, because the resistance of metal wire is far smaller than the resistance of polysilicon, therefore, the LDMOS resistance in the embodiment of the present invention has been reduced widely.
In the embodiment of the present invention, make the flow process of LDMOS grid specifically as shown in Figure 5:
Step 501: adopt interdigitated planar structure to make active area and the place of LDMOS, active area comprises source region, drain region, raceway groove etc.The distribution of above-mentioned active area and place as shown in Figure 6.
The process that is manufactured with source region and place is, at semiconductor substrate surface, be oxidized out the pad oxide that thickness is 100-300 dust, accumulation thickness is the silicon nitride layer of 1000-2000, then by processing steps such as photoetching, etchings, the silicon nitride of place is got rid of, through location oxidation of silicon process, on surface, place, produce the field oxide that thickness is 4000-10000 dust, then remove the silicon nitride of active area.When adopting common process to be manufactured with source region and place, in source region between every two adjacent drain regions, adopt location oxidation of silicon process to make several newly-increased places and (in the figure of the embodiment of the present invention, only draw a newly-increased place signal, newly-increased a plurality of places are equally applicable to the present invention), this newly-increased place is generally rectangle, the length of side is that 2-5 micron is best, if newly-increased place area is excessive, the source region area taking is excessive.
Step 502: make polysilicon gate and polysilicon layer projection.Make polysilicon gate and polysilicon layer projection floor map afterwards as shown in Figure 7.
Remove the pad oxide of surfaces of active regions, in surfaces of active regions, making thickness is the gate oxide of 100-1000 dust, and then accumulation a layer thickness is the polysilicon of 2000-8000 dust, then by processing steps such as photoetching, etchings, makes polysilicon gate.
When making polysilicon gate, in each newly-increased place, make a polysilicon layer projection, polysilicon layer projection in newly-increased place is connected with polysilicon gate through source region, and interval setpoint distance is made a plurality of polysilicon layer projections on polysilicon gate, wherein, each polysilicon layer projection all runs through the source region adjacent with polysilicon gate and extends to the place outside source region.Preferably, polysilicon layer projection and each polysilicon layer projection that extends to the place outside source region in above-mentioned each newly-increased place are made into the rectangle that the length of side is 1-10 micron, the scope that the polysilicon layer projection completing all exceeds active area extends to place.
Step 503: make contact hole in each polysilicon layer projection.Floor map after making contact hole as shown in Figure 8.
By processing steps such as photoetching, Implantations, adulterated in source region, drain region, then the dielectric layer that deposition thickness is 3000-10000, then by processing steps such as photoetching, etchings, the polysilicon layer in each newly-increased place projection and each extend in the polysilicon layer projection of the place outside source region and all make contact hole, preferably, this contact hole is made as to the rectangle that the length of side is 0.25-3 micron, and contact hole is surrounded completely by place.Contact hole in polysilicon layer projection in each newly-increased place is surrounded completely by newly-increased place, and each contact hole extending in the polysilicon layer projection of the place outside source region is also surrounded completely by the place outside source region.
Step 504: make metal wire, utilize metal wire that the contact hole in all polysilicon layer projections is together in series.Make metal wire floor map afterwards as shown in Figure 9.
Accumulation thickness is the metal level of 4000-30000 dust, then by processing steps such as photoetching, etchings, make and form metal wire, adopt metal wire that the contact hole in the polysilicon layer projection in each newly-increased place and each polysilicon layer projection that extends to the place outside source region is all together in series, the material of making metal wire can be the metal or alloy of the easy conductives such as copper, aluminium.
Because the contact hole in the polysilicon layer projection in the embodiment of the present invention and metal wire be not above drift region, but surrounded completely by place, therefore, when Metal field plate is connected with source electrode, the metal wire of grid and the Metal field plate of source electrode each other independent, can not affect each other, can be in different current potentials, the LDMOS in the embodiment of the present invention compared to existing technologies, can be applied to wider scope like this.
LDMOS grid making method and product that the embodiment of the present invention provides, by make several polysilicon layer projections on polysilicon gate, in polysilicon layer projection, make on contact hole, and adopt metal wire that the contact hole in polysilicon layer projection is together in series, thereby make metal wire in parallel with polysilicon gate, reduce the resistance of LDMOS, accelerate the switching speed of LDMOS, alleviate zones of different inconsistent problem switching time of LDMOS, and do not have influence on the design and fabrication of the grid of LDMOS and the Metal field plate of source electrode.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. a manufacture method for LDMOS lateral double diffusion metal oxide semiconductor fet gate, is characterized in that, comprising:
Adopt interdigitated planar structure to make drain region, source region and the polysilicon gate of LDMOS;
In source region between every two adjacent drain regions, make several newly-increased places;
In described newly-increased place, make polysilicon layer projection, described polysilicon layer projection is connected with polysilicon gate through source region, and interval setpoint distance is made a plurality of polysilicon layer projections on polysilicon gate, wherein, each polysilicon layer projection all runs through the source region adjacent with polysilicon gate and extends to the place outside source region;
In each polysilicon layer projection, make contact hole;
Make metal wire, utilize metal wire that the contact hole in all polysilicon layer projections is together in series.
2. the method for claim 1, is characterized in that, described contact hole is surrounded by place completely.
3. the method for claim 1, is characterized in that, described newly-increased place is made into the rectangle that the length of side is 2-5 micron.
4. the method for claim 1, is characterized in that, described contact hole is made into the rectangle that the length of side is 0.25-3 micron.
5. the method as described in claim 1 ~ 4 any one, is characterized in that, by aluminium or copper, makes described metal wire.
6. an electronic product, is characterized in that, comprising:
The LDMOS drain region, source region and the polysilicon gate that adopt interdigitated planar structure to make;
Newly-increased place, is located in the source region between every two adjacent drain regions;
Polysilicon layer projection, is arranged in described newly-increased place, is connected, and is positioned at interval setpoint distance on polysilicon gate, and run through the source region adjacent with polysilicon gate and extend to the place outside source region through source region with polysilicon gate;
Contact hole, is positioned in each polysilicon layer projection;
Metal wire, for being together in series the contact hole in all polysilicon layer projections.
7. product as claimed in claim 6, is characterized in that, described contact hole is surrounded by place completely.
8. product as claimed in claim 6, is characterized in that, described newly-increased place is that the length of side is the rectangle of 2-5 micron.
9. product as claimed in claim 6, is characterized in that, described contact hole is that the length of side is the rectangle of 0.25-3 micron.
10. the product as described in claim 6 ~ 9 any one, is characterized in that, the material of described metal wire is aluminium or copper.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047125A (en) * | 2015-09-18 | 2015-11-11 | 京东方科技集团股份有限公司 | Shifting register, repairing method thereof, grid integrated drive circuit and corresponding device |
| CN110690276A (en) * | 2018-07-05 | 2020-01-14 | 英飞凌科技股份有限公司 | Power semiconductor device |
| CN113948571A (en) * | 2021-10-18 | 2022-01-18 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
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| US20060091480A1 (en) * | 2004-11-03 | 2006-05-04 | Desko John C | Lateral double diffused MOS transistors |
| US20100207207A1 (en) * | 2009-02-16 | 2010-08-19 | Vanguard International Semiconductor | Semiconductor structure |
| KR20110037489A (en) * | 2009-10-07 | 2011-04-13 | 전북대학교산학협력단 | Laterally diffused metal oxide semiconductor transistor |
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