CN109103177B - Power device structure integrating Schottky junction and manufacturing method thereof - Google Patents

Power device structure integrating Schottky junction and manufacturing method thereof Download PDF

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CN109103177B
CN109103177B CN201710475113.0A CN201710475113A CN109103177B CN 109103177 B CN109103177 B CN 109103177B CN 201710475113 A CN201710475113 A CN 201710475113A CN 109103177 B CN109103177 B CN 109103177B
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groove
layer
schottky junction
power device
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CN109103177A (en
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陈茜
蒋建
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China Resources Microelectronics Chongqing Ltd
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China Resources Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]

Abstract

The invention provides a power device structure integrating a Schottky junction and a manufacturing method thereof, comprising the following steps: the N-type epitaxial layer is provided with a first groove, a second groove and a third groove, wherein an oxide layer is formed on the surface of the first groove, a Schottky junction is formed at the bottom of the first groove, and a Schottky metal layer connected with the Schottky junction is arranged in the second groove; insulating material and gate dielectric layer; interconnected polysilicon; a P-type body region and an N-type source region; a source metal layer and a gate metal layer. The invention adopts a full trench structure, the upper part of the gate polysilicon is isolated by the oxide film and led out to the gate electrode by another trench, thus a separate electrode contact photoetching process is not needed, the problems of threshold Vt drift and the like caused by electrode contact alignment deviation of the traditional trench type power device are avoided, the pin distance of the power device is effectively reduced, and higher device density can be realized.

Description

Power device structure integrating Schottky junction and manufacturing method thereof
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a power device structure integrated with a Schottky junction and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, a power device is widely applied to the fields of disk drive, automobile electronics and the like as a novel device. Power devices need to be able to withstand large voltages, currents and power loads. However, the conventional MOS transistor and other devices cannot meet the above requirements, and therefore, various power devices are focused on to meet the application requirements.
The conventional schottky diode is generally a metal-semiconductor device which is made of noble metal (gold, silver, aluminum, platinum, etc.) as a positive electrode, an N-type semiconductor as a negative electrode, and a rectifying characteristic utilizing a potential barrier formed on a contact surface of the two. Since a large number of electrons exist in the N-type semiconductor and only a very small amount of free electrons exist in the noble metal, electrons diffuse from the N-type semiconductor having a high concentration to the noble metal having a low concentration. Obviously, there is no hole in the noble metal, i.e., there is no diffusion movement of holes from the metal to the N-type semiconductor. As electrons continue to diffuse from the N-type semiconductor to the noble metal, the electron concentration at the surface of the N-type semiconductor gradually decreases, and the surface neutrality is broken, thus forming a potential barrier with the electric field direction of the N-type semiconductor toward the noble metal. However, under the action of the electric field, electrons in the noble metal also generate drift motion from the noble metal to the N-type semiconductor, thereby weakening the electric field formed due to the diffusion motion. After a space charge region with a certain width is established, electron drift movement caused by an electric field and electron diffusion movement caused by different concentrations reach relative balance, and a Schottky barrier is formed.
Therefore, the schottky diode is a majority carrier device working based on the rectifying characteristic of metal and semiconductor contact, has the characteristics of low forward voltage, low reverse recovery current, high switching speed, low noise coefficient, low power consumption and the like, and is widely applied to the fields of switching power supplies, frequency converters, drivers and the like at present.
At present, the power device and the schottky are integrated mainly to protect the source terminal (source) and the drain terminal (drain) of the power device, and the existing power device and schottky are integrated in the following two ways:
the first way is: the power device and the Schottky device are respectively independent chip devices and are integrated together through a packaging connecting wire during packaging, the method needs to independently provide two devices, and the two devices are integrated together through a back-end process such as packaging, so that the cost is high.
The second way is: the power device and the schottky device are formed together on one chip in the manufacturing process, but the conventional integration mode is the schottky device of the integrated plane of the power device at present, the schottky device almost occupies half of the total area of the chip of the device, and the area of the device is not reduced.
Based on the foregoing, it is necessary to provide a power device structure integrating schottky junctions and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to providing a power device structure integrated with a schottky junction and a method for manufacturing the same, which are used for solving the problems of high integration cost and large area of the schottky junction and the power device in the prior art, so that the schottky junction and the power device are well integrated together, the protection effect of the schottky junction on the source terminal and the drain terminal of the power device is ensured, and meanwhile, the area of a chip is not occupied, so that the area of the device can be reduced, and the cost is reduced.
To achieve the above and other related objects, the present invention provides a power device structure integrating a schottky junction, including: the semiconductor device comprises an N-type epitaxial layer, wherein a first groove, a second groove and a third groove which are mutually communicated are formed in the N-type epitaxial layer; the oxide layer is formed on the surfaces of the first groove, the second groove and the third groove, the oxide layer at the bottom of the first groove is removed, and a P-type doped region is formed in the N-type epitaxial layer at the bottom of the first groove; the metal silicide is formed at the bottom of the first groove to form a Schottky junction, a Schottky metal layer connected with the Schottky junction is filled in the second groove, and the Schottky metal layer in the second groove is used as a leading-out end of the Schottky junction; the first groove and the third groove are filled with insulating materials, part of the insulating materials in the first groove and the third groove are removed to form a fourth groove and a fifth groove which are connected with each other respectively, and part of the insulating materials are reserved on the metal silicide; the gate dielectric layer is formed on the side walls of the fourth groove and the fifth groove; the interconnected polysilicon is filled in the fourth groove and the fifth groove, an insulating layer is formed on the surface of the polysilicon of the fourth groove, and the polysilicon of the fifth groove is used as a gate leading-out end; the P-type body region is formed on the surface layer of the epitaxial layer; an N-type source region formed in the P-type body region; the source electrode metal layer is contacted with the gate leading-out end, and the source electrode metal layer is contacted with the N-type source region and the leading-out end of the Schottky junction.
Preferably, the thickness of the oxide layer is 50 nm-1000 nm.
Preferably, the doping concentration of the N-type epitaxial layer is 1E 15-1E 16/cm 3 The doping concentration of the P-type doping region is 1E 14-1E 15/cm 3 The doping concentration of the P-type body region is 1E 14-1E 16/cm 3 The doping concentration of the N-type source region is 1E 17-1E 19/cm 3 。
Preferably, the metal material of the metal silicide includes one of Pt, ni, ti, cr, W, mo and Co.
Preferably, the thickness of the insulating material remained on the metal silicide ranges from 300 nm to 500nm.
Preferably, the source metal layer and the gate metal layer each include one of an Al layer, an AlCu layer, an AlSiCu layer, a TiN/AlSiCu/TiN/Ti/Ni/Ag stack, a TiN/AlSiCu stack, a TiN/AlCu/TiN/Ti/Ni/Ag stack, a TiN/AlCu stack, a TiN/AlSi stack, or a TiN/Al stack.
The invention also provides a manufacturing method of the power device structure integrating the Schottky junction, which comprises the following steps: 1) Forming a first groove, a second groove and a third groove which are mutually communicated on the N-type epitaxial layer; 2) Forming an oxide layer on the surfaces of the first groove, the second groove and the third groove; 3) Removing the oxide layer at the bottom of the first groove, and performing P-type ion implantation on the exposed N-type epitaxial layer to form a P-type doped region; 4) Forming an interconnected Schottky metal layer at the bottom of the first groove and in the second groove, and annealing to form a metal silicide at the bottom of the first groove so as to form a Schottky junction, wherein the Schottky metal layer in the second groove is used as a leading-out end of the Schottky junction; 5) Filling insulating materials in the first groove and the third groove; 6) Etching to remove part of the insulating materials in the first groove and the third groove to form a plurality of interconnected fourth grooves and fifth grooves respectively, wherein part of the insulating materials are reserved on the metal silicide; 7) Forming gate dielectric layers on the side walls of the fourth groove and the fifth groove, filling interconnected polysilicon in the fourth groove and the fifth groove, forming an insulating layer on the surface of the polysilicon of the fourth groove, and taking the polysilicon of the fifth groove as a gate leading-out end; 8) Forming a P-type body region on the surface layer of the epitaxial layer, and forming an N-type source region in the P-type body region; 9) And manufacturing a source electrode metal layer and a gate electrode metal layer, wherein the gate electrode metal layer is contacted with the gate electrode leading-out end, and the source electrode metal layer is contacted with the N-type source region and the leading-out end of the Schottky junction.
Preferably, in step 2), an oxide layer is formed on the surfaces of the first trench, the second trench and the third trench by a thermal oxidation method, and the thickness of the oxide layer is 50 nm-1000 nm.
Preferably, in step 3), the P-type ion comprises B or BF 2 The dosage of the P-type ion implantation is 1E 11-1E 13/cm 2 。
Preferably, step 4) comprises: 4-1) forming an interconnected Schottky metal layer in the first groove and the second groove by adopting a sputtering process or a deposition process, wherein the material of the Schottky metal layer comprises one of Pt, ni, ti, cr, W, mo and Co; 4-2) forming metal silicide at the bottom of the first groove by adopting a rapid heat treatment method or a furnace annealing method so as to form a Schottky junction, wherein the Schottky metal layer in the second groove is used as a leading-out end of the Schottky junction.
Preferably, in step 5), silicon dioxide is filled in the first groove and the third groove by adopting a high density plasma chemical vapor deposition (HDP) process or a tetraethyl orthosilicate (TEOS) hydrolytic polycondensation process.
Preferably, in step 6), the thickness of the insulating material remained on the metal silicide ranges from 300 nm to 500nm.
As described above, the power device structure integrated with schottky junction and the manufacturing method thereof of the present invention have the following beneficial effects:
the Schottky junction is integrated at the bottom of the groove of the power device, the Schottky metal is led out through the groove and is connected with the source metal of the power device, and the grid region of the whole power device is led out to the grid electrode through the groove.
On the basis of the traditional groove type power device, the invention adopts a full groove structure, the upper part of the groove is isolated by the oxide film in the sinking channel groove of the gate polysilicon and is led out to the gate electrode by another groove, thus a separate electrode contact (contact) photoetching process is not needed, the problems of threshold Vt drift and the like caused by the deviation of electrode contact alignment of the traditional groove type power device are avoided, the pitch (pitch) of the power device is effectively reduced, and higher device density can be realized.
Drawings
Fig. 1 to 12 are schematic structural views showing steps of a method for manufacturing an integrated schottky junction power device structure according to the present invention, and fig. 10 is a schematic structural view showing the integrated schottky junction power device structure according to the present invention.
Description of element reference numerals
101 N-type epitaxial layer
102. First groove
103. Second groove
104. Third groove
105. Oxide layer
106 P-type doped region
107. Schottky metal layer
108. Metal silicide
109. Insulating material
110. Fourth groove
111. Fifth groove
112. Gate dielectric layer
113. Polycrystalline silicon
114 P-type body region
115 N-type source region
116. Source electrode metal layer
117. Gate metal layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-12. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 12, the present embodiment provides a method for manufacturing a power device structure integrated with a schottky junction, the method comprising the steps of:
as shown in fig. 1 to 2, first, step 1) is performed to form a first trench 102, a second trench 103, and a third trench 104, which are mutually penetrated, on an N-type epitaxial layer 101.
As an example, the N-type epitaxial layer 101 is an N-type lightly doped silicon epitaxial layer. In this embodiment, the thickness of the lightly N-doped silicon epitaxial layer is between 2.5 and 30 μm, and the doping concentration is about 1E 15-1E 16/cm 3 Between them. The first trench 102 and the second trench 103 and the third trench 104 are all prepared in the silicon epitaxial layer.
In this embodiment, the first trench 102, the second trench 103 and the third trench 104 are mutually communicated, as shown in fig. 2, so that the subsequent schottky junction and the gate of the transistor can be led out through the trench, and the photolithography process of an additional contact region is not required, thereby greatly saving the process cost.
As an example, the first, second and third trenches 102, 103 and 104 have a width of 0.2 to 1 μm and a depth of 2.5 to 10 μm, and specifically, the first, second and third trenches 102, 103 and 104 have a width of 0.5 μm and a depth of 5 μm. The planar shape of the first groove 102 may be a well shape, a continuous elongated shape, a discontinuous elongated shape, or a sealed rectangular ring, a circular ring, or the like. The second trenches 103 and the third trenches 104 are respectively located in peripheral regions of the plurality of first trenches 102.
As shown in fig. 3, step 2) is then performed to form an oxide layer 105 on the surfaces of the first trench 102, the second trench 103 and the third trench 104.
As an example, in step 2), an oxide layer 105 is formed on the surfaces of the first trench 102, the second trench 103 and the third trench 104 by a thermal oxidation method, and in this embodiment, the thermal oxidation method is performed in a thermal furnace tube, and the thickness of the oxide layer 105 is 50nm to 1000nm.
As shown in fig. 4, step 3) is performed, the oxide layer 105 at the bottom of the first trench 102 is removed, and P-type ion implantation is performed on the exposed N-type epitaxial layer 101 to form a P-type doped region 106.
In step 3), the oxide layer 105 at the bottom of the first trench 102 is removed by dry etching, and the P-type ions include B or BF 2 The dosage of the P-type ion implantation is 1E 11-1E 13/cm 2 。
As shown in fig. 5, step 4) is performed, forming an interconnected schottky metal layer 107 at the bottom of the first trench 102 and in the second trench 103, and annealing to form a metal silicide 108 at the bottom of the first trench 102, so as to form a schottky junction, wherein the schottky metal layer 107 in the second trench 103 is used as a leading-out terminal of the schottky junction;
as an example, step 4) comprises:
step 4-1), forming an interconnected schottky metal layer 107 in the first trench 102 and the second trench 103 by adopting a sputtering process or a deposition process, wherein the material of the schottky metal layer 107 comprises one of Pt, ni, ti, cr, W, mo and Co;
step 4-2), a rapid thermal processing method or a furnace annealing method is adopted to form a metal silicide 108 at the bottom of the first trench 102 so as to form a schottky junction, and the schottky metal layer 107 in the second trench 103 is used as a leading-out end of the schottky junction.
As shown in fig. 6, step 5) is performed to fill the first trench 102 and the third trench 104 with an insulating material 109.
As an example, in step 5), silicon dioxide is filled in the first trench 102 and the third trench 104 by using a high density plasma chemical vapor deposition (HDP) process or a tetraethyl orthosilicate (TEOS) hydrolytic polycondensation process. In this embodiment, the first trench 102 and the third trench 104 are filled with silicon dioxide by using a high density plasma chemical vapor deposition (HDP) process.
As shown in fig. 7, step 6) is performed, and a portion of the insulating material 109 in the first trench 102 and the third trench 104 is etched to form a plurality of interconnected fourth trenches 110 and fifth trenches 111, respectively, where a portion of the insulating material 109 remains on the metal silicide 108 as isolation between the schottky junction and the subsequent polysilicon 113. .
As an example, in step 6), the thickness of the insulating material 109 remaining on the metal silicide 108 ranges from 300 to 500nm.
As shown in fig. 8, step 7) is performed, a gate dielectric layer 112 is formed on the sidewalls of the fourth trench 110 and the fifth trench 111, the fourth trench 110 and the fifth trench 111 are filled with the polysilicon 113, an insulating layer is formed on the surface of the polysilicon 113 in the fourth trench 110, and the polysilicon 113 in the fifth trench 111 is used as a gate lead-out terminal.
For example, a thermal oxidation process is used to form a gate dielectric layer 112 on the sidewalls of the fourth trench 110 and the fifth trench 111, and then a chemical vapor deposition process is used to fill the fourth trench 110 and the fifth trench 111 with the polysilicon 113 interconnected, wherein the doping concentration of the polysilicon 113 is 10 19 ～10 21 /cm 3 . And then forming an insulating layer on the surface of the polysilicon 113 of the fourth trench 110 by adopting a thermal oxidation process, wherein the polysilicon 113 of the fifth trench 111 is used as a gate leading-out terminal.
As shown in fig. 9, step 8) is performed to form a P-type body region 114 on the surface of the epitaxial layer, and an N-type source region 115 is formed in the P-type body region 114.
By way of example, the doping concentration of the P-type body region 114 is 1E 14-1E 16/cm 3 The doping concentration of the N-type source region 115 is 1E 17-1E 19/cm 3 。
As shown in fig. 10 to 12, step 9) is finally performed to produce a source metal layer 116 and a gate metal layer 117, the gate metal layer being in contact with the gate terminal, and the source metal layer 116 being in contact with the N-type source region 115 and the terminal of the schottky junction.
As an example, the source metal layer 116 and the gate metal layer 117 include one of an Al layer, an AlCu layer, an AlSiCu layer, a TiN/AlSiCu/TiN/Ti/Ni/Ag stack, a TiN/AlSiCu stack, a TiN/AlCu/TiN/Ti/Ni/Ag stack, a TiN/AlCu stack, a TiN/AlSi stack, or a TiN/Al stack, respectively.
As an example, the layout of the source metal layer 116 and the gate metal layer 117 is as shown in fig. 11 and 12, fig. 11 shows that the gate metal layer 117 is disposed on one corner of the device and isolated from the source metal layer 116, and fig. 12 shows that the gate metal layer 117 is disposed at the center of one side of the device and isolated from the source metal layer 116. By arranging different gate metal layers 117 and source metal layers 116, the packaging requirements of more devices can be met, so that the application range of the power device is widened.
The Schottky junction is integrated at the bottom of the groove of the power device, the Schottky metal is led out through the groove and is connected with the source metal of the power device, and the grid region of the whole power device is led out to the grid electrode through the groove.
On the basis of the traditional trench type power device, the full trench structure is adopted, the gate polysilicon 113 is sunk into the trench, the upper surface is isolated by the oxide film and is led out to the gate electrode by the other trench, so that a separate electrode contact (contact) photoetching process is not needed, the problems of threshold Vt drift and the like caused by electrode contact alignment deviation of the traditional trench type power device are avoided, the pitch (pitch) of the power device is effectively reduced, and higher device density can be realized.
As shown in fig. 11, the present embodiment further provides a power device structure integrating schottky junctions, where the power device structure includes: an N-type epitaxial layer 101, wherein a first trench 102, a second trench 103 and a third trench 104 are formed in the N-type epitaxial layer 101; an oxide layer 105 formed on the surfaces of the first trench 102, the second trench 103 and the third trench 104, wherein the oxide layer 105 at the bottom of the first trench 102 is removed, and a P-type doped region 106 is formed in the N-type epitaxial layer 101 at the bottom of the first trench 102; a metal silicide 108 formed at the bottom of the first trench 102 to form a schottky junction, wherein the second trench 103 is filled with a schottky metal layer 107 connected with the schottky junction, and the schottky metal layer 107 in the second trench 103 is used as a leading-out terminal of the schottky junction; an insulating material 109 filled in the first trench 102 and the third trench 104, wherein a portion of the insulating material 109 in the first trench 102 and the third trench 104 is removed to form a fourth trench 110 and a fifth trench 111, respectively, of the plurality of interconnects, and a portion of the insulating material 109 remains on the metal silicide 108; a gate dielectric layer 112 formed on the sidewalls of the fourth trench 110 and the fifth trench 111; an interconnected polysilicon 113 filled in the fourth trench 110 and the fifth trench 111, wherein an insulating layer is formed on the surface of the polysilicon 113 in the fourth trench 110, and the polysilicon 113 in the fifth trench 111 is used as a gate lead-out terminal; a P-type body region 114 formed on the surface of the epitaxial layer; an N-type source region 115 formed in the P-type body region 114; a source metal layer 116 and a gate metal layer 117, the gate metal layer being in contact with the gate terminal, the source metal layer 116 being in contact with the N-type source region 115 and the terminal of the schottky junction.
The oxide layer 105 has a thickness of 50nm to 1000nm as an example.
As an example, the doping concentration of the N-type epitaxial layer 101 is 1E 15-1E 16/cm 3 The doping concentration of the P-type doped region 106 is 1E 14-1E 15/cm 3 The doping concentration of the P-type body region 114 is 1E 14-1E 16/cm 3 The doping concentration of the N-type source region 115 is 1E 17-1E 19/cm 3 。
As an example, the metal material of the metal silicide 108 includes one of Pt, ni, ti, cr, W, mo and Co.
As an example, the thickness of the insulating material 109 remaining on the metal silicide 108 ranges from 300 to 500nm.
As an example, the source metal layer 116 and the gate metal layer 117 include one of an Al layer, an AlCu layer, an AlSiCu layer, a TiN/AlSiCu/TiN/Ti/Ni/Ag stack, a TiN/AlSiCu stack, a TiN/AlCu/TiN/Ti/Ni/Ag stack, a TiN/AlCu stack, a TiN/AlSi stack, or a TiN/Al stack, respectively.
As an example, the layout of the source metal layer 116 and the gate metal layer 117 is as shown in fig. 11 and 12, fig. 11 shows that the gate metal layer 117 is disposed on one corner of the device and isolated from the source metal layer 116, and fig. 12 shows that the gate metal layer 117 is disposed at the center of one side of the device and isolated from the source metal layer 116. By arranging different gate metal layers 117 and source metal layers 116, the packaging requirements of more devices can be met, so that the application range of the power device is widened.
As described above, the power device structure integrated with schottky junction and the manufacturing method thereof of the present invention have the following beneficial effects:
the Schottky junction is integrated at the bottom of the groove of the power device, the Schottky metal is led out through the groove and is connected with the source metal of the power device, and the grid region of the whole power device is led out to the grid electrode through the groove.
On the basis of the traditional trench type power device, the full trench structure is adopted, the gate polysilicon 113 is sunk into the trench, the upper surface is isolated by the oxide film and is led out to the gate electrode by the other trench, so that a separate electrode contact (contact) photoetching process is not needed, the problems of threshold Vt drift and the like caused by electrode contact alignment deviation of the traditional trench type power device are avoided, the pitch (pitch) of the power device is effectively reduced, and higher device density can be realized.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (12)

1. A power device structure integrating a schottky junction, the power device structure comprising:
the semiconductor device comprises an N-type epitaxial layer, wherein a first groove, a second groove and a third groove which are mutually communicated are formed in the N-type epitaxial layer;
the oxide layer is formed on the surfaces of the first groove, the second groove and the third groove, the oxide layer at the bottom of the first groove is removed, and a P-type doped region is formed in the N-type epitaxial layer at the bottom of the first groove;
the metal silicide is formed at the bottom of the first groove to form a Schottky junction, a Schottky metal layer connected with the Schottky junction is filled in the second groove, and the Schottky metal layer in the second groove is used as a leading-out end of the Schottky junction;
the first groove and the third groove are filled with insulating materials, part of the insulating materials in the first groove and the third groove are removed to form a fourth groove and a fifth groove which are connected with each other respectively, and part of the insulating materials are reserved on the metal silicide;
the gate dielectric layer is formed on the side walls of the fourth groove and the fifth groove;
the interconnected polysilicon is filled in the fourth groove and the fifth groove, an insulating layer is formed on the surface of the polysilicon of the fourth groove, and the polysilicon of the fifth groove is used as a gate leading-out end;
the P-type body region is formed on the surface layer of the epitaxial layer;
an N-type source region formed in the P-type body region;
the source electrode metal layer is contacted with the gate leading-out end, and the source electrode metal layer is contacted with the N-type source region and the leading-out end of the Schottky junction.
2. The schottky junction integrated power device structure of claim 1 wherein: the thickness of the oxide layer is 50 nm-1000 nm.
3. The schottky junction integrated power device structure of claim 1 wherein: the doping concentration of the N-type epitaxial layer is 1E 15-1E 16/cm 3 The doping concentration of the P-type doping region is 1E 14-1E 15/cm 3 The doping concentration of the P-type body region is 1E 14-1E 16/cm 3 The doping concentration of the N-type source region is 1E 17-1E 19/cm 3 。
4. The schottky junction integrated power device structure of claim 1 wherein: the metal material of the metal silicide comprises one of Pt, ni, ti, cr, W, mo and Co.
5. The schottky junction integrated power device structure of claim 1 wherein: the thickness range of the insulating material remained on the metal silicide is 300-500 nm.
6. The schottky junction integrated power device structure of claim 1 wherein: the source metal layer and the gate metal layer respectively comprise one of an Al layer, an AlCu layer, an AlSiCu layer, a TiN/AlSiCu/TiN/Ti/Ni/Ag lamination, a TiN/AlSiCu lamination, a TiN/AlCu/TiN/Ti/Ni/Ag lamination, a TiN/AlCu lamination, a TiN/AlSi lamination or a TiN/Al lamination.
7. A method of fabricating a schottky junction integrated power device structure, comprising:
1) Forming a first groove, a second groove and a third groove which are mutually communicated on the N-type epitaxial layer;
2) Forming an oxide layer on the surfaces of the first groove, the second groove and the third groove;
3) Removing the oxide layer at the bottom of the first groove, and performing P-type ion implantation on the exposed N-type epitaxial layer to form a P-type doped region;
4) Forming an interconnected Schottky metal layer at the bottom of the first groove and in the second groove, and annealing to form a metal silicide at the bottom of the first groove so as to form a Schottky junction, wherein the Schottky metal layer in the second groove is used as a leading-out end of the Schottky junction;
5) Filling insulating materials in the first groove and the third groove;
6) Etching to remove part of the insulating materials in the first groove and the third groove to form a plurality of interconnected fourth grooves and fifth grooves respectively, wherein part of the insulating materials are reserved on the metal silicide;
7) Forming gate dielectric layers on the side walls of the fourth groove and the fifth groove, filling interconnected polysilicon in the fourth groove and the fifth groove, forming an insulating layer on the surface of the polysilicon of the fourth groove, and taking the polysilicon of the fifth groove as a gate leading-out end;
8) Forming a P-type body region on the surface layer of the epitaxial layer, and forming an N-type source region in the P-type body region;
9) And manufacturing a source electrode metal layer and a gate electrode metal layer, wherein the gate electrode metal layer is contacted with the gate electrode leading-out end, and the source electrode metal layer is contacted with the N-type source region and the leading-out end of the Schottky junction.
8. The method for manufacturing the schottky junction integrated power device structure according to claim 7, wherein: in the step 2), an oxidation layer is formed on the surfaces of the first groove, the second groove and the third groove by adopting a thermal oxidation method, and the thickness of the oxidation layer is 50 nm-1000 nm.
9. The method for manufacturing the schottky junction integrated power device structure according to claim 7, wherein: in step 3), the P-type ions comprise B or BF 2 The dosage of the P-type ion implantation is 1E 11-1E 13/cm 2 。
10. The method for manufacturing the schottky junction integrated power device structure according to claim 7, wherein: step 4) comprises:
4-1) forming an interconnected Schottky metal layer in the first groove and the second groove by adopting a sputtering process or a deposition process, wherein the material of the Schottky metal layer comprises one of Pt, ni, ti, cr, W, mo and Co;
4-2) forming metal silicide at the bottom of the first groove by adopting a rapid heat treatment method or a furnace annealing method so as to form a Schottky junction, wherein the Schottky metal layer in the second groove is used as a leading-out end of the Schottky junction.
11. The method for manufacturing the schottky junction integrated power device structure according to claim 7, wherein: in step 5), silicon dioxide is filled in the first groove and the third groove by adopting a high-density plasma chemical vapor deposition (HDP) process or a tetraethyl orthosilicate (TEOS) hydrolytic polycondensation process.
12. The method for manufacturing the schottky junction integrated power device structure according to claim 7, wherein: in the step 6), the thickness range of the insulating material remained on the metal silicide is 300-500 nm.
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